[Qemu-commits] [qemu/qemu] 26ba00: target/arm: Don't do two-stage lookup if stage 2 i...

[Paolo Bonzini]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 26ba00cf58e9f21b08fff4c691ce7e9bb21dd123
      
https://github.com/qemu/qemu/commit/26ba00cf58e9f21b08fff4c691ce7e9bb21dd123
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-11-22 (Tue, 22 Nov 2022)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Don't do two-stage lookup if stage 2 is disabled

In get_phys_addr_with_struct(), we call get_phys_addr_twostage() if
the CPU supports EL2.  However, we don't check here that stage 2 is
actually enabled.  Instead we only check that inside
get_phys_addr_twostage() to skip stage 2 translation.  This means
that even if stage 2 is disabled we still tell the stage 1 lookup to
do its page table walks via stage 2.

This works by luck for normal CPU accesses, but it breaks for debug
accesses, which are used by the disassembler and also by semihosting
file reads and writes, because the debug case takes a different code
path inside S1_ptw_translate().

This means that setups that use semihosting for file loads are broken
(a regression since 7.1, introduced in recent ptw refactoring), and
that sometimes disassembly in debug logs reports "unable to read
memory" rather than showing the guest insns.

Fix the bug by hoisting the "is stage 2 enabled?" check up to
get_phys_addr_with_struct(), so that we handle S2 disabled the same
way we do the "no EL2" case, with a simple single stage lookup.

Reported-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221121212404.1450382-1-peter.maydell@linaro.org


  Commit: 15f8f4671afd22491ce99d28a296514717fead4f
      
https://github.com/qemu/qemu/commit/15f8f4671afd22491ce99d28a296514717fead4f
  Author: Ard Biesheuvel <ardb@kernel.org>
  Date:   2022-11-22 (Tue, 22 Nov 2022)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Use signed quantity to represent VMSAv8-64 translation level

The LPA2 extension implements 52-bit virtual addressing for 4k and 16k
translation granules, and for the former, this means an additional level
of translation is needed. This means we start counting at -1 instead of
0 when doing a walk, and so 'level' is now a signed quantity, and should
be typed as such. So turn it from uint32_t into int32_t.

This avoids a level of -1 getting misinterpreted as being >= 3, and
terminating a page table walk prematurely with a bogus output address.

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 80e99f293e22868f50163f98276e0273e0237add
      
https://github.com/qemu/qemu/commit/80e99f293e22868f50163f98276e0273e0237add
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2022-11-22 (Tue, 22 Nov 2022)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20221122' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm:
 * Fix broken 5-level pagetable handling
 * Fix debug accesses when EL2 is present

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# gpg: Signature made Tue 22 Nov 2022 11:37:44 EST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20221122' of 
https://git.linaro.org/people/pmaydell/qemu-arm:
  target/arm: Use signed quantity to represent VMSAv8-64 translation level
  target/arm: Don't do two-stage lookup if stage 2 is disabled

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


Compare: https://github.com/qemu/qemu/compare/16a550bdc0e4...80e99f293e22