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[Qemu-commits] [qemu/qemu] 3fc8f7: hw/intc: Convert the memops to with_a
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From: |
Paolo Bonzini |
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Subject: |
[Qemu-commits] [qemu/qemu] 3fc8f7: hw/intc: Convert the memops to with_attrs in Loong... |
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Date: |
Sat, 05 Nov 2022 05:25:14 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 3fc8f74b51858353356968b3d04a5cccdc547caa
https://github.com/qemu/qemu/commit/3fc8f74b51858353356968b3d04a5cccdc547caa
Author: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Date: 2022-11-04 (Fri, 04 Nov 2022)
Changed paths:
M hw/intc/loongarch_extioi.c
M hw/intc/trace-events
Log Message:
-----------
hw/intc: Convert the memops to with_attrs in LoongArch extioi
Converting the MemoryRegionOps read/write handlers to
with_attrs in LoongArch extioi emulation.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221021015307.2570844-2-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Commit: a649fffcc9589a88464474e9105798eb62023352
https://github.com/qemu/qemu/commit/a649fffcc9589a88464474e9105798eb62023352
Author: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Date: 2022-11-04 (Fri, 04 Nov 2022)
Changed paths:
M hw/intc/loongarch_extioi.c
M target/loongarch/iocsr_helper.c
Log Message:
-----------
hw/intc: Fix LoongArch extioi coreisr accessing
1. When cpu read or write extioi COREISR reg, it should access
the reg belonged to itself, so the cpu index of 's->coreisr'
is current cpu number. Using MemTxAttrs' requester_id to get
the cpu index.
2. it need not to mask 0x1f when calculate the coreisr array index.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221021015307.2570844-3-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Commit: 021836936ef90fe1e52fe7ab7b7f2bcb9a66368a
https://github.com/qemu/qemu/commit/021836936ef90fe1e52fe7ab7b7f2bcb9a66368a
Author: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Date: 2022-11-04 (Fri, 04 Nov 2022)
Changed paths:
M hw/loongarch/virt.c
M include/hw/loongarch/virt.h
Log Message:
-----------
hw/loongarch: Load FDT table into dram memory space
Load FDT table into dram memory space, and the addr is 2 MiB.
Since lowmem region starts from 0, FDT base address is located
at 2 MiB to avoid NULL pointer access.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20221028014007.2718352-2-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Commit: ca5bf7ad0222ad4a884c90a821a22000d918c54e
https://github.com/qemu/qemu/commit/ca5bf7ad0222ad4a884c90a821a22000d918c54e
Author: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Date: 2022-11-04 (Fri, 04 Nov 2022)
Changed paths:
M hw/loongarch/virt.c
M include/hw/pci-host/ls7a.h
Log Message:
-----------
hw/loongarch: Improve fdt for LoongArch virt machine
Add new items into LoongArch FDT, including rtc and uart info.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20221028014007.2718352-3-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Commit: 3dfbb6dee57f48abdc5b51edfd4dd57869d838df
https://github.com/qemu/qemu/commit/3dfbb6dee57f48abdc5b51edfd4dd57869d838df
Author: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Date: 2022-11-04 (Fri, 04 Nov 2022)
Changed paths:
M hw/loongarch/acpi-build.c
M hw/loongarch/virt.c
Log Message:
-----------
hw/loongarch: Add TPM device for LoongArch virt machine
Add TPM device for LoongArch virt machine, including
establish TPM acpi info and add TYPE_TPM_TIS_SYSBUS
to dynamic_sysbus_devices list.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20221028014007.2718352-4-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Commit: a6b129c8102668717370ec27490523fb1290ae5d
https://github.com/qemu/qemu/commit/a6b129c8102668717370ec27490523fb1290ae5d
Author: Song Gao <gaosong@loongson.cn>
Date: 2022-11-04 (Fri, 04 Nov 2022)
Changed paths:
M target/loongarch/cpu.c
M target/loongarch/cpu.h
Log Message:
-----------
target/loongarch: Add exception subcode
We need subcodes to distinguish the same excode cs->exception_indexs,
such as EXCCODE_ADEF/EXCCODE_ADEM.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20221101073210.3934280-1-gaosong@loongson.cn>
Commit: 8752b1306002237c39b3f849ca564c9db55c8b1f
https://github.com/qemu/qemu/commit/8752b1306002237c39b3f849ca564c9db55c8b1f
Author: Song Gao <gaosong@loongson.cn>
Date: 2022-11-04 (Fri, 04 Nov 2022)
Changed paths:
M target/loongarch/cpu.c
M target/loongarch/tlb_helper.c
Log Message:
-----------
target/loongarch: Fix raise_mmu_exception() set wrong exception_index
When the address is invalid address, We should set exception_index
according to MMUAccessType, and EXCCODE_ADEF need't update badinstr.
Otherwise, The system enters an infinite loop. e.g:
run test.c on system mode
test.c:
#include<stdio.h>
void (*func)(int *);
int main()
{
int i = 8;
void *ptr = (void *)0x4000000000000000;
func = ptr;
func(&i);
return 0;
}
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20221101073210.3934280-2-gaosong@loongson.cn>
Commit: b4bda2006f482f778d9dbf86038ff115fe89db92
https://github.com/qemu/qemu/commit/b4bda2006f482f778d9dbf86038ff115fe89db92
Author: Rui Wang <wangrui@loongson.cn>
Date: 2022-11-04 (Fri, 04 Nov 2022)
Changed paths:
M target/loongarch/cpu.h
M target/loongarch/insn_trans/trans_privileged.c.inc
M target/loongarch/translate.c
Log Message:
-----------
target/loongarch: Adjust the layout of hardware flags bit fields
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Rui Wang <wangrui@loongson.cn>
Message-Id: <20221104040517.222059-2-wangrui@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Commit: 2419978cb09e11bc53a07d4de5621424d2a6a86d
https://github.com/qemu/qemu/commit/2419978cb09e11bc53a07d4de5621424d2a6a86d
Author: Rui Wang <wangrui@loongson.cn>
Date: 2022-11-04 (Fri, 04 Nov 2022)
Changed paths:
M target/loongarch/cpu.c
M target/loongarch/cpu.h
M target/loongarch/insn_trans/trans_farith.c.inc
M target/loongarch/insn_trans/trans_fcmp.c.inc
M target/loongarch/insn_trans/trans_fmemory.c.inc
M target/loongarch/insn_trans/trans_fmov.c.inc
Log Message:
-----------
target/loongarch: Fix emulation of float-point disable exception
We need to emulate it to generate a floating point disable exception
when CSR.EUEN.FPE is zero.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Rui Wang <wangrui@loongson.cn>
Message-Id: <20221104040517.222059-3-wangrui@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Commit: 2b39abb2d6ed022c62eba2d124432d91c52a9d22
https://github.com/qemu/qemu/commit/2b39abb2d6ed022c62eba2d124432d91c52a9d22
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-11-04 (Fri, 04 Nov 2022)
Changed paths:
M hw/arm/boot.c
Log Message:
-----------
hw/arm/boot: Set SME and SVE EL3 vector lengths when booting kernel
When we direct boot a kernel on a CPU which emulates EL3, we need
to set up the EL3 system registers as the Linux kernel documentation
specifies:
https://www.kernel.org/doc/Documentation/arm64/booting.rst
For SVE and SME this includes:
- ZCR_EL3.LEN must be initialised to the same value for all CPUs the
kernel is executed on.
- SMCR_EL3.LEN must be initialised to the same value for all CPUs the
kernel will execute on.
Although we are technically compliant with this, the "same value" we
currently use by default is the reset value of 0. This will end up
forcing the guest kernel's SVE and SME vector length to be only the
smallest supported length.
Initialize the vector length fields to their maximum possible value,
which is 0xf. If the implementation doesn't actually support that
vector length then the effective vector length will be constrained
down to the maximum supported value at point of use.
This allows the guest to use all the vector lengths the emulated CPU
supports (by programming the _EL2 and _EL1 versions of these
registers.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221027140207.413084-2-peter.maydell@linaro.org
Commit: d7ef5e16a17c7dd068420c79fa9e893f15b4abaf
https://github.com/qemu/qemu/commit/d7ef5e16a17c7dd068420c79fa9e893f15b4abaf
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-11-04 (Fri, 04 Nov 2022)
Changed paths:
M hw/arm/boot.c
Log Message:
-----------
hw/arm/boot: Set SCR_EL3.HXEn when booting kernel
When we direct boot a kernel on a CPU which emulates EL3, we need to
set up the EL3 system registers as the Linux kernel documentation
specifies:
https://www.kernel.org/doc/Documentation/arm64/booting.rst
For CPUs with FEAT_HCX support this includes:
- SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
but we forgot to do this when implementing FEAT_HCX, which would mean
that a guest trying to access the HCRX_EL2 register would crash.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221027140207.413084-3-peter.maydell@linaro.org
Commit: 4870f38b0babe48babdce90ac8bba11d29abaf0d
https://github.com/qemu/qemu/commit/4870f38b0babe48babdce90ac8bba11d29abaf0d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-11-04 (Fri, 04 Nov 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB
The HCR_EL2.TTLB bit is supposed to trap all EL1 execution of TLB
maintenance instructions. However we have added new TLB insns for
FEAT_TLBIOS and FEAT_TLBIRANGE, and forgot to set their accessfn to
access_ttlb. Add the missing accessfns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6f2d9d74416a71dedeb1a52480e8e809e2862702
https://github.com/qemu/qemu/commit/6f2d9d74416a71dedeb1a52480e8e809e2862702
Author: Timofey Kutergin <tkutergin@gmail.com>
Date: 2022-11-04 (Fri, 04 Nov 2022)
Changed paths:
M target/arm/helper.c
M target/arm/ptw.c
Log Message:
-----------
target/arm: Fix Privileged Access Never (PAN) for aarch32
When we implemented the PAN support we theoretically wanted
to support it for both AArch32 and AArch64, but in practice
several bugs made it essentially unusable with an AArch32
guest. Fix all those problems:
- Use CPSR.PAN to check for PAN state in aarch32 mode
- throw permission fault during address translation when PAN is
enabled and kernel tries to access user acessible page
- ignore SCTLR_XP bit for armv7 and armv8 (conflicts with SCTLR_SPAN).
Signed-off-by: Timofey Kutergin <tkutergin@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221027112619.2205229-1-tkutergin@gmail.com
[PMM: tweak commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 302ad91209c5b01c091b8d2b7c2c8995837023df
https://github.com/qemu/qemu/commit/302ad91209c5b01c091b8d2b7c2c8995837023df
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-11-04 (Fri, 04 Nov 2022)
Changed paths:
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Copy the entire vector in DO_ZIP
With odd_ofs set, we weren't copying enough data.
Fixes: 09eb6d7025d1 ("target/arm: Move sve zip high_ofs into simd_data")
Reported-by: Idan Horowitz <idan.horowitz@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221031054144.3574-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 638d5dbd78ea81c943959e2f2c65c109e5278a78
https://github.com/qemu/qemu/commit/638d5dbd78ea81c943959e2f2c65c109e5278a78
Author: Ake Koomsin <ake@igel.co.jp>
Date: 2022-11-04 (Fri, 04 Nov 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Honor HCR_E2H and HCR_TGE in ats_write64()
We need to check HCR_E2H and HCR_TGE to select the right MMU index for
the correct translation regime.
To check for EL2&0 translation regime:
- For S1E0*, S1E1* and S12E* ops, check both HCR_E2H and HCR_TGE
- For S1E2* ops, check only HCR_E2H
Signed-off-by: Ake Koomsin <ake@igel.co.jp>
Message-id: 20221101064250.12444-1-ake@igel.co.jp
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cead7fa4c06087c86c67c5ce815cc1ff0bfeac3a
https://github.com/qemu/qemu/commit/cead7fa4c06087c86c67c5ce815cc1ff0bfeac3a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-11-04 (Fri, 04 Nov 2022)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Two fixes for secure ptw
Reversed the sense of non-secure in get_phys_addr_lpae,
and failed to initialize attrs.secure for ARMMMUIdx_Phys_S.
Fixes: 48da29e4 ("target/arm: Add ptw_idx to S1Translate")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1293
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7a033008cc1865bfda3f2d6b92885439ae202009
https://github.com/qemu/qemu/commit/7a033008cc1865bfda3f2d6b92885439ae202009
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-11-04 (Fri, 04 Nov 2022)
Changed paths:
M hw/intc/loongarch_extioi.c
M hw/intc/trace-events
M hw/loongarch/acpi-build.c
M hw/loongarch/virt.c
M include/hw/loongarch/virt.h
M include/hw/pci-host/ls7a.h
M target/loongarch/cpu.c
M target/loongarch/cpu.h
M target/loongarch/insn_trans/trans_farith.c.inc
M target/loongarch/insn_trans/trans_fcmp.c.inc
M target/loongarch/insn_trans/trans_fmemory.c.inc
M target/loongarch/insn_trans/trans_fmov.c.inc
M target/loongarch/insn_trans/trans_privileged.c.inc
M target/loongarch/iocsr_helper.c
M target/loongarch/tlb_helper.c
M target/loongarch/translate.c
Log Message:
-----------
Merge tag 'pull-loongarch-20221104' of https://gitlab.com/gaosong/qemu into
staging
pull-loongarch-20221104
v2:
- fix win32 build error;
- Add Rui Wang' patches.
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# =wblG
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# gpg: Signature made Fri 04 Nov 2022 05:21:52 EDT
# gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF
* tag 'pull-loongarch-20221104' of https://gitlab.com/gaosong/qemu:
target/loongarch: Fix emulation of float-point disable exception
target/loongarch: Adjust the layout of hardware flags bit fields
target/loongarch: Fix raise_mmu_exception() set wrong exception_index
target/loongarch: Add exception subcode
hw/loongarch: Add TPM device for LoongArch virt machine
hw/loongarch: Improve fdt for LoongArch virt machine
hw/loongarch: Load FDT table into dram memory space
hw/intc: Fix LoongArch extioi coreisr accessing
hw/intc: Convert the memops to with_attrs in LoongArch extioi
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 6295a58ad1b73985b9c32d184de7d2ed1fbe1774
https://github.com/qemu/qemu/commit/6295a58ad1b73985b9c32d184de7d2ed1fbe1774
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-11-04 (Fri, 04 Nov 2022)
Changed paths:
M hw/arm/boot.c
M target/arm/helper.c
M target/arm/ptw.c
M target/arm/sve_helper.c
Log Message:
-----------
Merge tag 'pull-target-arm-20221104' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Fix regression booting Trusted Firmware
* Honor HCR_E2H and HCR_TGE in ats_write64()
* Copy the entire vector in DO_ZIP
* Fix Privileged Access Never (PAN) for aarch32
* Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB
* Set SCR_EL3.HXEn when direct booting kernel
* Set SME and SVE EL3 vector lengths when direct booting kernel
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# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 04 Nov 2022 07:34:01 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20221104' of
https://git.linaro.org/people/pmaydell/qemu-arm:
target/arm: Two fixes for secure ptw
target/arm: Honor HCR_E2H and HCR_TGE in ats_write64()
target/arm: Copy the entire vector in DO_ZIP
target/arm: Fix Privileged Access Never (PAN) for aarch32
target/arm: Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB
hw/arm/boot: Set SCR_EL3.HXEn when booting kernel
hw/arm/boot: Set SME and SVE EL3 vector lengths when booting kernel
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/ece5f8374d04...6295a58ad1b7
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