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[Qemu-commits] [qemu/qemu] 9d7ccb: hw/i386/e820: remove legacy reserved
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From: |
Paolo Bonzini |
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Subject: |
[Qemu-commits] [qemu/qemu] 9d7ccb: hw/i386/e820: remove legacy reserved entries for e820 |
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Date: |
Mon, 31 Oct 2022 11:49:44 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 9d7ccb12022abb2b530f9a6142bee428fbb2e09f
https://github.com/qemu/qemu/commit/9d7ccb12022abb2b530f9a6142bee428fbb2e09f
Author: Ani Sinha <ani@anisinha.ca>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/i386/e820_memory_layout.c
M hw/i386/e820_memory_layout.h
M hw/i386/fw_cfg.c
M hw/i386/fw_cfg.h
M hw/i386/microvm.c
Log Message:
-----------
hw/i386/e820: remove legacy reserved entries for e820
e820 reserved entries were used before the dynamic entries with fw config files
were intoduced. Please see the following change:
7d67110f2d9a6("pc: add etc/e820 fw_cfg file")
Identical support was introduced into seabios as well with the following commit:
ce39bd4031820 ("Add support for etc/e820 fw_cfg file")
Both the above commits are now quite old. QEMU machines 1.7 and newer no longer
use the reserved entries. Seabios uses fw config files and
dynamic e820 entries by default and only falls back to using reserved entries
when it has to work with old qemu (versions earlier than 1.7). Please see
functions qemu_cfg_e820() and qemu_early_e820(). It is safe to remove legacy
FW_CFG_E820_TABLE and associated code now as QEMU 7.0 has deprecated i440fx
machines 1.7 and older. It would be incredibly rare to run the latest qemu
version with a very old version of seabios that did not support fw config files
for e820.
As far as I could see, edk2/ovfm never supported reserved entries and uses fw
config files from the beginning. So there should be no incompatibilities with
ovfm as well.
CC: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Ani Sinha <ani@anisinha.ca>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <20220831045311.33083-1-ani@anisinha.ca>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 99082442d26ef4dd03ef92245be01f36cf0a648a
https://github.com/qemu/qemu/commit/99082442d26ef4dd03ef92245be01f36cf0a648a
Author: Robert Hoo <robert.hu@linux.intel.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: allow SSDT changes
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Reviewed-by: Jingqi Liu <jingqi.liu@intel.com>
Message-Id: <20220922122155.1326543-2-robert.hu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 18e34ad687e9da1a871c989450aa5c5f2d24a1da
https://github.com/qemu/qemu/commit/18e34ad687e9da1a871c989450aa5c5f2d24a1da
Author: Robert Hoo <robert.hu@linux.intel.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/acpi/nvdimm.c
Log Message:
-----------
acpi/ssdt: Fix aml_or() and aml_and() in if clause
In If condition, using bitwise and/or, rather than logical and/or.
The result change in AML code:
If (((Local6 == Zero) | (Arg0 != Local0)))
==>
If (((Local6 == Zero) || (Arg0 != Local0)))
If (((ObjectType (Arg3) == 0x04) & (SizeOf (Arg3) == One)))
==>
If (((ObjectType (Arg3) == 0x04) && (SizeOf (Arg3) == One)))
Fixes: 90623ebf603 ("nvdimm acpi: check UUID")
Fixes: 4568c948066 ("nvdimm acpi: save arg3 of _DSM method")
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Reviewed-by: Jingqi Liu <jingqi.liu@intel.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20220922122155.1326543-3-robert.hu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: b69577d66ff27db9023080129d30426dafc4f64b
https://github.com/qemu/qemu/commit/b69577d66ff27db9023080129d30426dafc4f64b
Author: Robert Hoo <robert.hu@linux.intel.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/acpi/nvdimm.c
Log Message:
-----------
acpi/nvdimm: define macro for NVDIMM Device _DSM
Since it will be heavily used in next patch, define macro
NVDIMM_DEVICE_DSM_UUID for "4309AC30-0D11-11E4-9191-0800200C9A66", which is
NVDIMM device specific method uuid defined in NVDIMM _DSM interface spec,
Section 3. [1]
No functional changes in this patch.
[1] https://pmem.io/documents/IntelOptanePMem_DSM_Interface-V2.0.pdf
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20220922122155.1326543-4-robert.hu@linux.intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 2cad339064e6862bd7188ed5facdb7b8a8c1618a
https://github.com/qemu/qemu/commit/2cad339064e6862bd7188ed5facdb7b8a8c1618a
Author: Robert Hoo <robert.hu@linux.intel.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/acpi/nvdimm.c
Log Message:
-----------
acpi/nvdimm: Implement ACPI NVDIMM Label Methods
Recent ACPI spec [1] has defined NVDIMM Label Methods _LS{I,R,W}, which
deprecates corresponding _DSM Functions defined by PMEM _DSM Interface spec
[2].
Since the semantics of the new Label Methods are almost same as old _DSM
methods, the implementations here simply wrapper old ones.
ASL form diff can be found in next patch of updating golden master
binaries.
[1] ACPI Spec v6.4, 6.5.10 NVDIMM Label Methods
https://uefi.org/sites/default/files/resources/ACPI_Spec_6_4_Jan22.pdf
[2] Intel PMEM _DSM Interface Spec v2.0, 3.10 Deprecated Functions
https://pmem.io/documents/IntelOptanePMem_DSM_Interface-V2.0.pdf
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Message-Id: <20220922122155.1326543-5-robert.hu@linux.intel.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 0825f62bde198a1034c333a7e2306f675bf0caed
https://github.com/qemu/qemu/commit/0825f62bde198a1034c333a7e2306f675bf0caed
Author: Robert Hoo <robert.hu@linux.intel.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/data/acpi/pc/SSDT.dimmpxm
M tests/data/acpi/q35/SSDT.dimmpxm
M tests/data/acpi/virt/SSDT.memhp
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
test/acpi/bios-tables-test: SSDT: update golden master binaries
And empty bios-tables-test-allowed-diff.h.
Diff of ASL form, from qtest testlog.txt:
@@ -1,30 +1,30 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180629 (64-bit version)
* Copyright (c) 2000 - 2018 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/pc/SSDT.dimmpxm, Thu Sep 22 18:25:06 2022
+ * Disassembly of /tmp/aml-YYZZS1, Thu Sep 22 18:25:06 2022
*
* Original Table Header:
* Signature "SSDT"
- * Length 0x000002DE (734)
+ * Length 0x00000717 (1815)
* Revision 0x01
- * Checksum 0x56
+ * Checksum 0xBC
* OEM ID "BOCHS "
* OEM Table ID "NVDIMM"
* OEM Revision 0x00000001 (1)
* Compiler ID "BXPC"
* Compiler Version 0x00000001 (1)
*/
DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000001)
{
Scope (\_SB)
{
Device (NVDR)
{
Name (_HID, "ACPI0012" /* NVDIMM Root Device */) // _HID:
Hardware ID
Method (NCAL, 5, Serialized)
{
Local6 = MEMA /* \MEMA */
@@ -49,52 +49,52 @@
ODAT, 32736
}
If ((Arg4 == Zero))
{
Local0 = ToUUID ("2f10e7a4-9e91-11e4-89d3-123b93f75cba")
}
ElseIf ((Arg4 == 0x00010000))
{
Local0 = ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62")
}
Else
{
Local0 = ToUUID ("4309ac30-0d11-11e4-9191-0800200c9a66")
}
- If (((Local6 == Zero) | (Arg0 != Local0)))
+ If (((Local6 == Zero) || (Arg0 != Local0)))
{
If ((Arg2 == Zero))
{
Return (Buffer (One)
{
0x00
// .
})
}
Return (Buffer (One)
{
0x01 // .
})
}
HDLE = Arg4
REVS = Arg1
FUNC = Arg2
- If (((ObjectType (Arg3) == 0x04) & (SizeOf (Arg3) == One)))
+ If (((ObjectType (Arg3) == 0x04) && (SizeOf (Arg3) == One)))
{
Local2 = Arg3 [Zero]
Local3 = DerefOf (Local2)
FARG = Local3
}
NTFI = Local6
Local1 = (RLEN - 0x04)
If ((Local1 < 0x08))
{
Local2 = Zero
Name (TBUF, Buffer (One)
{
0x00 // .
})
Local7 = Buffer (Zero){}
@@ -161,45 +161,234 @@
Else
{
If ((Local1 == Zero))
{
Return (Local2)
}
Local3 += Local1
Concatenate (Local2, Local0, Local2)
}
}
}
Device (NV00)
{
Name (_ADR, One) // _ADR: Address
+ Method (_LSI, 0, Serialized) // _LSI: Label Storage
Information
+ {
+ Local0 = NCAL (ToUUID
("4309ac30-0d11-11e4-9191-0800200c9a66"), One, 0x04, Zero, One)
+ CreateDWordField (Local0, Zero, STTS)
+ CreateDWordField (Local0, 0x04, SLSA)
+ CreateDWordField (Local0, 0x08, MAXT)
+ Local1 = Package (0x03)
+ {
+ STTS,
+ SLSA,
+ MAXT
+ }
+ Return (Local1)
+ }
+
+ Method (_LSR, 2, Serialized) // _LSR: Label Storage Read
+ {
+ Name (INPT, Buffer (0x08)
+ {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 //
........
+ })
+ CreateDWordField (INPT, Zero, OFST)
+ CreateDWordField (INPT, 0x04, LEN)
+ OFST = Arg0
+ LEN = Arg1
+ Local0 = Package (0x01)
+ {
+ INPT
+ }
+ Local3 = NCAL (ToUUID
("4309ac30-0d11-11e4-9191-0800200c9a66"), One, 0x05, Local0, One)
+ CreateDWordField (Local3, Zero, STTS)
+ CreateField (Local3, 0x20, (LEN << 0x03), LDAT)
+ Name (LSA, Buffer (Zero){})
+ ToBuffer (LDAT, LSA) /* \_SB_.NVDR.NV00._LSR.LSA_ */
+ Local1 = Package (0x02)
+ {
+ STTS,
+ LSA
+ }
+ Return (Local1)
+ }
+
+ Method (_LSW, 3, Serialized) // _LSW: Label Storage Write
+ {
+ Local2 = Arg2
+ Name (INPT, Buffer (0x08)
+ {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 //
........
+ })
+ CreateDWordField (INPT, Zero, OFST)
+ CreateDWordField (INPT, 0x04, TLEN)
+ OFST = Arg0
+ TLEN = Arg1
+ Concatenate (INPT, Local2, INPT) /*
\_SB_.NVDR.NV00._LSW.INPT */
+ Local0 = Package (0x01)
+ {
+ INPT
+ }
+ Local3 = NCAL (ToUUID
("4309ac30-0d11-11e4-9191-0800200c9a66"), One, 0x06, Local0, One)
+ CreateDWordField (Local3, Zero, STTS)
+ Return (STTS) /* \_SB_.NVDR.NV00._LSW.STTS */
+ }
+
(iterates in each NV)
Message-Id: <20220922122155.1326543-6-robert.hu@linux.intel.com>
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1f50468be0729adba1265e902601317ca3d2c4dd
https://github.com/qemu/qemu/commit/1f50468be0729adba1265e902601317ca3d2c4dd
Author: Lei He <helei.sig11@bytedance.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M backends/cryptodev-builtin.c
M backends/cryptodev-vhost-user.c
M backends/cryptodev.c
M hw/virtio/virtio-crypto.c
M include/sysemu/cryptodev.h
Log Message:
-----------
virtio-crypto: Support asynchronous mode
virtio-crypto: Modify the current interface of virtio-crypto
device to support asynchronous mode.
Signed-off-by: lei he <helei.sig11@bytedance.com>
Message-Id: <20221008085030.70212-2-helei.sig11@bytedance.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 323fbe783a4140a7e0e108390ac1db0f4a98e365
https://github.com/qemu/qemu/commit/323fbe783a4140a7e0e108390ac1db0f4a98e365
Author: Lei He <helei.sig11@bytedance.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M crypto/der.c
M crypto/der.h
M tests/unit/test-crypto-der.c
Log Message:
-----------
crypto: Support DER encodings
Add encoding interfaces for DER encoding:
1. support decoding of 'bit string', 'octet string', 'object id'
and 'context specific tag' for DER encoder.
2. implemented a simple DER encoder.
3. add more testsuits for DER encoder.
Signed-off-by: lei he <helei.sig11@bytedance.com>
Message-Id: <20221008085030.70212-3-helei.sig11@bytedance.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: dcbd2ffa923d80dde6e553e643fec96da9b119a4
https://github.com/qemu/qemu/commit/dcbd2ffa923d80dde6e553e643fec96da9b119a4
Author: Lei He <helei.sig11@bytedance.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M crypto/akcipher.c
M crypto/rsakey.c
M crypto/rsakey.h
M include/crypto/akcipher.h
Log Message:
-----------
crypto: Support export akcipher to pkcs8
crypto: support export RSA private keys with PKCS#8 standard.
So that users can upload this private key to linux kernel.
Signed-off-by: lei he <helei.sig11@bytedance.com>
Message-Id: <20221008085030.70212-4-helei.sig11@bytedance.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Commit: e35898b254b153991c81de577fc7238dc592d039
https://github.com/qemu/qemu/commit/e35898b254b153991c81de577fc7238dc592d039
Author: Lei He <helei.sig11@bytedance.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
A backends/cryptodev-lkcf.c
M backends/meson.build
M include/sysemu/cryptodev.h
M qapi/qom.json
Log Message:
-----------
cryptodev: Add a lkcf-backend for cryptodev
cryptodev: Added a new type of backend named lkcf-backend for
cryptodev. This backend upload asymmetric keys to linux kernel,
and let kernel do the accelerations if possible.
The lkcf stands for Linux Kernel Cryptography Framework.
Signed-off-by: lei he <helei.sig11@bytedance.com>
Message-Id: <20221008085030.70212-5-helei.sig11@bytedance.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 04cb1feafb86ee17a4cf5bc077f6fafd99ff2bbb
https://github.com/qemu/qemu/commit/04cb1feafb86ee17a4cf5bc077f6fafd99ff2bbb
Author: Ani Sinha <ani@anisinha.ca>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
A tests/avocado/acpi-bits/bits-tests/smbios.py2
A tests/avocado/acpi-bits/bits-tests/testacpi.py2
A tests/avocado/acpi-bits/bits-tests/testcpuid.py2
Log Message:
-----------
acpi/tests/avocado/bits: initial commit of test scripts that are run by
biosbits
This is initial commit of cpuid, acpi and smbios python test scripts for
biosbits to execute. No change has been made to them from the original code
written by the biosbits author Josh Triplett. They are required to be installed
into the bits iso file and then run from within the virtual machine booted off
with biosbits iso.
The test scripts have a ".py2" extension in order to prevent avocado from
loading them. They are written in python 2.7 and are run from within bios bits.
There is no need for avocado to try to load them and call out errors on python3
specific syntaxes.
The original location of these tests are here:
https://github.com/biosbits/bits/blob/master/python/testacpi.py
https://github.com/biosbits/bits/blob/master/python/smbios.py
https://github.com/biosbits/bits/blob/master/python/testcpuid.py
For QEMU, we maintain a fork of the above repo here with numerious fixes:
https://gitlab.com/qemu-project/biosbits-bits
The acpi test for example is maintained here in the fork:
https://gitlab.com/qemu-project/biosbits-bits/-/raw/master/python/testacpi.py
Cc: Daniel P. Berrangé <berrange@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Maydell Peter <peter.maydell@linaro.org>
Cc: John Snow <jsnow@redhat.com>
Cc: Thomas Huth <thuth@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Michael Tsirkin <mst@redhat.com>
Signed-off-by: Ani Sinha <ani@anisinha.ca>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20221021095108.104843-2-ani@anisinha.ca>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 452b4b182ebbf0c641845ee62dfb1b012c63fed8
https://github.com/qemu/qemu/commit/452b4b182ebbf0c641845ee62dfb1b012c63fed8
Author: Ani Sinha <ani@anisinha.ca>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/avocado/acpi-bits/bits-tests/testacpi.py2
Log Message:
-----------
acpi/tests/avocado/bits: disable acpi PSS tests that are failing in biosbits
PSS tests in acpi test suite seems to be failing in biosbits. This is because
the test is unable to find PSS support in QEMU bios. Let us disable
them for now so that make check does not fail. We can fix the tests and
re-enable them later.
Example failure:
---- ACPI _PSS (Pstate) table conformance tests ----
[assert] _PSS must exist FAIL
\_SB_.CPUS.C000
No _PSS exists
Summary: 1 passed, 1 failed
---- ACPI _PSS (Pstate) runtime tests ----
[assert] _PSS must exist FAIL
\_SB_.CPUS.C000
No _PSS exists
Summary: 0 passed, 1 failed
Cc: Daniel P. Berrangé <berrange@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Maydell Peter <peter.maydell@linaro.org>
Cc: John Snow <jsnow@redhat.com>
Cc: Thomas Huth <thuth@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Michael Tsirkin <mst@redhat.com>
Signed-off-by: Ani Sinha <ani@anisinha.ca>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20221021095108.104843-4-ani@anisinha.ca>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: cdec24aa0ba47dc0c8183cbb0774ef3500f64b82
https://github.com/qemu/qemu/commit/cdec24aa0ba47dc0c8183cbb0774ef3500f64b82
Author: Ani Sinha <ani@anisinha.ca>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
A tests/avocado/acpi-bits/bits-config/bits-cfg.txt
Log Message:
-----------
acpi/tests/avocado/bits: add biosbits config file for running bios tests
This change adds initial biosbits config file that instructs biosbits to run
bios test suits in batch mode. Additionally acpi and smbios structures are also
dumped.
Cc: Daniel P. Berrangé <berrange@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Maydell Peter <peter.maydell@linaro.org>
Cc: John Snow <jsnow@redhat.com>
Cc: Thomas Huth <thuth@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Michael Tsirkin <mst@redhat.com>
Signed-off-by: Ani Sinha <ani@anisinha.ca>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20221021095108.104843-5-ani@anisinha.ca>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: cd84a7fb79822ac27fbd92275d9f16b21f97f364
https://github.com/qemu/qemu/commit/cd84a7fb79822ac27fbd92275d9f16b21f97f364
Author: Ani Sinha <ani@anisinha.ca>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
A tests/avocado/acpi-bits.py
Log Message:
-----------
acpi/tests/avocado/bits: add acpi and smbios avocado tests that uses biosbits
This introduces QEMU acpi/smbios biosbits avocado test which is run
from within the python virtual environment. When the bits tests are run, bits
binaries are downloaded from an external repo/location, bios bits iso is
regenerated containing the acpi/smbios bits tests that are maintained as a part
of the QEMU source under tests/avocado/acpi-bits/bits-test . When the VM is
spawned with the iso, it runs the tests in batch mode and the results are pushed
out from the VM to the test machine where they are analyzed by this script and
pass/fail results are reported.
Cc: Daniel P. Berrangé <berrange@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Maydell Peter <peter.maydell@linaro.org>
Cc: John Snow <jsnow@redhat.com>
Cc: Thomas Huth <thuth@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Michael Tsirkin <mst@redhat.com>
Signed-off-by: Ani Sinha <ani@anisinha.ca>
Message-Id: <20221021095108.104843-6-ani@anisinha.ca>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 9df5394710cef8a1fe68aceb7ee4f57ad2c5f7df
https://github.com/qemu/qemu/commit/9df5394710cef8a1fe68aceb7ee4f57ad2c5f7df
Author: Ani Sinha <ani@anisinha.ca>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
A docs/devel/acpi-bits.rst
M docs/devel/index-build.rst
Log Message:
-----------
acpi/tests/avocado/bits/doc: add a doc file to describe the acpi bits test
A doc file is added under docs/devel that describes the purpose of the various
test files and gives guidance to developers on where and how to make changes.
Cc: Daniel P. Berrange" <berrange@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Maydell Peter <peter.maydell@linaro.org>
Cc: John Snow <jsnow@redhat.com>
Cc: Thomas Huth <thuth@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Michael Tsirkin <mst@redhat.com>
Signed-off-by: Ani Sinha <ani@anisinha.ca>
Message-Id: <20221021095108.104843-7-ani@anisinha.ca>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 5bd148d6a7e9eae49c4c8fb8f912d618707b0576
https://github.com/qemu/qemu/commit/5bd148d6a7e9eae49c4c8fb8f912d618707b0576
Author: Ani Sinha <ani@anisinha.ca>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: add myself as the maintainer for acpi biosbits avocado tests
I wrote the biosbits avocado tests for testing QEMU's ACPI/SMBIOS implementation
and all the related changes including fixes in biosbits software itself. Making
myself as the maintainer for QEMU's biosbits related files and test scripts.
Cc: Daniel P. Berrangé <berrange@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Maydell Peter <peter.maydell@linaro.org>
Cc: John Snow <jsnow@redhat.com>
Cc: Thomas Huth <thuth@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Michael Tsirkin <mst@redhat.com>
Signed-off-by: Ani Sinha <ani@anisinha.ca>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20221021095108.104843-8-ani@anisinha.ca>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: e55083ed55f20b129491a4310a73af8405a225e3
https://github.com/qemu/qemu/commit/e55083ed55f20b129491a4310a73af8405a225e3
Author: Julia Suvorova <jusual@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/smbios/smbios.c
M hw/smbios/smbios_build.h
M include/hw/firmware/smbios.h
Log Message:
-----------
hw/smbios: add core_count2 to smbios table type 4
In order to use the increased number of cpus, we need to bring smbios
tables in line with the SMBIOS 3.0 specification. This allows us to
introduce core_count2 which acts as a duplicate of core_count if we have
fewer cores than 256, and contains the actual core number per socket if
we have more.
core_enabled2 and thread_count2 fields work the same way.
Signed-off-by: Julia Suvorova <jusual@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20220731162141.178443-2-jusual@redhat.com>
Message-Id: <20221011111731.101412-2-jusual@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1bd47298f0f0a5c00c43ff0a38939592590a3a4d
https://github.com/qemu/qemu/commit/1bd47298f0f0a5c00c43ff0a38939592590a3a4d
Author: Julia Suvorova <jusual@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
bios-tables-test: teach test to use smbios 3.0 tables
Introduce the 64-bit entry point. Since we no longer have a total
number of structures, stop checking for the new ones at the EOF
structure (type 127).
Signed-off-by: Julia Suvorova <jusual@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20220731162141.178443-3-jusual@redhat.com>
Message-Id: <20221011111731.101412-3-jusual@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: be92e1b477f159bfc7fadab9fd93fc055b2c5cc2
https://github.com/qemu/qemu/commit/be92e1b477f159bfc7fadab9fd93fc055b2c5cc2
Author: Julia Suvorova <jusual@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
A tests/data/acpi/q35/APIC.core-count2
A tests/data/acpi/q35/DSDT.core-count2
A tests/data/acpi/q35/FACP.core-count2
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: allow changes for core_count2 test
Signed-off-by: Julia Suvorova <jusual@redhat.com>
Message-Id: <20220731162141.178443-4-jusual@redhat.com>
Message-Id: <20221011111731.101412-4-jusual@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Commit: 32c00544aae47f97d53d2fcfae4889e6cb2c4fac
https://github.com/qemu/qemu/commit/32c00544aae47f97d53d2fcfae4889e6cb2c4fac
Author: Julia Suvorova <jusual@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
bios-tables-test: add test for number of cores > 255
The new test is run with a large number of cpus and checks if the
core_count field in smbios_cpu_test (structure type 4) is correct.
Choose q35 as it allows to run with -smp > 255.
Signed-off-by: Julia Suvorova <jusual@redhat.com>
Message-Id: <20220731162141.178443-5-jusual@redhat.com>
Message-Id: <20221011111731.101412-5-jusual@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Commit: 5ba217d9a12cb207a5492cd58597dbadf6218f0c
https://github.com/qemu/qemu/commit/5ba217d9a12cb207a5492cd58597dbadf6218f0c
Author: Julia Suvorova <jusual@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/data/acpi/q35/APIC.core-count2
M tests/data/acpi/q35/DSDT.core-count2
M tests/data/acpi/q35/FACP.core-count2
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: update tables for new core count test
Changes in the tables (for 275 cores):
FACP:
+ Use APIC Cluster Model (V4) : 1
APIC:
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
...
+
+[81Ch 2076 1] Subtable Type : 00 [Processor Local APIC]
+[81Dh 2077 1] Length : 08
+[81Eh 2078 1] Processor ID : FE
+[81Fh 2079 1] Local Apic ID : FE
+[820h 2080 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[824h 2084 1] Subtable Type : 09 [Processor Local x2APIC]
+[825h 2085 1] Length : 10
+[826h 2086 2] Reserved : 0000
+[828h 2088 4] Processor x2Apic ID : 000000FF
+[82Ch 2092 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+[830h 2096 4] Processor UID : 000000FF
...
DSDT:
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+ }
...
+ Processor (C0FE, 0xFE, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0xFE))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0xFE, 0xFE, 0x01, 0x00, 0x00, 0x00 //
........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0xFE)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0xFE, Arg0, Arg1, Arg2)
+ }
+ }
+
+ Device (C0FF)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID:
Hardware ID
+ Name (_UID, 0xFF) // _UID: Unique ID
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0xFF))
+ }
+
+ Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry
+ {
+ /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0xFF, 0x00, 0x00,
0x00, // ........
+ /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00
// ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0xFF)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0xFF, Arg0, Arg1, Arg2)
+ }
+ }
+
...
Signed-off-by: Julia Suvorova <jusual@redhat.com>
Message-Id: <20220731162141.178443-6-jusual@redhat.com>
Message-Id: <20221011111731.101412-6-jusual@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 6b64d095422c932aa8f83ff96158e365cc37e34a
https://github.com/qemu/qemu/commit/6b64d095422c932aa8f83ff96158e365cc37e34a
Author: Miguel Luis <miguel.luis@oracle.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: virt: allow acpi MADT and FADT changes
Step 3 from bios-tables-test.c documented procedure.
Signed-off-by: Miguel Luis <miguel.luis@oracle.com>
Message-Id: <20221011181730.10885-2-miguel.luis@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Ani Sinha <ani@anisinha.ca>
Commit: f4136e74ceac970efd330a45bb0cdd6bc19d1e1e
https://github.com/qemu/qemu/commit/f4136e74ceac970efd330a45bb0cdd6bc19d1e1e
Author: Miguel Luis <miguel.luis@oracle.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/acpi/aml-build.c
M hw/arm/virt-acpi-build.c
Log Message:
-----------
acpi: fadt: support revision 6.0 of the ACPI specification
Update the Fixed ACPI Description Table (FADT) to revision 6.0 of the ACPI
specification adding the field "Hypervisor Vendor Identity".
This field's description states the following: "64-bit identifier of hypervisor
vendor. All bytes in this field are considered part of the vendor identity.
These identifiers are defined independently by the vendors themselves,
usually following the name of the hypervisor product. Version information
should NOT be included in this field - this shall simply denote the vendor's
name or identifier. Version information can be communicated through a
supplemental vendor-specific hypervisor API. Firmware implementers would
place zero bytes into this field, denoting that no hypervisor is present in
the actual firmware."
Signed-off-by: Miguel Luis <miguel.luis@oracle.com>
Reviewed-by: Ani Sinha <ani@anisinha.ca>
Message-Id: <20221011181730.10885-3-miguel.luis@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a73c9bc76e37bb6266d72c68da9e0faec4563154
https://github.com/qemu/qemu/commit/a73c9bc76e37bb6266d72c68da9e0faec4563154
Author: Miguel Luis <miguel.luis@oracle.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/arm/virt-acpi-build.c
Log Message:
-----------
acpi: arm/virt: madt: bump to revision 4 accordingly to ACPI 6.0 Errata A
MADT has been updated with the GIC Structures from ACPI 6.0 Errata A
and so MADT revision and GICC Structure must be updated also.
Fixes: 37f33084ed2e ("acpi: arm/virt: madt: use build_append_int_noprefix() API
to compose MADT table")
Signed-off-by: Miguel Luis <miguel.luis@oracle.com>
Reviewed-by: Ani Sinha <ani@anisinha.ca>
Message-Id: <20221011181730.10885-4-miguel.luis@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 7d14200d9f0916b67fd3b8c5aadb8dd12f396502
https://github.com/qemu/qemu/commit/7d14200d9f0916b67fd3b8c5aadb8dd12f396502
Author: Miguel Luis <miguel.luis@oracle.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/data/acpi/virt/APIC
M tests/data/acpi/virt/APIC.memhp
M tests/data/acpi/virt/APIC.numamem
M tests/data/acpi/virt/FACP
M tests/data/acpi/virt/FACP.memhp
M tests/data/acpi/virt/FACP.numamem
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: virt: update ACPI MADT and FADT binaries
Step 6 & 7 of the bios-tables-test.c documented procedure.
Differences between disassembled ASL files for MADT:
@@ -11,9 +11,9 @@
*/
[000h 0000 4] Signature : "APIC" [Multiple APIC
Description Table (MADT)]
-[004h 0004 4] Table Length : 000000A8
-[008h 0008 1] Revision : 03
-[009h 0009 1] Checksum : 50
+[004h 0004 4] Table Length : 000000AC
+[008h 0008 1] Revision : 04
+[009h 0009 1] Checksum : 47
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
@@ -34,7 +34,7 @@
[041h 0065 3] Reserved : 000000
[044h 0068 1] Subtable Type : 0B [Generic Interrupt
Controller]
-[045h 0069 1] Length : 4C
+[045h 0069 1] Length : 50
[046h 0070 2] Reserved : 0000
[048h 0072 4] CPU Interface Number : 00000000
[04Ch 0076 4] Processor UID : 00000000
@@ -51,28 +51,29 @@
[07Ch 0124 4] Virtual GIC Interrupt : 00000000
[080h 0128 8] Redistributor Base Address : 0000000000000000
[088h 0136 8] ARM MPIDR : 0000000000000000
-/**** ACPI subtable terminates early - may be older version (dump table) */
+[090h 0144 1] Efficiency Class : 00
+[091h 0145 3] Reserved : 000000
-[090h 0144 1] Subtable Type : 0D [Generic MSI Frame]
-[091h 0145 1] Length : 18
-[092h 0146 2] Reserved : 0000
-[094h 0148 4] MSI Frame ID : 00000000
-[098h 0152 8] Base Address : 0000000008020000
-[0A0h 0160 4] Flags (decoded below) : 00000001
+[094h 0148 1] Subtable Type : 0D [Generic MSI Frame]
+[095h 0149 1] Length : 18
+[096h 0150 2] Reserved : 0000
+[098h 0152 4] MSI Frame ID : 00000000
+[09Ch 0156 8] Base Address : 0000000008020000
+[0A4h 0164 4] Flags (decoded below) : 00000001
Select SPI : 1
-[0A4h 0164 2] SPI Count : 0040
-[0A6h 0166 2] SPI Base : 0050
+[0A8h 0168 2] SPI Count : 0040
+[0AAh 0170 2] SPI Base : 0050
-Raw Table Data: Length 168 (0xA8)
+Raw Table Data: Length 172 (0xAC)
- 0000: 41 50 49 43 A8 00 00 00 03 50 42 4F 43 48 53 20 // APIC.....PBOCHS
+ 0000: 41 50 49 43 AC 00 00 00 04 47 42 4F 43 48 53 20 // APIC.....GBOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 00 00 00 00 00 00 00 00 0C 18 00 00 // ................
0030: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 // ................
- 0040: 02 00 00 00 0B 4C 00 00 00 00 00 00 00 00 00 00 // .....L..........
+ 0040: 02 00 00 00 0B 50 00 00 00 00 00 00 00 00 00 00 // .....P..........
0050: 01 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 // ................
0060: 00 00 00 00 00 00 01 08 00 00 00 00 00 00 04 08 // ................
0070: 00 00 00 00 00 00 03 08 00 00 00 00 00 00 00 00 // ................
0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
- 0090: 0D 18 00 00 00 00 00 00 00 00 02 08 00 00 00 00 // ................
- 00A0: 01 00 00 00 40 00 50 00 // ....@.P.
+ 0090: 00 00 00 00 0D 18 00 00 00 00 00 00 00 00 02 08 // ................
+ 00A0: 00 00 00 00 01 00 00 00 40 00 50 00 // ........@.P.
Differences between disassembled ASL files for FADT:
@@ -11,9 +11,9 @@
*/
[000h 0000 4] Signature : "FACP" [Fixed ACPI
Description Table (FADT)]
-[004h 0004 4] Table Length : 0000010C
-[008h 0008 1] Revision : 05
-[009h 0009 1] Checksum : 55
+[004h 0004 4] Table Length : 00000114
+[008h 0008 1] Revision : 06
+[009h 0009 1] Checksum : 15
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
@@ -99,7 +99,7 @@
PSCI Compliant : 1
Must use HVC for PSCI : 1
-[083h 0131 1] FADT Minor Revision : 01
+[083h 0131 1] FADT Minor Revision : 00
[084h 0132 8] FACS Address : 0000000000000000
[08Ch 0140 8] DSDT Address : 0000000000000000
[094h 0148 12] PM1A Event Block : [Generic Address Structure]
@@ -173,11 +173,11 @@
[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy]
[104h 0260 8] Address : 0000000000000000
-/**** ACPI table terminates in the middle of a data structure! (dump table) */
+[10Ch 0268 8] Hypervisor ID : 00000000554D4551
-Raw Table Data: Length 268 (0x10C)
+Raw Table Data: Length 276 (0x114)
- 0000: 46 41 43 50 0C 01 00 00 05 55 42 4F 43 48 53 20 // FACP.....UBOCHS
+ 0000: 46 41 43 50 14 01 00 00 06 15 42 4F 43 48 53 20 // FACP......BOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
@@ -185,7 +185,7 @@ Raw Table Data: Length 268 (0x10C)
0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
- 0080: 00 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0080: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
@@ -193,4 +193,5 @@ Raw Table Data: Length 268 (0x10C)
00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
- 0100: 00 00 00 00 00 00 00 00 00 00 00 00 // ............
+ 0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // ............QEMU
+ 0110: 00 00 00 00 // ....
Signed-off-by: Miguel Luis <miguel.luis@oracle.com>
Message-Id: <20221011181730.10885-5-miguel.luis@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Ani Sinha <ani@anisinha.ca>
Commit: 1e9d7f2c4d009c47b0384ba149b6e2024fa38347
https://github.com/qemu/qemu/commit/1e9d7f2c4d009c47b0384ba149b6e2024fa38347
Author: Huai-Cheng Kuo <hchkuo@avery-design.com.tw>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M MAINTAINERS
M hw/pci/meson.build
A hw/pci/pcie_doe.c
M include/hw/pci/pci_ids.h
M include/hw/pci/pcie.h
A include/hw/pci/pcie_doe.h
M include/hw/pci/pcie_regs.h
Log Message:
-----------
hw/pci: PCIe Data Object Exchange emulation
Emulation of PCIe Data Object Exchange (DOE)
PCIE Base Specification r6.0 6.3 Data Object Exchange
Supports multiple DOE PCIe Extended Capabilities for a single PCIe
device. For each capability, a static array of DOEProtocol should be passed
to pcie_doe_init(). The protocols in that array will be registered under
the DOE capability structure. For each protocol, vendor ID, type, and
corresponding callback function (handle_request()) should be implemented.
This callback function represents how the DOE request for corresponding
protocol will be handled.
pcie_doe_{read/write}_config() must be appended to corresponding PCI
device's config_read/write() handler to enable DOE access. In
pcie_doe_read_config(), false will be returned if pci_config_read()
offset is not within DOE capability range. In pcie_doe_write_config(),
the function will have no affect if the address is not within the related
DOE PCIE extended capability.
Signed-off-by: Huai-Cheng Kuo <hchkuo@avery-design.com.tw>
Signed-off-by: Chris Browy <cbrowy@avery-design.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20221014151045.24781-2-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: cc835fcc1afef08869b72047f3d44a1e28b63d75
https://github.com/qemu/qemu/commit/cc835fcc1afef08869b72047f3d44a1e28b63d75
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/mem/cxl_type3.c
Log Message:
-----------
hw/mem/cxl-type3: Add MSIX support
This will be used by several upcoming patch sets so break it out
such that it doesn't matter which one lands first.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20221014151045.24781-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: b4c41809787fb328bbed0f6500a5b9da111f5fde
https://github.com/qemu/qemu/commit/b4c41809787fb328bbed0f6500a5b9da111f5fde
Author: Huai-Cheng Kuo <hchkuo@avery-design.com.tw>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
A hw/cxl/cxl-cdat.c
M hw/cxl/meson.build
A include/hw/cxl/cxl_cdat.h
M include/hw/cxl/cxl_component.h
M include/hw/cxl/cxl_device.h
M include/hw/cxl/cxl_pci.h
Log Message:
-----------
hw/cxl/cdat: CXL CDAT Data Object Exchange implementation
The Data Object Exchange implementation of CXL Coherent Device Attribute
Table (CDAT). This implementation is referring to "Coherent Device
Attribute Table Specification, Rev. 1.03, July. 2022" and "Compute
Express Link Specification, Rev. 3.0, July. 2022"
This patch adds core support that will be shared by both
end-points and switch port emulation.
Signed-off-by: Huai-Cheng Kuo <hchkuo@avery-design.com.tw>
Signed-off-by: Chris Browy <cbrowy@avery-design.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20221014151045.24781-4-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 9a7487165649e7ca66d94d3731ff4c9d9e351462
https://github.com/qemu/qemu/commit/9a7487165649e7ca66d94d3731ff4c9d9e351462
Author: Huai-Cheng Kuo <hchkuo@avery-design.com.tw>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/mem/cxl_type3.c
Log Message:
-----------
hw/mem/cxl-type3: Add CXL CDAT Data Object Exchange
The CDAT can be specified in two ways. One is to add ",cdat=<filename>"
in "-device cxl-type3"'s command option. The file is required to provide
the whole CDAT table in binary mode. The other is to use the default
that provides some 'reasonable' numbers based on type of memory and
size.
The DOE capability supporting CDAT is added to hw/mem/cxl_type3.c with
capability offset 0x190. The config read/write to this capability range
can be generated in the OS to request the CDAT data.
Signed-off-by: Huai-Cheng Kuo <hchkuo@avery-design.com.tw>
Signed-off-by: Chris Browy <cbrowy@avery-design.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20221014151045.24781-5-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 7e918af6c6193b5e6146d5b19ad5c6ff3801dc23
https://github.com/qemu/qemu/commit/7e918af6c6193b5e6146d5b19ad5c6ff3801dc23
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/pci-bridge/cxl_upstream.c
M include/hw/cxl/cxl_cdat.h
Log Message:
-----------
hw/pci-bridge/cxl-upstream: Add a CDAT table access DOE
This Data Object Exchange Mailbox allows software to query the
latency and bandwidth between ports on the switch. For now
only provide information on routes between the upstream port and
each downstream port (not p2p).
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
--
Changes since v8: Mostly to match the type 3 equivalent
- Move enum out of function and give it a more descriptive namespace.
Message-Id: <20221014151045.24781-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a77efb5f592e0d3fd166fdb6065a9994c2f1ec53
https://github.com/qemu/qemu/commit/a77efb5f592e0d3fd166fdb6065a9994c2f1ec53
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/qtest/cxl-test.c
Log Message:
-----------
tests/qtest/cxl-test: Remove temporary directories after testing
The cxl-test leaves some temporary directories behind. Let's
clean them up now!
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20221012091435.893570-1-thuth@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Zhang Chen <chen.zhang@intel.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Commit: 89ba3956fee198d708b0d1061a1f668c111669fb
https://github.com/qemu/qemu/commit/89ba3956fee198d708b0d1061a1f668c111669fb
Author: Yajun Wu <yajunw@nvidia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/block/vhost-user-blk.c
M hw/net/vhost_net.c
Log Message:
-----------
vhost: Change the sequence of device start
This patch is part of adding vhost-user vhost_dev_start support. The
motivation is to improve backend configuration speed and reduce live
migration VM downtime.
Moving the device start routines after finishing all the necessary device
and VQ configuration, further aligning to the virtio specification for
"device initialization sequence".
Following patch will add vhost-user vhost_dev_start support.
Signed-off-by: Yajun Wu <yajunw@nvidia.com>
Acked-by: Parav Pandit <parav@nvidia.com>
Message-Id: <20221017064452.1226514-2-yajunw@nvidia.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: cf955ee34abd065c5676cc9800a73f88480d34f7
https://github.com/qemu/qemu/commit/cf955ee34abd065c5676cc9800a73f88480d34f7
Author: Yajun Wu <yajunw@nvidia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: Support vhost_dev_start
The motivation of adding vhost-user vhost_dev_start support is to
improve backend configuration speed and reduce live migration VM
downtime.
Today VQ configuration is issued one by one. For virtio net with
multi-queue support, backend needs to update RSS (Receive side
scaling) on every rx queue enable. Updating RSS is time-consuming
(typical time like 7ms).
Implement already defined vhost status and message in the vhost
specification [1].
(a) VHOST_USER_PROTOCOL_F_STATUS
(b) VHOST_USER_SET_STATUS
(c) VHOST_USER_GET_STATUS
Send message VHOST_USER_SET_STATUS with VIRTIO_CONFIG_S_DRIVER_OK for
device start and reset(0) for device stop.
On reception of the DRIVER_OK message, backend can apply the needed setting
only once (instead of incremental) and also utilize parallelism on enabling
queues.
This improves QEMU's live migration downtime with vhost user backend
implementation by great margin, specially for the large number of VQs of 64
from 800 msec to 250 msec.
[1] https://qemu-project.gitlab.io/qemu/interop/vhost-user.html
Signed-off-by: Yajun Wu <yajunw@nvidia.com>
Acked-by: Parav Pandit <parav@nvidia.com>
Message-Id: <20221017064452.1226514-3-yajunw@nvidia.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 3b5b31639242afc63d847b6dddb78f8989968410
https://github.com/qemu/qemu/commit/3b5b31639242afc63d847b6dddb78f8989968410
Author: Eric Auger <eric.auger@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/virtio/virtio-iommu-pci.c
Log Message:
-----------
hw/virtio/virtio-iommu-pci: Enforce the device is plugged on the root bus
In theory the virtio-iommu-pci could be plugged anywhere in the PCIe
topology and as long as the dt/acpi info are properly built this should
work. However at the moment we fail to do that because the
virtio-iommu-pci BDF is not computed at plug time and in that case
vms->virtio_iommu_bdf gets an incorrect value.
For instance if the virtio-iommu-pci is plugged onto a pcie root port
and the virtio-iommu protects a virtio-block-pci device the guest does
not boot.
So let's do not pretend we do support this case and fail the initialize()
if we detect the virtio-iommu-pci is plugged anywhere else than on the
root bus. Anyway this ability is not needed.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-Id: <20221012163448.121368-1-eric.auger@redhat.com>
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 32f5d865ec4ddd0c8263f43d1f4d0df9d7fb1749
https://github.com/qemu/qemu/commit/32f5d865ec4ddd0c8263f43d1f4d0df9d7fb1749
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M include/hw/virtio/virtio.h
Log Message:
-----------
virtio: re-order vm_running and use_started checks
During migration the virtio device state can be restored before we
restart the VM. As no devices can be running while the VM is paused it
makes sense to bail out early in that case.
This returns the order introduced in:
9f6bcfd99f (hw/virtio: move vm_running check to virtio_device_started)
to what virtio-sock was doing longhand.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Christian Borntraeger <borntraeger@linux.ibm.com>
Message-Id: <20221014132108.2559156-1-alex.bennee@linaro.org>
Tested-by: Christian Borntraeger <borntraeger@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 13ef7fbfb86707a3196dbcb890e039cd57a411fe
https://github.com/qemu/qemu/commit/13ef7fbfb86707a3196dbcb890e039cd57a411fe
Author: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/virtio/virtio.c
Log Message:
-----------
virtio: introduce __virtio_queue_reset()
Separate the logic of vq reset. This logic will be called directly
later.
Signed-off-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221017092558.111082-2-xuanzhuo@linux.alibaba.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: d35a4053139fe9793576aa5c5d96b502315b1840
https://github.com/qemu/qemu/commit/d35a4053139fe9793576aa5c5d96b502315b1840
Author: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/virtio/virtio.c
M include/hw/virtio/virtio.h
Log Message:
-----------
virtio: introduce virtio_queue_reset()
Introduce a new interface function virtio_queue_reset() to implement
reset for vq.
Add a new callback to VirtioDeviceClass for queue reset operation for
each child device.
Signed-off-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221017092558.111082-3-xuanzhuo@linux.alibaba.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 5bfb13a525fd3e7185f346e0a23f55eef8a5e412
https://github.com/qemu/qemu/commit/5bfb13a525fd3e7185f346e0a23f55eef8a5e412
Author: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/virtio/virtio.c
M include/hw/virtio/virtio.h
Log Message:
-----------
virtio: introduce virtio_queue_enable()
Introduce the interface queue_enable() in VirtioDeviceClass and the
fucntion virtio_queue_enable() in virtio, it can be called when
VIRTIO_PCI_COMMON_Q_ENABLE is written and related virtqueue can be
started. It only supports the devices of virtio 1 or later. The
not-supported devices can only start the virtqueue when DRIVER_OK.
Signed-off-by: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Signed-off-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221017092558.111082-4-xuanzhuo@linux.alibaba.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 42e03374329c737b0afdc37ac1f2951a32ac88d9
https://github.com/qemu/qemu/commit/42e03374329c737b0afdc37ac1f2951a32ac88d9
Author: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/core/machine.c
M include/hw/virtio/virtio.h
Log Message:
-----------
virtio: core: vq reset feature negotation support
A a new command line parameter "queue_reset" is added.
Meanwhile, the vq reset feature is disabled for pre-7.2 machines.
Signed-off-by: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Signed-off-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221017092558.111082-5-xuanzhuo@linux.alibaba.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 6d988a90544fc1364c4aa19bdc22fa9add5fa94d
https://github.com/qemu/qemu/commit/6d988a90544fc1364c4aa19bdc22fa9add5fa94d
Author: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/virtio/virtio-pci.c
M include/hw/virtio/virtio-pci.h
Log Message:
-----------
virtio-pci: support queue reset
PCI devices support vq reset.
Based on this function, the driver can adjust the size of the ring, and
quickly recycle the buffer in the ring.
The migration of the virtio devices will not happen during a reset
operation. This is becuase the global iothread lock is held. Migration
thread also needs the lock. As a result, when migration of virtio
devices starts, the 'reset' status of VirtIOPCIQueue will always be 0.
Thus, we do not need to add it in vmstate_virtio_pci_modern_queue_state.
Signed-off-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Signed-off-by: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221017092558.111082-6-xuanzhuo@linux.alibaba.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: f9d7f4f19550d3c699f89491a4d2516f195fdb06
https://github.com/qemu/qemu/commit/f9d7f4f19550d3c699f89491a4d2516f195fdb06
Author: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/virtio/virtio-pci.c
Log Message:
-----------
virtio-pci: support queue enable
PCI devices support device specific vq enable.
Based on this function, the driver can re-enable the virtqueue after the
virtqueue is reset.
Signed-off-by: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Signed-off-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221017092558.111082-7-xuanzhuo@linux.alibaba.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 00729975233efab30f4f4120c63bf691f8685e1e
https://github.com/qemu/qemu/commit/00729975233efab30f4f4120c63bf691f8685e1e
Author: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/virtio/vhost.c
M include/hw/virtio/vhost.h
Log Message:
-----------
vhost: expose vhost_virtqueue_start()
Expose vhost_virtqueue_start(), we need to use it when restarting a
virtqueue.
Signed-off-by: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Signed-off-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221017092558.111082-8-xuanzhuo@linux.alibaba.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 5b7507056e01af594204545dd954bdb29ebf265b
https://github.com/qemu/qemu/commit/5b7507056e01af594204545dd954bdb29ebf265b
Author: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/virtio/vhost.c
M include/hw/virtio/vhost.h
Log Message:
-----------
vhost: expose vhost_virtqueue_stop()
Expose vhost_virtqueue_stop(), we need to use it when resetting a
virtqueue.
Signed-off-by: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Signed-off-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221017092558.111082-9-xuanzhuo@linux.alibaba.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: f9c01e170492e91683b711c352f4dcff6a03f948
https://github.com/qemu/qemu/commit/f9c01e170492e91683b711c352f4dcff6a03f948
Author: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/net/vhost_net-stub.c
M hw/net/vhost_net.c
M include/net/vhost_net.h
Log Message:
-----------
vhost-net: vhost-kernel: introduce vhost_net_virtqueue_reset()
Introduce vhost_virtqueue_reset(), which can reset the specific
virtqueue in the device. Then it will unmap vrings and the desc
of the virtqueue.
Here we do not reuse the vhost_net_stop_one() or vhost_dev_stop(),
because they work at queue pair level. We do not use
vhost_virtqueue_stop() because it may stop the device in the
backend.
This patch only considers the case of vhost-kernel, when
NetClientDriver is NET_CLIENT_DRIVER_TAP.
Furthermore, we do not need net->nc->info->poll() because
it enables userspace datapath and we want to stop all
datapaths for this reset virtqueue here.
Signed-off-by: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Signed-off-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221017092558.111082-10-xuanzhuo@linux.alibaba.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: d051fa70e0fa02b744189bcb3a7a7c3c05bfed6d
https://github.com/qemu/qemu/commit/d051fa70e0fa02b744189bcb3a7a7c3c05bfed6d
Author: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/net/vhost_net-stub.c
M hw/net/vhost_net.c
M include/net/vhost_net.h
Log Message:
-----------
vhost-net: vhost-kernel: introduce vhost_net_virtqueue_restart()
Introduce vhost_net_virtqueue_restart(), which can restart the
specific virtqueue when the vhost net started running before.
If it fails to restart the virtqueue, the device will be stopped.
Here we do not reuse vhost_net_start_one() or vhost_dev_start()
because they work at queue pair level. The mem table and features
do not change, so we can call the vhost_virtqueue_start() to
restart a specific queue.
This patch only considers the case of vhost-kernel, when
NetClientDriver is NET_CLIENT_DRIVER_TAP.
Signed-off-by: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Signed-off-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221017092558.111082-11-xuanzhuo@linux.alibaba.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 5e300897ef5f13c785b90bad2fe028fbd403e505
https://github.com/qemu/qemu/commit/5e300897ef5f13c785b90bad2fe028fbd403e505
Author: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/net/virtio-net.c
Log Message:
-----------
virtio-net: introduce flush_or_purge_queued_packets()
Introduce the fucntion flush_or_purge_queued_packets(), it will be
used in device reset and virtqueue reset. Therefore, we extract the
common logic as a new function.
Signed-off-by: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Signed-off-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221017092558.111082-12-xuanzhuo@linux.alibaba.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 357823a2990af259b823556b750f746f7a37ca44
https://github.com/qemu/qemu/commit/357823a2990af259b823556b750f746f7a37ca44
Author: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/net/virtio-net.c
Log Message:
-----------
virtio-net: support queue reset
virtio-net and vhost-kernel implement queue reset.
Queued packets in the corresponding queue pair are flushed
or purged.
For virtio-net, userspace datapath will be disabled later in
__virtio_queue_reset(). It will set addr of vring to 0 and idx to 0.
Thus, virtio_net_receive() and virtio_net_flush_tx() will not receive
or send packets.
For vhost-net, the datapath will be disabled in vhost_net_virtqueue_reset().
Signed-off-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Signed-off-by: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221017092558.111082-13-xuanzhuo@linux.alibaba.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 081f18eb73794fcabcb5b2725cfedf285b5e27ed
https://github.com/qemu/qemu/commit/081f18eb73794fcabcb5b2725cfedf285b5e27ed
Author: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/net/virtio-net.c
Log Message:
-----------
virtio-net: support queue_enable
Support queue_enable in vhost-kernel scenario. It can be called when
a vq reset operation has been performed and the vq is restared.
It should be noted that we can restart the vq when the vhost has
already started. When launching a new vhost device, the vhost is not
started and all vqs are not initalized until VIRTIO_PCI_COMMON_STATUS
is written. Thus, we should use vhost_started to differentiate the
two cases: vq reset and device start.
Currently it only supports vhost-kernel.
Signed-off-by: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Signed-off-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221017092558.111082-14-xuanzhuo@linux.alibaba.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 117db13f11e697bf2f792ad3daa691339455df72
https://github.com/qemu/qemu/commit/117db13f11e697bf2f792ad3daa691339455df72
Author: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/net/vhost_net.c
Log Message:
-----------
vhost: vhost-kernel: enable vq reset feature
Add virtqueue reset feature for vhost-kernel.
Signed-off-by: Kangjie Xu <kangjie.xu@linux.alibaba.com>
Signed-off-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221017092558.111082-15-xuanzhuo@linux.alibaba.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 3e7ccfe4511e269cfd382a645100b4af6df970bb
https://github.com/qemu/qemu/commit/3e7ccfe4511e269cfd382a645100b4af6df970bb
Author: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/net/virtio-net.c
Log Message:
-----------
virtio-net: enable vq reset feature
Add virtqueue reset feature for virtio-net
Signed-off-by: Xuan Zhuo <xuanzhuo@linux.alibaba.com>
Message-Id: <20221017092558.111082-16-xuanzhuo@linux.alibaba.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: cede7be5e04ae9a4c1b94c74e18e02d22013e99b
https://github.com/qemu/qemu/commit/cede7be5e04ae9a4c1b94c74e18e02d22013e99b
Author: David Daney <david.daney@fungible.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/virtio/virtio-rng-pci.c
Log Message:
-----------
virtio-rng-pci: Allow setting nvectors, so we can use MSI-X
Most other virtio-pci devices allow MSI-X, let's have it for rng too.
Signed-off-by: David Daney <david.daney@fungible.com>
Reviewed-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@fungible.com>
Message-Id: <20221014160947.66105-1-philmd@fungible.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: e00bb2850819d682ee69286312a3c725ebd66640
https://github.com/qemu/qemu/commit/e00bb2850819d682ee69286312a3c725ebd66640
Author: Yajun Wu <yajunw@nvidia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/virtio/vhost-user.c
Log Message:
-----------
vhost-user: Fix out of order vring host notification handling
vhost backend sends host notification for every VQ. If backend creates
VQs in parallel, the VHOST_USER_SLAVE_VRING_HOST_NOTIFIER_MSG may
arrive to QEMU in different order than incremental queue index order.
For example VQ 1's message arrive earlier than VQ 0's:
After alloc VhostUserHostNotifier for VQ 1. GPtrArray becomes
[ nil, VQ1 pointer ]
After alloc VhostUserHostNotifier for VQ 0. GPtrArray becomes
[ VQ0 pointer, nil, VQ1 pointer ]
This is wrong. fetch_notifier will return NULL for VQ 1 in
vhost_user_get_vring_base, causes host notifier miss removal(leak).
The fix is to remove current element from GPtrArray, make the right
position for element to insert.
Fixes: 503e355465 ("virtio/vhost-user: dynamically assign
VhostUserHostNotifiers")
Signed-off-by: Yajun Wu <yajunw@nvidia.com>
Acked-by: Parav Pandit <parav@nvidia.com>
Message-Id: <20221018023651.1359420-1-yajunw@nvidia.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: af98c66d8e3a26da9fb13f45035125c625c005da
https://github.com/qemu/qemu/commit/af98c66d8e3a26da9fb13f45035125c625c005da
Author: Igor Mammedov <imammedo@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
A hw/display/acpi-vga-stub.c
A hw/display/acpi-vga.c
M hw/display/meson.build
M hw/display/vga-pci.c
M hw/display/vga_int.h
M hw/i386/acpi-build.c
Log Message:
-----------
acpi: pc: vga: use AcpiDevAmlIf interface to build VGA device descriptors
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20221017102146.2254096-2-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
NB: we do not expect any functional change in
any ACPI tables with this change. It's only a refactoring.
Reviewed-by: Ani Sinha <ani@anisinha.ca>
Commit: a6e150a38d7c625e2e6d59ed7f1314f6dabac48c
https://github.com/qemu/qemu/commit/a6e150a38d7c625e2e6d59ed7f1314f6dabac48c
Author: Igor Mammedov <imammedo@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: acpi: whitelist DSDT before generating PCI-ISA bridge AML automatically
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20221017102146.2254096-3-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 30f352eebc807b0e6973365220fa625587f9245f
https://github.com/qemu/qemu/commit/30f352eebc807b0e6973365220fa625587f9245f
Author: Igor Mammedov <imammedo@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/i386/acpi-build.c
M hw/isa/lpc_ich9.c
M hw/isa/piix3.c
Log Message:
-----------
acpi: pc/q35: drop ad-hoc PCI-ISA bridge AML routines and let bus
ennumeration generate AML
PCI-ISA bridges that are built in PIIX/Q35 are building its own AML
using AcpiDevAmlIf interface. Now build_append_pci_bus_devices()
gained AcpiDevAmlIf interface support to get AML of devices atached
to PCI slots.
So drop ad-hoc build_q35_isa_bridge()/build_piix4_isa_bridge()
and let PCI bus enumeration to include PCI-ISA bridge AML
when it's enumerated by build_append_pci_bus_devices().
AML change is mostly contextual, which moves whole ISA hierarchy
directly under PCI host bridge instead of it being described
as separate \SB.PCI0.ISA block.
Note:
If bus/slot that hosts ISA bridge has BSEL set, it will gain new
ASUN and _DMS entries (i.e. acpi-index support, but it should not
cause any functional change and that is fine from PCI Firmware
spec point of view), potentially it's possible to suppress that
by adding a flag to PCIDevice but I don't see a reason to do that
yet, I'd rather treat bridge just as any other PCI device if it's
possible.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20221017102146.2254096-4-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 0e309f05bb50da417d8d83fb9acbc9b479e6117c
https://github.com/qemu/qemu/commit/0e309f05bb50da417d8d83fb9acbc9b479e6117c
Author: Igor Mammedov <imammedo@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/data/acpi/pc/DSDT
M tests/data/acpi/pc/DSDT.acpierst
M tests/data/acpi/pc/DSDT.acpihmat
M tests/data/acpi/pc/DSDT.bridge
M tests/data/acpi/pc/DSDT.cphp
M tests/data/acpi/pc/DSDT.dimmpxm
M tests/data/acpi/pc/DSDT.hpbridge
M tests/data/acpi/pc/DSDT.hpbrroot
M tests/data/acpi/pc/DSDT.ipmikcs
M tests/data/acpi/pc/DSDT.memhp
M tests/data/acpi/pc/DSDT.nohpet
M tests/data/acpi/pc/DSDT.numamem
M tests/data/acpi/pc/DSDT.roothp
M tests/data/acpi/q35/DSDT
M tests/data/acpi/q35/DSDT.acpierst
M tests/data/acpi/q35/DSDT.acpihmat
M tests/data/acpi/q35/DSDT.applesmc
M tests/data/acpi/q35/DSDT.bridge
M tests/data/acpi/q35/DSDT.cphp
M tests/data/acpi/q35/DSDT.cxl
M tests/data/acpi/q35/DSDT.dimmpxm
M tests/data/acpi/q35/DSDT.ipmibt
M tests/data/acpi/q35/DSDT.ipmismbus
M tests/data/acpi/q35/DSDT.ivrs
M tests/data/acpi/q35/DSDT.memhp
M tests/data/acpi/q35/DSDT.mmio64
M tests/data/acpi/q35/DSDT.multi-bridge
M tests/data/acpi/q35/DSDT.nohpet
M tests/data/acpi/q35/DSDT.numamem
M tests/data/acpi/q35/DSDT.pvpanic-isa
M tests/data/acpi/q35/DSDT.tis.tpm12
M tests/data/acpi/q35/DSDT.tis.tpm2
M tests/data/acpi/q35/DSDT.viot
M tests/data/acpi/q35/DSDT.xapic
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: acpi: update expected DSDT after ISA bridge is moved directly under
PCI host bridge
example of the change for PC machine with hotplug disabled on root buss (no
BSEL case):
- Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve)
+ Field (S08.P40C, ByteAcc, NoLock, Preserve)
===
- Scope (_SB.PCI0)
- {
- Device (ISA)
- {
- Name (_ADR, 0x00010000) // _ADR: Address
- OperationRegion (P40C, PCI_Config, 0x60, 0x04)
...
- }
- }
-
Scope (_SB)
===
+ Device (S08)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ OperationRegion (P40C, PCI_Config, 0x60, 0x04)
...
+ }
+
Device (S10)
{
Name (_ADR, 0x00020000) // _ADR: Address
with hotplug enabled on root bus (i.e. bus has BSEL configured),
a following addtional entries will be seen:
+ Name (ASUN, One)
+ Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
+ {
+ Local0 = Package (0x02)
+ {
+ BSEL,
+ ASUN
+ }
+ Return (PDSM (Arg0, Arg1, Arg2, Arg3, Local0))
+ }
similar changes are expected for Q35 modulo:
- Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve)
+ Field (SF8.PIRQ, ByteAcc, NoLock, Preserve)
and bridge address
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20221017102146.2254096-5-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: ffe47355f3c4cafa248917d7d1f96ca53b477141
https://github.com/qemu/qemu/commit/ffe47355f3c4cafa248917d7d1f96ca53b477141
Author: Igor Mammedov <imammedo@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: acpi: whitelist DSDT before generating ICH9_SMB AML automatically
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20221017102146.2254096-6-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 0aedda0544dfcf592f41ee73aeeef0a7ebc89959
https://github.com/qemu/qemu/commit/0aedda0544dfcf592f41ee73aeeef0a7ebc89959
Author: Igor Mammedov <imammedo@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M include/hw/acpi/acpi_aml_interface.h
Log Message:
-----------
acpi: add get_dev_aml_func() helper
It will be used in followup commits to figure out if
device has it's own, device specific AML block.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20221017102146.2254096-7-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Ani Sinha <ani@anisinha.ca>
Commit: b58f6ddeba70d7baa01fcff3758aa12b3fa3fb9e
https://github.com/qemu/qemu/commit/b58f6ddeba70d7baa01fcff3758aa12b3fa3fb9e
Author: Igor Mammedov <imammedo@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/i386/acpi-build.c
Log Message:
-----------
acpi: enumerate SMB bridge automatically along with other PCI devices
to make that happen (bridge sits at _ADR: 0x001F0003),
relax PCI enumeration logic to include devices with *function* > 0
if device has something to say about itself (i.e. has build_dev_aml
callback set).
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20221017102146.2254096-8-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 00ffe258eb6429dff8ed93a66e1260cfad19a2ae
https://github.com/qemu/qemu/commit/00ffe258eb6429dff8ed93a66e1260cfad19a2ae
Author: Igor Mammedov <imammedo@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/data/acpi/q35/DSDT
M tests/data/acpi/q35/DSDT.acpierst
M tests/data/acpi/q35/DSDT.acpihmat
M tests/data/acpi/q35/DSDT.applesmc
M tests/data/acpi/q35/DSDT.bridge
M tests/data/acpi/q35/DSDT.cphp
M tests/data/acpi/q35/DSDT.cxl
M tests/data/acpi/q35/DSDT.dimmpxm
M tests/data/acpi/q35/DSDT.ipmibt
M tests/data/acpi/q35/DSDT.ipmismbus
M tests/data/acpi/q35/DSDT.ivrs
M tests/data/acpi/q35/DSDT.memhp
M tests/data/acpi/q35/DSDT.mmio64
M tests/data/acpi/q35/DSDT.multi-bridge
M tests/data/acpi/q35/DSDT.nohpet
M tests/data/acpi/q35/DSDT.numamem
M tests/data/acpi/q35/DSDT.pvpanic-isa
M tests/data/acpi/q35/DSDT.tis.tpm12
M tests/data/acpi/q35/DSDT.tis.tpm2
M tests/data/acpi/q35/DSDT.viot
M tests/data/acpi/q35/DSDT.xapic
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: acpi: update expected blobs
Expected change in q35 tests:
@@ -2797,14 +2797,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC
", 0x00000001)
}
}
- Scope (_SB.PCI0)
- {
- Device (SMB0)
- {
- Name (_ADR, 0x001F0003) // _ADR: Address
- }
- }
-
Scope (_SB)
{
Device (HPET)
@@ -3282,6 +3274,11 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC
", 0x00000001)
}
}
+ Device (SFB)
+ {
+ Name (_ADR, 0x001F0003) // _ADR: Address
+ }
+
Method (PCNT, 0, NotSerialized)
{
}
Also for ipmismbus test, child 'Device (MI1)' of SMB0 will be moved along with
it
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20221017102146.2254096-9-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 37cbbe34d9f34083100b95684a8576df02efc959
https://github.com/qemu/qemu/commit/37cbbe34d9f34083100b95684a8576df02efc959
Author: Igor Mammedov <imammedo@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: acpi: pc/q35 whitelist DSDT before \_GPE cleanup
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20221017102146.2254096-10-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1b578ec1e818660e0214dc34b3fb15e9456d160a
https://github.com/qemu/qemu/commit/1b578ec1e818660e0214dc34b3fb15e9456d160a
Author: Igor Mammedov <imammedo@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/i386/acpi-build.c
Log Message:
-----------
acpi: pc/35: sanitize _GPE declaration order
Move _GPE block declaration before it gets referenced by other
hotplug handlers. While at it move PCI hotplug (_E01) handler
after PCI tree description to avoid forward reference to
to not yet declared methods/devices.
PS:
Forward 'usage' usualy is fine as long as it's hidden within
method, however 'iasl' may print warnings. So be nice
to iasl/guest OS and do things in proper order.
PS2: Also follow up patches will move some of hotplug code
from PCI tree to _E01 and that also requires PCI Device
nodes build first, before Scope can reuse that from
global context.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20221017102146.2254096-11-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 628c557364d3036d985a4e258fc9d0ddf4988a22
https://github.com/qemu/qemu/commit/628c557364d3036d985a4e258fc9d0ddf4988a22
Author: Igor Mammedov <imammedo@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/data/acpi/pc/DSDT
M tests/data/acpi/pc/DSDT.acpierst
M tests/data/acpi/pc/DSDT.acpihmat
M tests/data/acpi/pc/DSDT.bridge
M tests/data/acpi/pc/DSDT.cphp
M tests/data/acpi/pc/DSDT.dimmpxm
M tests/data/acpi/pc/DSDT.hpbridge
M tests/data/acpi/pc/DSDT.hpbrroot
M tests/data/acpi/pc/DSDT.ipmikcs
M tests/data/acpi/pc/DSDT.memhp
M tests/data/acpi/pc/DSDT.nohpet
M tests/data/acpi/pc/DSDT.numamem
M tests/data/acpi/pc/DSDT.roothp
M tests/data/acpi/q35/DSDT
M tests/data/acpi/q35/DSDT.acpierst
M tests/data/acpi/q35/DSDT.acpihmat
M tests/data/acpi/q35/DSDT.applesmc
M tests/data/acpi/q35/DSDT.bridge
M tests/data/acpi/q35/DSDT.cphp
M tests/data/acpi/q35/DSDT.cxl
M tests/data/acpi/q35/DSDT.dimmpxm
M tests/data/acpi/q35/DSDT.ipmibt
M tests/data/acpi/q35/DSDT.ipmismbus
M tests/data/acpi/q35/DSDT.ivrs
M tests/data/acpi/q35/DSDT.memhp
M tests/data/acpi/q35/DSDT.mmio64
M tests/data/acpi/q35/DSDT.multi-bridge
M tests/data/acpi/q35/DSDT.nohpet
M tests/data/acpi/q35/DSDT.numamem
M tests/data/acpi/q35/DSDT.pvpanic-isa
M tests/data/acpi/q35/DSDT.tis.tpm12
M tests/data/acpi/q35/DSDT.tis.tpm2
M tests/data/acpi/q35/DSDT.viot
M tests/data/acpi/q35/DSDT.xapic
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: acpi: update expected blobs
Expected changes are:
1) Moving _GPE scope declaration achec of all _E0x methods
+ Scope (_GPE)
+ {
+ Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+ }
+
Scope (_SB)
{
Device (\_SB.PCI0.PRES)
============
\_SB.CPUS.CSCN ()
}
- Scope (_GPE)
- {
- Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
- }
2) Moving _E01 handler after PCI0 scope is defined
- Scope (_GPE)
- {
- Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware
ID
- Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE
- {
- Acquire (\_SB.PCI0.BLCK, 0xFFFF)
- \_SB.PCI0.PCNT ()
- Release (\_SB.PCI0.BLCK)
- }
- }
-
Scope (\_SB.PCI0)
{
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
=============
}
}
}
+
+ Scope (_GPE)
+ {
+ Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE
+ {
+ Acquire (\_SB.PCI0.BLCK, 0xFFFF)
+ \_SB.PCI0.PCNT ()
+ Release (\_SB.PCI0.BLCK)
+ }
+ }
}
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20221017102146.2254096-12-imammedo@redhat.com>
Commit: 99a9b6eddf24fc505ded7f246fb078c45a3218e3
https://github.com/qemu/qemu/commit/99a9b6eddf24fc505ded7f246fb078c45a3218e3
Author: Christian A. Ehrhardt <lk@c--e.de>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/acpi/erst.c
Log Message:
-----------
hw/acpi/erst.c: Fix memory handling issues
- Fix memset argument order: The second argument is
the value, the length goes last.
- Fix an integer overflow reported by Alexander Bulekov.
Both issues allow the guest to overrun the host buffer
allocated for the ERST memory device.
Cc: Eric DeVolder <eric.devolder@oracle.com
Cc: Alexander Bulekov <alxndr@bu.edu>
Cc: qemu-stable@nongnu.org
Fixes: f7e26ffa590 ("ACPI ERST: support for ACPI ERST feature")
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Christian A. Ehrhardt <lk@c--e.de>
Message-Id: <20221024154233.1043347-1-lk@c--e.de>
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1268
Reviewed-by: Alexander Bulekov <alxndr@bu.edu>
Reviewed-by: Eric DeVolder <eric.devolder@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c3ac591e625a914a6fe1f564cb70bb4099a0f4ad
https://github.com/qemu/qemu/commit/c3ac591e625a914a6fe1f564cb70bb4099a0f4ad
Author: Markus Armbruster <armbru@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add qapi/virtio.json to section "virtio"
Cc: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20221020120458.80709-1-armbru@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 0b4452fd6fd4436a026eb2554f06f875a0370c1d
https://github.com/qemu/qemu/commit/0b4452fd6fd4436a026eb2554f06f875a0370c1d
Author: Lev Kujawski <lkujaw@mailbox.org>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/qtest/libqos/pci.c
M tests/qtest/libqos/pci.h
Log Message:
-----------
qpci_device_enable: Allow for command bits hardwired to 0
Devices like the PIIX3/4 IDE controller do not support certain modes
of operation, such as memory space accesses, and indicate this lack of
support by hardwiring the applicable bits to zero. Extend the QEMU
PCI device testing framework to accommodate such devices.
* tests/qtest/libqos/pci.h: Add the command_disabled word to indicate
bits hardwired to 0.
* tests/qtest/libqos/pci.c: Verify that hardwired bits are actually
hardwired.
Signed-off-by: Lev Kujawski <lkujaw@mailbox.org>
Message-Id: <20221024094621.512806-2-lkujaw@mailbox.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a533183f0f2e1b1995f4fa6886bba992f95609c9
https://github.com/qemu/qemu/commit/a533183f0f2e1b1995f4fa6886bba992f95609c9
Author: Lev Kujawski <lkujaw@mailbox.org>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/core/machine.c
M hw/ide/piix.c
M include/hw/ide/pci.h
M tests/qtest/ide-test.c
Log Message:
-----------
hw/ide/piix: Ignore writes of hardwired PCI command register bits
One method to enable PCI bus mastering for IDE controllers, often used
by x86 firmware, is to write 0x7 to the PCI command register. Neither
the PIIX 3/4 specifications nor actual PIIX 3 hardware (a Tyan S1686D
system) permit setting the Memory Space Enable (MSE) bit, thus the
command register would be left in an unspecified state without this
patch.
* hw/core/machine.c
Facilitate migration by not masking writes to the PIIX 3/4 PCICMD
register for machine states of QEMU versions prior to 7.2.
* hw/ide/piix.c
a) Add a reference to the PIIX 4 data sheet.
b) Mask the MSE bit using the QEMU PCI device wmask field.
c) Define a new boolean property, x-filter-pcicmd, to control
whether the write mask is enabled and enable it by default
for both the PIIX 3 and PIIX 4 IDE controllers.
* include/hw/ide/pci.h
Add the boolean filter_pcicmd field to the PCIIDEState structure,
because the PIIX IDE controllers do not define their own state.
* tests/qtest/ide-test.c
Use the command_disabled field of the QPCIDevice testing model to
indicate that PCI_COMMAND_MEMORY is hardwired within PIIX 3/4 IDE
controllers.
Signed-off-by: Lev Kujawski <lkujaw@mailbox.org>
Message-Id: <20221024094621.512806-3-lkujaw@mailbox.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 707355e1c80998899e79daad32b0c7a2073d3ed8
https://github.com/qemu/qemu/commit/707355e1c80998899e79daad32b0c7a2073d3ed8
Author: Akihiko Odaki <akihiko.odaki@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/net/e1000e.c
M hw/net/rocker/rocker.c
M hw/net/vmxnet3.c
M hw/nvme/ctrl.c
M hw/pci/msix.c
M hw/rdma/vmw/pvrdma_main.c
M hw/remote/vfio-user-obj.c
M hw/virtio/virtio-pci.c
M include/hw/pci/msix.h
Log Message:
-----------
msix: Assert that specified vector is in range
There were several different ways to deal with the situation where the
vector specified for a msix function is out of bound:
- early return a function and keep progresssing
- propagate the error to the caller
- mark msix unusable
- assert it is in bound
- just ignore
An out-of-bound vector should not be specified if the device
implementation is correct so let msix functions always assert that the
specified vector is in range.
An exceptional case is virtio-pci, which allows the guest to configure
vectors. For virtio-pci, it is more appropriate to introduce its own
checks because it is sometimes too late to check the vector range in
msix functions.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20220829083524.143640-1-akihiko.odaki@daynix.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Yuval Shaia <yuval.shaia.ml@gmail.com>
Signed-off-by: Akihiko Odaki <<a href="mailto:akihiko.odaki@daynix.com";
target="_blank">akihiko.odaki@daynix.com</a>><br>
Commit: 595afe91b0eb5903118c748539f9905a5921e071
https://github.com/qemu/qemu/commit/595afe91b0eb5903118c748539f9905a5921e071
Author: Gregory Price <gourry.memverge@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/i386/pc.c
Log Message:
-----------
hw/i386/pc.c: CXL Fixed Memory Window should not reserve e820 in bios
Early-boot e820 records will be inserted by the bios/efi/early boot
software and be reported to the kernel via insert_resource. Later, when
CXL drivers iterate through the regions again, they will insert another
resource and make the RESERVED memory area a child.
This RESERVED memory area causes the memory region to become unusable,
and as a result attempting to create memory regions with
`cxl create-region ...`
Will fail due to the RESERVED area intersecting with the CXL window.
During boot the following traceback is observed:
0xffffffff81101650 in insert_resource_expand_to_fit ()
0xffffffff83d964c5 in e820__reserve_resources_late ()
0xffffffff83e03210 in pcibios_resource_survey ()
0xffffffff83e04f4a in pcibios_init ()
Which produces a call to reserve the CFMWS area:
(gdb) p *new
$54 = {start = 0x290000000, end = 0x2cfffffff, name = "Reserved",
flags = 0x200, desc = 0x7, parent = 0x0, sibling = 0x0,
child = 0x0}
Later the Kernel parses ACPI tables and reserves the exact same area as
the CXL Fixed Memory Window:
0xffffffff811016a4 in insert_resource_conflict ()
insert_resource ()
0xffffffff81a81389 in cxl_parse_cfmws ()
0xffffffff818c4a81 in call_handler ()
acpi_parse_entries_array ()
(gdb) p/x *new
$59 = {start = 0x290000000, end = 0x2cfffffff, name = "CXL Window 0",
flags = 0x200, desc = 0x0, parent = 0x0, sibling = 0x0,
child = 0x0}
This produces the following output in /proc/iomem:
590000000-68fffffff : CXL Window 0
590000000-68fffffff : Reserved
This reserved area causes `get_free_mem_region()` to fail due to a check
against `__region_intersects()`. Due to this reserved area, the
intersect check will only ever return REGION_INTERSECTS, which causes
`cxl create-region` to always fail.
Signed-off-by: Gregory Price <gregory.price@memverge.com>
Message-Id: <20221026205912.8579-1-gregory.price@memverge.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: cb1bc1c2513f78d24fd2cfef814a3754c32575bf
https://github.com/qemu/qemu/commit/cb1bc1c2513f78d24fd2cfef814a3754c32575bf
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/i386/acpi-build.c
Log Message:
-----------
hw/i386/acpi-build: Remove unused struct
Ammends commit b23046abe78f48498a423b802d6d86ba0172d57f 'pc: acpi-build:
simplify PCI bus tree generation'.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221026133110.91828-2-shentey@gmail.com>
Message-Id: <20221028103419.93398-2-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 6915c3a2176671e11cca930c526e080866c8ed14
https://github.com/qemu/qemu/commit/6915c3a2176671e11cca930c526e080866c8ed14
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/i386/acpi-build.c
Log Message:
-----------
hw/i386/acpi-build: Resolve redundant attribute
The is_piix4 attribute is set once in one location and read once in
another. Doing both in one location allows for removing the attribute
altogether.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221026133110.91828-3-shentey@gmail.com>
Message-Id: <20221028103419.93398-3-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: e7c0b8ff84d7a6327e8db23cd297281d85ada028
https://github.com/qemu/qemu/commit/e7c0b8ff84d7a6327e8db23cd297281d85ada028
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/i386/acpi-build.c
Log Message:
-----------
hw/i386/acpi-build: Resolve north rather than south bridges
The code currently assumes Q35 iff ICH9 and i440fx iff PIIX. Now that more
AML generation has been moved into the south bridges and since the
machines define themselves primarily through their north bridges, let's
switch to resolving the north bridges for AML generation instead. This
also allows for easier experimentation with different south bridges in
the "pc" machine, e.g. with PIIX4 and VT82xx.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20221028103419.93398-4-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 8dfe0c36d1d16ef3f08b6adf667ac8ed3bab4b75
https://github.com/qemu/qemu/commit/8dfe0c36d1d16ef3f08b6adf667ac8ed3bab4b75
Author: Brice Goglin <Brice.Goglin@inria.fr>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/core/machine.c
Log Message:
-----------
hmat acpi: Don't require initiator value in -numa
The "Memory Proximity Domain Attributes" structure of the ACPI HMAT
has a "Processor Proximity Domain Valid" flag that is currently
always set because Qemu -numa requires an initiator=X value
when hmat=on. Unsetting this flag allows to create more complex
memory topologies by having multiple best initiators for a single
memory target.
This patch allows -numa without initiator=X when hmat=on by keeping
the default value MAX_NODES in numa_state->nodes[i].initiator.
All places reading numa_state->nodes[i].initiator already check
whether it's different from MAX_NODES before using it.
Tested with
qemu-system-x86_64 -accel kvm \
-machine pc,hmat=on \
-drive if=pflash,format=raw,file=./OVMF.fd \
-drive media=disk,format=qcow2,file=efi.qcow2 \
-smp 4 \
-m 3G \
-object memory-backend-ram,size=1G,id=ram0 \
-object memory-backend-ram,size=1G,id=ram1 \
-object memory-backend-ram,size=1G,id=ram2 \
-numa node,nodeid=0,memdev=ram0,cpus=0-1 \
-numa node,nodeid=1,memdev=ram1,cpus=2-3 \
-numa node,nodeid=2,memdev=ram2 \
-numa
hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=10
\
-numa
hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
\
-numa
hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,latency=20
\
-numa
hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
\
-numa
hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,latency=30
\
-numa
hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
\
-numa
hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,latency=20
\
-numa
hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
\
-numa
hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,latency=10
\
-numa
hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
\
-numa
hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,latency=30
\
-numa
hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
which reports NUMA node2 at same distance from both node0 and node1 as seen in
lstopo:
Machine (2966MB total) + Package P#0
NUMANode P#2 (979MB)
Group0
NUMANode P#0 (980MB)
Core P#0 + PU P#0
Core P#1 + PU P#1
Group0
NUMANode P#1 (1007MB)
Core P#2 + PU P#2
Core P#3 + PU P#3
Before this patch, we had to add ",initiator=X" to "-numa
node,nodeid=2,memdev=ram2".
The lstopo output difference between initiator=1 and no initiator is:
@@ -1,10 +1,10 @@
Machine (2966MB total) + Package P#0
+ NUMANode P#2 (979MB)
Group0
NUMANode P#0 (980MB)
Core P#0 + PU P#0
Core P#1 + PU P#1
Group0
NUMANode P#1 (1007MB)
- NUMANode P#2 (979MB)
Core P#2 + PU P#2
Core P#3 + PU P#3
Corresponding changes in the HMAT MPDA structure:
@@ -49,10 +49,10 @@
[078h 0120 2] Structure Type : 0000 [Memory Proximity Domain
Attributes]
[07Ah 0122 2] Reserved : 0000
[07Ch 0124 4] Length : 00000028
-[080h 0128 2] Flags (decoded below) : 0001
- Processor Proximity Domain Valid : 1
+[080h 0128 2] Flags (decoded below) : 0000
+ Processor Proximity Domain Valid : 0
[082h 0130 2] Reserved1 : 0000
-[084h 0132 4] Attached Initiator Proximity Domain : 00000001
+[084h 0132 4] Attached Initiator Proximity Domain : 00000080
[088h 0136 4] Memory Proximity Domain : 00000002
[08Ch 0140 4] Reserved2 : 00000000
[090h 0144 8] Reserved3 : 0000000000000000
Final HMAT SLLB structures:
[0A0h 0160 2] Structure Type : 0001 [System Locality Latency
and Bandwidth Information]
[0A2h 0162 2] Reserved : 0000
[0A4h 0164 4] Length : 00000040
[0A8h 0168 1] Flags (decoded below) : 00
Memory Hierarchy : 0
[0A9h 0169 1] Data Type : 00
[0AAh 0170 2] Reserved1 : 0000
[0ACh 0172 4] Initiator Proximity Domains # : 00000002
[0B0h 0176 4] Target Proximity Domains # : 00000003
[0B4h 0180 4] Reserved2 : 00000000
[0B8h 0184 8] Entry Base Unit : 0000000000002710
[0C0h 0192 4] Initiator Proximity Domain List : 00000000
[0C4h 0196 4] Initiator Proximity Domain List : 00000001
[0C8h 0200 4] Target Proximity Domain List : 00000000
[0CCh 0204 4] Target Proximity Domain List : 00000001
[0D0h 0208 4] Target Proximity Domain List : 00000002
[0D4h 0212 2] Entry : 0001
[0D6h 0214 2] Entry : 0002
[0D8h 0216 2] Entry : 0003
[0DAh 0218 2] Entry : 0002
[0DCh 0220 2] Entry : 0001
[0DEh 0222 2] Entry : 0003
[0E0h 0224 2] Structure Type : 0001 [System Locality Latency
and Bandwidth Information]
[0E2h 0226 2] Reserved : 0000
[0E4h 0228 4] Length : 00000040
[0E8h 0232 1] Flags (decoded below) : 00
Memory Hierarchy : 0
[0E9h 0233 1] Data Type : 03
[0EAh 0234 2] Reserved1 : 0000
[0ECh 0236 4] Initiator Proximity Domains # : 00000002
[0F0h 0240 4] Target Proximity Domains # : 00000003
[0F4h 0244 4] Reserved2 : 00000000
[0F8h 0248 8] Entry Base Unit : 0000000000000001
[100h 0256 4] Initiator Proximity Domain List : 00000000
[104h 0260 4] Initiator Proximity Domain List : 00000001
[108h 0264 4] Target Proximity Domain List : 00000000
[10Ch 0268 4] Target Proximity Domain List : 00000001
[110h 0272 4] Target Proximity Domain List : 00000002
[114h 0276 2] Entry : 000A
[116h 0278 2] Entry : 0005
[118h 0280 2] Entry : 0001
[11Ah 0282 2] Entry : 0005
[11Ch 0284 2] Entry : 000A
[11Eh 0286 2] Entry : 0001
Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
Signed-off-by: Hesham Almatary <hesham.almatary@huawei.com>
Reviewed-by: Jingqi Liu <jingqi.liu@intel.com>
Message-Id: <20221027100037.251-2-hesham.almatary@huawei.com>
Tested-by: Yicong Yang <yangyicong@hisilicon.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: b44678afaaad8f070ce992ffe6b31baacc65034e
https://github.com/qemu/qemu/commit/b44678afaaad8f070ce992ffe6b31baacc65034e
Author: Brice Goglin <Brice.Goglin@inria.fr>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
A tests/data/acpi/q35/APIC.acpihmat-noinitiator
A tests/data/acpi/q35/DSDT.acpihmat-noinitiator
A tests/data/acpi/q35/HMAT.acpihmat-noinitiator
A tests/data/acpi/q35/SRAT.acpihmat-noinitiator
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: acpi: add and whitelist *.hmat-noinitiator expected blobs
.. which will be used by follow up hmat-noinitiator test-case.
Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
Signed-off-by: Hesham Almatary <hesham.almatary@huawei.com>
Message-Id: <20221027100037.251-3-hesham.almatary@huawei.com>
Tested-by: Yicong Yang <yangyicong@hisilicon.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: e7f65df13eac9f20c7581fd6319d6835c603f061
https://github.com/qemu/qemu/commit/e7f65df13eac9f20c7581fd6319d6835c603f061
Author: Brice Goglin <Brice.Goglin@inria.fr>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
tests: acpi: q35: add test for hmat nodes without initiators
expected HMAT:
[000h 0000 4] Signature : "HMAT" [Heterogeneous Memory
Attributes Table]
[004h 0004 4] Table Length : 00000120
[008h 0008 1] Revision : 02
[009h 0009 1] Checksum : 4F
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] Reserved : 00000000
[028h 0040 2] Structure Type : 0000 [Memory Proximity Domain
Attributes]
[02Ah 0042 2] Reserved : 0000
[02Ch 0044 4] Length : 00000028
[030h 0048 2] Flags (decoded below) : 0001
Processor Proximity Domain Valid : 1
[032h 0050 2] Reserved1 : 0000
[034h 0052 4] Attached Initiator Proximity Domain : 00000000
[038h 0056 4] Memory Proximity Domain : 00000000
[03Ch 0060 4] Reserved2 : 00000000
[040h 0064 8] Reserved3 : 0000000000000000
[048h 0072 8] Reserved4 : 0000000000000000
[050h 0080 2] Structure Type : 0000 [Memory Proximity Domain
Attributes]
[052h 0082 2] Reserved : 0000
[054h 0084 4] Length : 00000028
[058h 0088 2] Flags (decoded below) : 0001
Processor Proximity Domain Valid : 1
[05Ah 0090 2] Reserved1 : 0000
[05Ch 0092 4] Attached Initiator Proximity Domain : 00000001
[060h 0096 4] Memory Proximity Domain : 00000001
[064h 0100 4] Reserved2 : 00000000
[068h 0104 8] Reserved3 : 0000000000000000
[070h 0112 8] Reserved4 : 0000000000000000
[078h 0120 2] Structure Type : 0000 [Memory Proximity Domain
Attributes]
[07Ah 0122 2] Reserved : 0000
[07Ch 0124 4] Length : 00000028
[080h 0128 2] Flags (decoded below) : 0000
Processor Proximity Domain Valid : 0
[082h 0130 2] Reserved1 : 0000
[084h 0132 4] Attached Initiator Proximity Domain : 00000080
[088h 0136 4] Memory Proximity Domain : 00000002
[08Ch 0140 4] Reserved2 : 00000000
[090h 0144 8] Reserved3 : 0000000000000000
[098h 0152 8] Reserved4 : 0000000000000000
[0A0h 0160 2] Structure Type : 0001 [System Locality Latency
and Bandwidth Information]
[0A2h 0162 2] Reserved : 0000
[0A4h 0164 4] Length : 00000040
[0A8h 0168 1] Flags (decoded below) : 00
Memory Hierarchy : 0
[0A9h 0169 1] Data Type : 00
[0AAh 0170 2] Reserved1 : 0000
[0ACh 0172 4] Initiator Proximity Domains # : 00000002
[0B0h 0176 4] Target Proximity Domains # : 00000003
[0B4h 0180 4] Reserved2 : 00000000
[0B8h 0184 8] Entry Base Unit : 0000000000002710
[0C0h 0192 4] Initiator Proximity Domain List : 00000000
[0C4h 0196 4] Initiator Proximity Domain List : 00000001
[0C8h 0200 4] Target Proximity Domain List : 00000000
[0CCh 0204 4] Target Proximity Domain List : 00000001
[0D0h 0208 4] Target Proximity Domain List : 00000002
[0D4h 0212 2] Entry : 0001
[0D6h 0214 2] Entry : 0002
[0D8h 0216 2] Entry : 0003
[0DAh 0218 2] Entry : 0002
[0DCh 0220 2] Entry : 0001
[0DEh 0222 2] Entry : 0003
[0E0h 0224 2] Structure Type : 0001 [System Locality Latency
and Bandwidth Information]
[0E2h 0226 2] Reserved : 0000
[0E4h 0228 4] Length : 00000040
[0E8h 0232 1] Flags (decoded below) : 00
Memory Hierarchy : 0
[0E9h 0233 1] Data Type : 03
[0EAh 0234 2] Reserved1 : 0000
[0ECh 0236 4] Initiator Proximity Domains # : 00000002
[0F0h 0240 4] Target Proximity Domains # : 00000003
[0F4h 0244 4] Reserved2 : 00000000
[0F8h 0248 8] Entry Base Unit : 0000000000000001
[100h 0256 4] Initiator Proximity Domain List : 00000000
[104h 0260 4] Initiator Proximity Domain List : 00000001
[108h 0264 4] Target Proximity Domain List : 00000000
[10Ch 0268 4] Target Proximity Domain List : 00000001
[110h 0272 4] Target Proximity Domain List : 00000002
[114h 0276 2] Entry : 000A
[116h 0278 2] Entry : 0005
[118h 0280 2] Entry : 0001
[11Ah 0282 2] Entry : 0005
[11Ch 0284 2] Entry : 000A
[11Eh 0286 2] Entry : 0001
Raw Table Data: Length 288 (0x120)
0000: 48 4D 41 54 20 01 00 00 02 4F 42 4F 43 48 53 20 // HMAT ....OBOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(...
0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0050: 00 00 00 00 28 00 00 00 01 00 00 00 01 00 00 00 // ....(...........
0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0070: 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(...
0080: 00 00 00 00 80 00 00 00 02 00 00 00 00 00 00 00 // ................
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00A0: 01 00 00 00 40 00 00 00 00 00 00 00 02 00 00 00 // ....@...........
00B0: 03 00 00 00 00 00 00 00 10 27 00 00 00 00 00 00 // .........'......
00C0: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // ................
00D0: 02 00 00 00 01 00 02 00 03 00 02 00 01 00 03 00 // ................
00E0: 01 00 00 00 40 00 00 00 00 03 00 00 02 00 00 00 // ....@...........
00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // ................
0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // ................
0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00 // ................
Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
Signed-off-by: Hesham Almatary <hesham.almatary@huawei.com>
Message-Id: <20221027100037.251-4-hesham.almatary@huawei.com>
Tested-by: Yicong Yang <yangyicong@hisilicon.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 036091d88257e5587ecfc27390e995284735b894
https://github.com/qemu/qemu/commit/036091d88257e5587ecfc27390e995284735b894
Author: Brice Goglin <Brice.Goglin@inria.fr>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/data/acpi/q35/APIC.acpihmat-noinitiator
M tests/data/acpi/q35/DSDT.acpihmat-noinitiator
M tests/data/acpi/q35/HMAT.acpihmat-noinitiator
M tests/data/acpi/q35/SRAT.acpihmat-noinitiator
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: acpi: q35: update expected blobs *.hmat-noinitiators expected HMAT:
[000h 0000 4] Signature : "HMAT" [Heterogeneous Memory
Attributes Table]
[004h 0004 4] Table Length : 00000120
[008h 0008 1] Revision : 02
[009h 0009 1] Checksum : 4F
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] Reserved : 00000000
[028h 0040 2] Structure Type : 0000 [Memory Proximity Domain
Attributes]
[02Ah 0042 2] Reserved : 0000
[02Ch 0044 4] Length : 00000028
[030h 0048 2] Flags (decoded below) : 0001
Processor Proximity Domain Valid : 1
[032h 0050 2] Reserved1 : 0000
[034h 0052 4] Attached Initiator Proximity Domain : 00000000
[038h 0056 4] Memory Proximity Domain : 00000000
[03Ch 0060 4] Reserved2 : 00000000
[040h 0064 8] Reserved3 : 0000000000000000
[048h 0072 8] Reserved4 : 0000000000000000
[050h 0080 2] Structure Type : 0000 [Memory Proximity Domain
Attributes]
[052h 0082 2] Reserved : 0000
[054h 0084 4] Length : 00000028
[058h 0088 2] Flags (decoded below) : 0001
Processor Proximity Domain Valid : 1
[05Ah 0090 2] Reserved1 : 0000
[05Ch 0092 4] Attached Initiator Proximity Domain : 00000001
[060h 0096 4] Memory Proximity Domain : 00000001
[064h 0100 4] Reserved2 : 00000000
[068h 0104 8] Reserved3 : 0000000000000000
[070h 0112 8] Reserved4 : 0000000000000000
[078h 0120 2] Structure Type : 0000 [Memory Proximity Domain
Attributes]
[07Ah 0122 2] Reserved : 0000
[07Ch 0124 4] Length : 00000028
[080h 0128 2] Flags (decoded below) : 0000
Processor Proximity Domain Valid : 0
[082h 0130 2] Reserved1 : 0000
[084h 0132 4] Attached Initiator Proximity Domain : 00000080
[088h 0136 4] Memory Proximity Domain : 00000002
[08Ch 0140 4] Reserved2 : 00000000
[090h 0144 8] Reserved3 : 0000000000000000
[098h 0152 8] Reserved4 : 0000000000000000
[0A0h 0160 2] Structure Type : 0001 [System Locality Latency
and Bandwidth Information]
[0A2h 0162 2] Reserved : 0000
[0A4h 0164 4] Length : 00000040
[0A8h 0168 1] Flags (decoded below) : 00
Memory Hierarchy : 0
[0A9h 0169 1] Data Type : 00
[0AAh 0170 2] Reserved1 : 0000
[0ACh 0172 4] Initiator Proximity Domains # : 00000002
[0B0h 0176 4] Target Proximity Domains # : 00000003
[0B4h 0180 4] Reserved2 : 00000000
[0B8h 0184 8] Entry Base Unit : 0000000000002710
[0C0h 0192 4] Initiator Proximity Domain List : 00000000
[0C4h 0196 4] Initiator Proximity Domain List : 00000001
[0C8h 0200 4] Target Proximity Domain List : 00000000
[0CCh 0204 4] Target Proximity Domain List : 00000001
[0D0h 0208 4] Target Proximity Domain List : 00000002
[0D4h 0212 2] Entry : 0001
[0D6h 0214 2] Entry : 0002
[0D8h 0216 2] Entry : 0003
[0DAh 0218 2] Entry : 0002
[0DCh 0220 2] Entry : 0001
[0DEh 0222 2] Entry : 0003
[0E0h 0224 2] Structure Type : 0001 [System Locality Latency
and Bandwidth Information]
[0E2h 0226 2] Reserved : 0000
[0E4h 0228 4] Length : 00000040
[0E8h 0232 1] Flags (decoded below) : 00
Memory Hierarchy : 0
[0E9h 0233 1] Data Type : 03
[0EAh 0234 2] Reserved1 : 0000
[0ECh 0236 4] Initiator Proximity Domains # : 00000002
[0F0h 0240 4] Target Proximity Domains # : 00000003
[0F4h 0244 4] Reserved2 : 00000000
[0F8h 0248 8] Entry Base Unit : 0000000000000001
[100h 0256 4] Initiator Proximity Domain List : 00000000
[104h 0260 4] Initiator Proximity Domain List : 00000001
[108h 0264 4] Target Proximity Domain List : 00000000
[10Ch 0268 4] Target Proximity Domain List : 00000001
[110h 0272 4] Target Proximity Domain List : 00000002
[114h 0276 2] Entry : 000A
[116h 0278 2] Entry : 0005
[118h 0280 2] Entry : 0001
[11Ah 0282 2] Entry : 0005
[11Ch 0284 2] Entry : 000A
[11Eh 0286 2] Entry : 0001
Raw Table Data: Length 288 (0x120)
0000: 48 4D 41 54 20 01 00 00 02 4F 42 4F 43 48 53 20 // HMAT ....OBOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(...
0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0050: 00 00 00 00 28 00 00 00 01 00 00 00 01 00 00 00 // ....(...........
0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0070: 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(...
0080: 00 00 00 00 80 00 00 00 02 00 00 00 00 00 00 00 // ................
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00A0: 01 00 00 00 40 00 00 00 00 00 00 00 02 00 00 00 // ....@...........
00B0: 03 00 00 00 00 00 00 00 10 27 00 00 00 00 00 00 // .........'......
00C0: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // ................
00D0: 02 00 00 00 01 00 02 00 03 00 02 00 01 00 03 00 // ................
00E0: 01 00 00 00 40 00 00 00 00 03 00 00 02 00 00 00 // ....@...........
00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // ................
0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // ................
0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00 // ................
Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
Signed-off-by: Hesham Almatary <hesham.almatary@huawei.com>
Message-Id: <20221027100037.251-5-hesham.almatary@huawei.com>
Tested-by: Yicong Yang <yangyicong@hisilicon.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a042807bf0eb9eb2e3b874a1d264a722bb107905
https://github.com/qemu/qemu/commit/a042807bf0eb9eb2e3b874a1d264a722bb107905
Author: Hesham Almatary <hesham.almatary@huawei.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
A tests/data/acpi/virt/APIC.acpihmatvirt
A tests/data/acpi/virt/DSDT.acpihmatvirt
A tests/data/acpi/virt/HMAT.acpihmatvirt
A tests/data/acpi/virt/PPTT.acpihmatvirt
A tests/data/acpi/virt/SRAT.acpihmatvirt
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: Add HMAT AArch64/virt empty table files
Signed-off-by: Hesham Almatary <hesham.almatary@huawei.com>
Message-Id: <20221027100037.251-6-hesham.almatary@huawei.com>
Tested-by: Yicong Yang <yangyicong@hisilicon.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: eb852ef79c5c8f3538c9fc4054becf6a19aad4b7
https://github.com/qemu/qemu/commit/eb852ef79c5c8f3538c9fc4054becf6a19aad4b7
Author: Xiang Chen <chenxiang66@hisilicon.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/arm/Kconfig
M hw/arm/virt-acpi-build.c
Log Message:
-----------
hw/arm/virt: Enable HMAT on arm virt machine
Since the patchset ("Build ACPI Heterogeneous Memory Attribute Table (HMAT)"),
HMAT is supported, but only x86 is enabled. Enable HMAT on arm virt machine.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: Hesham Almatary <hesham.almatary@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20221027100037.251-7-hesham.almatary@huawei.com>
Tested-by: Yicong Yang <yangyicong@hisilicon.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 27e42c2d273c97d08ab9b17758309731b4932776
https://github.com/qemu/qemu/commit/27e42c2d273c97d08ab9b17758309731b4932776
Author: Hesham Almatary <hesham.almatary@huawei.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators
This patch imitates the "tests: acpi: q35: add test for hmat nodes
without initiators" commit to test numa nodes with different HMAT
attributes, but on AArch64/virt.
Tested with:
qemu-system-aarch64 -accel tcg \
-machine virt,hmat=on,gic-version=3 -cpu cortex-a57 \
-bios qemu-efi-aarch64/QEMU_EFI.fd \
-kernel Image -append "root=/dev/vda2 console=ttyAMA0" \
-drive if=virtio,file=aarch64.qcow2,format=qcow2,id=hd \
-device virtio-rng-pci \
-net user,hostfwd=tcp::10022-:22 -net nic \
-device intel-hda -device hda-duplex -nographic \
-smp 4 \
-m 3G \
-object memory-backend-ram,size=1G,id=ram0 \
-object memory-backend-ram,size=1G,id=ram1 \
-object memory-backend-ram,size=1G,id=ram2 \
-numa node,nodeid=0,memdev=ram0,cpus=0-1 \
-numa node,nodeid=1,memdev=ram1,cpus=2-3 \
-numa node,nodeid=2,memdev=ram2 \
-numa
hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=10
\
-numa
hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
\
-numa
hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,latency=20
\
-numa
hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
\
-numa
hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,latency=30
\
-numa
hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
\
-numa
hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,latency=20
\
-numa
hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880
\
-numa
hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,latency=10
\
-numa
hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760
\
-numa
hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,latency=30
\
-numa
hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576
Signed-off-by: Hesham Almatary <hesham.almatary@huawei.com>
Message-Id: <20221027100037.251-8-hesham.almatary@huawei.com>
Tested-by: Yicong Yang <yangyicong@hisilicon.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c97e6b64078d67b9647db1ee742a3362ba4fd1a7
https://github.com/qemu/qemu/commit/c97e6b64078d67b9647db1ee742a3362ba4fd1a7
Author: Hesham Almatary <hesham.almatary@huawei.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tests/data/acpi/virt/APIC.acpihmatvirt
M tests/data/acpi/virt/DSDT.acpihmatvirt
M tests/data/acpi/virt/HMAT.acpihmatvirt
M tests/data/acpi/virt/PPTT.acpihmatvirt
M tests/data/acpi/virt/SRAT.acpihmatvirt
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: virt: Update expected *.acpihmatvirt tables
* Expected ACPI Data Table [HMAT]
[000h 0000 4] Signature : "HMAT" [Heterogeneous
Memory Attributes Table]
[004h 0004 4] Table Length : 00000120
[008h 0008 1] Revision : 02
[009h 0009 1] Checksum : 4F
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] Reserved : 00000000
[028h 0040 2] Structure Type : 0000 [Memory Proximity
Domain Attributes]
[02Ah 0042 2] Reserved : 0000
[02Ch 0044 4] Length : 00000028
[030h 0048 2] Flags (decoded below) : 0001
Processor Proximity Domain Valid : 1
[032h 0050 2] Reserved1 : 0000
[034h 0052 4] Processor Proximity Domain : 00000000
[038h 0056 4] Memory Proximity Domain : 00000000
[03Ch 0060 4] Reserved2 : 00000000
[040h 0064 8] Reserved3 : 0000000000000000
[048h 0072 8] Reserved4 : 0000000000000000
[050h 0080 2] Structure Type : 0000 [Memory Proximity
Domain Attributes]
[052h 0082 2] Reserved : 0000
[054h 0084 4] Length : 00000028
[058h 0088 2] Flags (decoded below) : 0001
Processor Proximity Domain Valid : 1
[05Ah 0090 2] Reserved1 : 0000
[05Ch 0092 4] Processor Proximity Domain : 00000001
[060h 0096 4] Memory Proximity Domain : 00000001
[064h 0100 4] Reserved2 : 00000000
[068h 0104 8] Reserved3 : 0000000000000000
[070h 0112 8] Reserved4 : 0000000000000000
[078h 0120 2] Structure Type : 0000 [Memory Proximity
Domain Attributes]
[07Ah 0122 2] Reserved : 0000
[07Ch 0124 4] Length : 00000028
[080h 0128 2] Flags (decoded below) : 0000
Processor Proximity Domain Valid : 0
[082h 0130 2] Reserved1 : 0000
[084h 0132 4] Processor Proximity Domain : 00000080
[088h 0136 4] Memory Proximity Domain : 00000002
[08Ch 0140 4] Reserved2 : 00000000
[040h 0064 8] Reserved3 : 0000000000000000
[048h 0072 8] Reserved4 : 0000000000000000
[050h 0080 2] Structure Type : 0000 [Memory Proximity
Domain Attributes]
[052h 0082 2] Reserved : 0000
[054h 0084 4] Length : 00000028
[058h 0088 2] Flags (decoded below) : 0001
Processor Proximity Domain Valid : 1
[05Ah 0090 2] Reserved1 : 0000
[05Ch 0092 4] Processor Proximity Domain : 00000001
[060h 0096 4] Memory Proximity Domain : 00000001
[064h 0100 4] Reserved2 : 00000000
[068h 0104 8] Reserved3 : 0000000000000000
[070h 0112 8] Reserved4 : 0000000000000000
[078h 0120 2] Structure Type : 0000 [Memory Proximity
Domain Attributes]
[07Ah 0122 2] Reserved : 0000
[07Ch 0124 4] Length : 00000028
[080h 0128 2] Flags (decoded below) : 0000
Processor Proximity Domain Valid : 0
[082h 0130 2] Reserved1 : 0000
[084h 0132 4] Processor Proximity Domain : 00000080
[088h 0136 4] Memory Proximity Domain : 00000002
[08Ch 0140 4] Reserved2 : 00000000
[090h 0144 8] Reserved3 : 0000000000000000
[098h 0152 8] Reserved4 : 0000000000000000
[0A0h 0160 2] Structure Type : 0001 [System Locality
Latency and Bandwidth Information]
[0A2h 0162 2] Reserved : 0000
[0A4h 0164 4] Length : 00000040
[0A8h 0168 1] Flags (decoded below) : 00
Memory Hierarchy : 0
[0A9h 0169 1] Data Type : 00
[0AAh 0170 2] Reserved1 : 0000
[0ACh 0172 4] Initiator Proximity Domains # : 00000002
[0B0h 0176 4] Target Proximity Domains # : 00000003
[0B4h 0180 4] Reserved2 : 00000000
[0B8h 0184 8] Entry Base Unit : 0000000000002710
[0C0h 0192 4] Initiator Proximity Domain List : 00000000
[0C4h 0196 4] Initiator Proximity Domain List : 00000001
[0C8h 0200 4] Target Proximity Domain List : 00000000
[0CCh 0204 4] Target Proximity Domain List : 00000001
[0D0h 0208 4] Target Proximity Domain List : 00000002
[0D4h 0212 2] Entry : 0001
[0D6h 0214 2] Entry : 0002
[0D8h 0216 2] Entry : 0003
[0DAh 0218 2] Entry : 0002
[0DCh 0220 2] Entry : 0001
[0DEh 0222 2] Entry : 0003
[0E0h 0224 2] Structure Type : 0001 [System Locality
Latency and Bandwidth Information]
[0E2h 0226 2] Reserved : 0000
[0E4h 0228 4] Length : 00000040
[0E8h 0232 1] Flags (decoded below) : 00
Memory Hierarchy : 0
[0E9h 0233 1] Data Type : 03
[0EAh 0234 2] Reserved1 : 0000
[0ECh 0236 4] Initiator Proximity Domains # : 00000002
[0F0h 0240 4] Target Proximity Domains # : 00000003
[0F4h 0244 4] Reserved2 : 00000000
[0F8h 0248 8] Entry Base Unit : 0000000000000001
[100h 0256 4] Initiator Proximity Domain List : 00000000
[104h 0260 4] Initiator Proximity Domain List : 00000001
[108h 0264 4] Target Proximity Domain List : 00000000
[10Ch 0268 4] Target Proximity Domain List : 00000001
[110h 0272 4] Target Proximity Domain List : 00000002
[114h 0276 2] Entry : 000A
[116h 0278 2] Entry : 0005
[118h 0280 2] Entry : 0001
[11Ah 0282 2] Entry : 0005
[11Ch 0284 2] Entry : 000A
[11Eh 0286 2] Entry : 0001
Raw Table Data: Length 288 (0x120)
0000: 48 4D 41 54 20 01 00 00 02 4F 42 4F 43 48 53 20 // HMAT
....OBOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC
....BXPC
0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 //
............(...
0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 //
................
0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 //
................
0050: 00 00 00 00 28 00 00 00 01 00 00 00 01 00 00 00 //
....(...........
0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 //
................
0070: 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 //
............(...
0080: 00 00 00 00 80 00 00 00 02 00 00 00 00 00 00 00 //
................
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 //
................
00A0: 01 00 00 00 40 00 00 00 00 00 00 00 02 00 00 00 //
....@...........
00B0: 03 00 00 00 00 00 00 00 10 27 00 00 00 00 00 00 //
.........'......
00C0: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 //
................
00D0: 02 00 00 00 01 00 02 00 03 00 02 00 01 00 03 00 //
................
00E0: 01 00 00 00 40 00 00 00 00 03 00 00 02 00 00 00 //
....@...........
00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 //
................
0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 //
................
0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00 //
................
Signed-off-by: Hesham Almatary <hesham.almatary@huawei.com>
Message-Id: <20221027100037.251-9-hesham.almatary@huawei.com>
Tested-by: Yicong Yang <yangyicong@hisilicon.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 21039ea0287d00609813b01a781b96ae370c7926
https://github.com/qemu/qemu/commit/21039ea0287d00609813b01a781b96ae370c7926
Author: Cindy Lu <lulu@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/vfio/common.c
M include/exec/memory.h
M softmmu/memory.c
Log Message:
-----------
vfio: move implement of vfio_get_xlat_addr() to memory.c
- Move the implement vfio_get_xlat_addr to softmmu/memory.c, and
change the name to memory_get_xlat_addr(). So we can use this
function on other devices, such as vDPA device.
- Add a new function vfio_get_xlat_addr in vfio/common.c, and it will check
whether the memory is backed by a discard manager. then device can
have its own warning.
Signed-off-by: Cindy Lu <lulu@redhat.com>
Message-Id: <20221031031020.1405111-2-lulu@redhat.com>
Acked-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 25500c234ee09b9c66040d44cc04e8d55ce89bd7
https://github.com/qemu/qemu/commit/25500c234ee09b9c66040d44cc04e8d55ce89bd7
Author: Jason Wang <jasowang@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel-iommu: don't warn guest errors when getting rid2pasid entry
We use to warn on wrong rid2pasid entry. But this error could be
triggered by the guest and could happens during initialization. So
let's don't warn in this case.
Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221028061436.30093-2-jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Commit: f06a6087e31f62f411e963a990188421e668dec8
https://github.com/qemu/qemu/commit/f06a6087e31f62f411e963a990188421e668dec8
Author: Jason Wang <jasowang@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/i386/intel_iommu.c
M include/hw/i386/intel_iommu.h
Log Message:
-----------
intel-iommu: drop VTDBus
We introduce VTDBus structure as an intermediate step for searching
the address space. This works well with SID based matching/lookup. But
when we want to support SID plus PASID based address space lookup,
this intermediate steps turns out to be a burden. So the patch simply
drops the VTDBus structure and use the PCIBus and devfn as the key for
the g_hash_table(). This simplifies the codes and the future PASID
extension.
To prevent being slower for past vtd_find_as_from_bus_num() callers, a
vtd_as cache indexed by the bus number is introduced to store the last
recent search result of a vtd_as belongs to a specific bus.
Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221028061436.30093-3-jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Commit: 68fbde504099438197ed76a3dac531df71e8ab9a
https://github.com/qemu/qemu/commit/68fbde504099438197ed76a3dac531df71e8ab9a
Author: Jason Wang <jasowang@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel-iommu: convert VTD_PE_GET_FPD_ERR() to be a function
We used to have a macro for VTD_PE_GET_FPD_ERR() but it has an
internal goto which prevents it from being reused. This patch convert
that macro to a dedicated function and let the caller to decide what
to do (e.g using goto or not). This makes sure it can be re-used for
other function that requires fault reporting.
Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221028061436.30093-4-jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Commit: 07ee04a2016da0bd1eae615678db26b86923d383
https://github.com/qemu/qemu/commit/07ee04a2016da0bd1eae615678db26b86923d383
Author: Jason Wang <jasowang@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
M hw/i386/trace-events
M include/hw/i386/intel_iommu.h
M include/hw/pci/pci_bus.h
Log Message:
-----------
intel-iommu: PASID support
This patch introduce ECAP_PASID via "x-pasid-mode". Based on the
existing support for scalable mode, we need to implement the following
missing parts:
1) tag VTDAddressSpace with PASID and support IOMMU/DMA translation
with PASID
2) tag IOTLB with PASID
3) PASID cache and its flush
4) PASID based IOTLB invalidation
For simplicity PASID cache is not implemented so we can simply
implement the PASID cache flush as a no and leave it to be implemented
in the future. For PASID based IOTLB invalidation, since we haven't
had L1 stage support, the PASID based IOTLB invalidation is not
implemented yet. For PASID based device IOTLB invalidation, it
requires the support for vhost so we forbid enabling device IOTLB when
PASID is enabled now. Those work could be done in the future.
Note that though PASID based IOMMU translation is ready but no device
can issue PASID DMA right now. In this case, PCI_NO_PASID is used as
PASID to identify the address without PASID. vtd_find_add_as() has
been extended to provision address space with PASID which could be
utilized by the future extension of PCI core to allow device model to
use PASID based DMA translation.
This feature would be useful for:
1) prototyping PASID support for devices like virtio
2) future vPASID work
3) future PRS and vSVA work
Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20221028061436.30093-5-jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c13094b29cadcb48c70815d69232ea2a5572b800
https://github.com/qemu/qemu/commit/c13094b29cadcb48c70815d69232ea2a5572b800
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M MAINTAINERS
M backends/cryptodev-builtin.c
A backends/cryptodev-lkcf.c
M backends/cryptodev-vhost-user.c
M backends/cryptodev.c
M backends/meson.build
M crypto/akcipher.c
M crypto/der.c
M crypto/der.h
M crypto/rsakey.c
M crypto/rsakey.h
A docs/devel/acpi-bits.rst
M docs/devel/index-build.rst
M hw/acpi/aml-build.c
M hw/acpi/erst.c
M hw/acpi/nvdimm.c
M hw/arm/Kconfig
M hw/arm/virt-acpi-build.c
M hw/block/vhost-user-blk.c
M hw/core/machine.c
A hw/cxl/cxl-cdat.c
M hw/cxl/meson.build
A hw/display/acpi-vga-stub.c
A hw/display/acpi-vga.c
M hw/display/meson.build
M hw/display/vga-pci.c
M hw/display/vga_int.h
M hw/i386/acpi-build.c
M hw/i386/e820_memory_layout.c
M hw/i386/e820_memory_layout.h
M hw/i386/fw_cfg.c
M hw/i386/fw_cfg.h
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
M hw/i386/microvm.c
M hw/i386/pc.c
M hw/i386/trace-events
M hw/ide/piix.c
M hw/isa/lpc_ich9.c
M hw/isa/piix3.c
M hw/mem/cxl_type3.c
M hw/net/e1000e.c
M hw/net/rocker/rocker.c
M hw/net/vhost_net-stub.c
M hw/net/vhost_net.c
M hw/net/virtio-net.c
M hw/net/vmxnet3.c
M hw/nvme/ctrl.c
M hw/pci-bridge/cxl_upstream.c
M hw/pci/meson.build
M hw/pci/msix.c
A hw/pci/pcie_doe.c
M hw/rdma/vmw/pvrdma_main.c
M hw/remote/vfio-user-obj.c
M hw/smbios/smbios.c
M hw/smbios/smbios_build.h
M hw/vfio/common.c
M hw/virtio/vhost-user.c
M hw/virtio/vhost.c
M hw/virtio/virtio-crypto.c
M hw/virtio/virtio-iommu-pci.c
M hw/virtio/virtio-pci.c
M hw/virtio/virtio-rng-pci.c
M hw/virtio/virtio.c
M include/crypto/akcipher.h
M include/exec/memory.h
M include/hw/acpi/acpi_aml_interface.h
A include/hw/cxl/cxl_cdat.h
M include/hw/cxl/cxl_component.h
M include/hw/cxl/cxl_device.h
M include/hw/cxl/cxl_pci.h
M include/hw/firmware/smbios.h
M include/hw/i386/intel_iommu.h
M include/hw/ide/pci.h
M include/hw/pci/msix.h
M include/hw/pci/pci_bus.h
M include/hw/pci/pci_ids.h
M include/hw/pci/pcie.h
A include/hw/pci/pcie_doe.h
M include/hw/pci/pcie_regs.h
M include/hw/virtio/vhost.h
M include/hw/virtio/virtio-pci.h
M include/hw/virtio/virtio.h
M include/net/vhost_net.h
M include/sysemu/cryptodev.h
M qapi/qom.json
M softmmu/memory.c
A tests/avocado/acpi-bits.py
A tests/avocado/acpi-bits/bits-config/bits-cfg.txt
A tests/avocado/acpi-bits/bits-tests/smbios.py2
A tests/avocado/acpi-bits/bits-tests/testacpi.py2
A tests/avocado/acpi-bits/bits-tests/testcpuid.py2
M tests/data/acpi/pc/DSDT
M tests/data/acpi/pc/DSDT.acpierst
M tests/data/acpi/pc/DSDT.acpihmat
M tests/data/acpi/pc/DSDT.bridge
M tests/data/acpi/pc/DSDT.cphp
M tests/data/acpi/pc/DSDT.dimmpxm
M tests/data/acpi/pc/DSDT.hpbridge
M tests/data/acpi/pc/DSDT.hpbrroot
M tests/data/acpi/pc/DSDT.ipmikcs
M tests/data/acpi/pc/DSDT.memhp
M tests/data/acpi/pc/DSDT.nohpet
M tests/data/acpi/pc/DSDT.numamem
M tests/data/acpi/pc/DSDT.roothp
M tests/data/acpi/pc/SSDT.dimmpxm
A tests/data/acpi/q35/APIC.acpihmat-noinitiator
A tests/data/acpi/q35/APIC.core-count2
M tests/data/acpi/q35/DSDT
M tests/data/acpi/q35/DSDT.acpierst
M tests/data/acpi/q35/DSDT.acpihmat
A tests/data/acpi/q35/DSDT.acpihmat-noinitiator
M tests/data/acpi/q35/DSDT.applesmc
M tests/data/acpi/q35/DSDT.bridge
A tests/data/acpi/q35/DSDT.core-count2
M tests/data/acpi/q35/DSDT.cphp
M tests/data/acpi/q35/DSDT.cxl
M tests/data/acpi/q35/DSDT.dimmpxm
M tests/data/acpi/q35/DSDT.ipmibt
M tests/data/acpi/q35/DSDT.ipmismbus
M tests/data/acpi/q35/DSDT.ivrs
M tests/data/acpi/q35/DSDT.memhp
M tests/data/acpi/q35/DSDT.mmio64
M tests/data/acpi/q35/DSDT.multi-bridge
M tests/data/acpi/q35/DSDT.nohpet
M tests/data/acpi/q35/DSDT.numamem
M tests/data/acpi/q35/DSDT.pvpanic-isa
M tests/data/acpi/q35/DSDT.tis.tpm12
M tests/data/acpi/q35/DSDT.tis.tpm2
M tests/data/acpi/q35/DSDT.viot
M tests/data/acpi/q35/DSDT.xapic
A tests/data/acpi/q35/FACP.core-count2
A tests/data/acpi/q35/HMAT.acpihmat-noinitiator
A tests/data/acpi/q35/SRAT.acpihmat-noinitiator
M tests/data/acpi/q35/SSDT.dimmpxm
M tests/data/acpi/virt/APIC
A tests/data/acpi/virt/APIC.acpihmatvirt
M tests/data/acpi/virt/APIC.memhp
M tests/data/acpi/virt/APIC.numamem
A tests/data/acpi/virt/DSDT.acpihmatvirt
M tests/data/acpi/virt/FACP
M tests/data/acpi/virt/FACP.memhp
M tests/data/acpi/virt/FACP.numamem
A tests/data/acpi/virt/HMAT.acpihmatvirt
A tests/data/acpi/virt/PPTT.acpihmatvirt
A tests/data/acpi/virt/SRAT.acpihmatvirt
M tests/data/acpi/virt/SSDT.memhp
M tests/qtest/bios-tables-test.c
M tests/qtest/ide-test.c
M tests/qtest/libqos/pci.c
M tests/qtest/libqos/pci.h
M tests/unit/test-crypto-der.c
Log Message:
-----------
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu
into staging
pci,pc,virtio: features, tests, fixes, cleanups
lots of acpi rework
first version of biosbits infrastructure
ASID support in vhost-vdpa
core_count2 support in smbios
PCIe DOE emulation
virtio vq reset
HMAT support
part of infrastructure for viommu support in vhost-vdpa
VTD PASID support
fixes, tests all over the place
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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# gpg: Signature made Mon 31 Oct 2022 11:01:50 EDT
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (85
commits)
intel-iommu: PASID support
intel-iommu: convert VTD_PE_GET_FPD_ERR() to be a function
intel-iommu: drop VTDBus
intel-iommu: don't warn guest errors when getting rid2pasid entry
vfio: move implement of vfio_get_xlat_addr() to memory.c
tests: virt: Update expected *.acpihmatvirt tables
tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators
hw/arm/virt: Enable HMAT on arm virt machine
tests: Add HMAT AArch64/virt empty table files
tests: acpi: q35: update expected blobs *.hmat-noinitiators expected HMAT:
tests: acpi: q35: add test for hmat nodes without initiators
tests: acpi: add and whitelist *.hmat-noinitiator expected blobs
hmat acpi: Don't require initiator value in -numa
hw/i386/acpi-build: Resolve north rather than south bridges
hw/i386/acpi-build: Resolve redundant attribute
hw/i386/acpi-build: Remove unused struct
hw/i386/pc.c: CXL Fixed Memory Window should not reserve e820 in bios
msix: Assert that specified vector is in range
hw/ide/piix: Ignore writes of hardwired PCI command register bits
qpci_device_enable: Allow for command bits hardwired to 0
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/5107fd3effb1...c13094b29cad
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Paolo Bonzini <=