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[Qemu-commits] [qemu/qemu] 41bf93: bsd-user: Catch up with sys/param.h r
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From: |
Paolo Bonzini |
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Subject: |
[Qemu-commits] [qemu/qemu] 41bf93: bsd-user: Catch up with sys/param.h requirement fo... |
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Date: |
Mon, 31 Oct 2022 03:42:18 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 41bf9322a0f8378b1194324cf7c6048253673046
https://github.com/qemu/qemu/commit/41bf9322a0f8378b1194324cf7c6048253673046
Author: Muhammad Moinur Rahman <bofh@FreeBSD.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M bsd-user/host/i386/host-signal.h
M bsd-user/host/x86_64/host-signal.h
Log Message:
-----------
bsd-user: Catch up with sys/param.h requirement for machine/pmap.h
Some versions of FreeBSD now require sys/param.h for machine/pmap.h on
x86. Include them here to meet that requirement. It does no harm on
older versions, so there's no need to #ifdef it.
Signed-off-by: Muhammad Moinur Rahman <bofh@FreeBSD.org>
Reviewed-by: John Baldwin <jhb@FreeBSD.org>
Signed-off-by: Warner Losh <imp@bsdimp.com>
Commit: 36c182bbe680d64f0868522bb9256b5b8eccf280
https://github.com/qemu/qemu/commit/36c182bbe680d64f0868522bb9256b5b8eccf280
Author: Claudio Imbrenda <imbrenda@linux.ibm.com>
Date: 2022-10-27 (Thu, 27 Oct 2022)
Changed paths:
M hw/s390x/pv.c
Log Message:
-----------
s390x/pv: remove semicolon from macro definition
Remove spurious semicolon at the end of the macro s390_pv_cmd
Signed-off-by: Claudio Imbrenda <imbrenda@linux.ibm.com>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Message-Id: <20221010151041.89071-1-imbrenda@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: d001a81256d1291319e13711f73d1f436beb81af
https://github.com/qemu/qemu/commit/d001a81256d1291319e13711f73d1f436beb81af
Author: Cornelia Huck <cohuck@redhat.com>
Date: 2022-10-27 (Thu, 27 Oct 2022)
Changed paths:
M MAINTAINERS
Log Message:
-----------
s390x: step down as general arch maintainer
I haven't really been working on s390x for some time now, and in
practice, I don't have time for it, either. So let's remove myself
from this entry.
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Message-Id: <20221010160957.40779-1-cohuck@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 38621181ae3cbec62e3490fbc14f6ac01642d07a
https://github.com/qemu/qemu/commit/38621181ae3cbec62e3490fbc14f6ac01642d07a
Author: Nico Boehr <nrb@linux.ibm.com>
Date: 2022-10-27 (Thu, 27 Oct 2022)
Changed paths:
M hw/s390x/tod-kvm.c
Log Message:
-----------
s390x/tod-kvm: don't save/restore the TOD in PV guests
Under PV, the guest's TOD clock is under control of the ultravisor and the
hypervisor cannot change it.
With upcoming kernel changes[1], the Linux kernel will reject QEMU's
request to adjust the guest's clock in this case, so don't attempt to set
the clock.
This avoids the following warning message on save/restore of a PV guest:
warning: Unable to set KVM guest TOD clock: Operation not supported
[1] https://lore.kernel.org/all/20221011160712.928239-2-nrb@linux.ibm.com/
Fixes: c3347ed0d2ee ("s390x: protvirt: Support unpack facility")
Signed-off-by: Nico Boehr <nrb@linux.ibm.com>
Message-Id: <20221012123229.1196007-1-nrb@linux.ibm.com>
[thuth: Add curly braces]
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 117ea96089e36a4d31a42f96062b950641ba1698
https://github.com/qemu/qemu/commit/117ea96089e36a4d31a42f96062b950641ba1698
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-10-27 (Thu, 27 Oct 2022)
Changed paths:
M tests/tcg/s390x/Makefile.target
Log Message:
-----------
tests/tcg/s390x: Test compiler flags only once, not every time
This is common practice, see the Makefile.target in the aarch64
folder for example.
Suggested-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20221012182755.1014853-2-thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: f7d81a351d6122440f9190adba69da3f81b7b186
https://github.com/qemu/qemu/commit/f7d81a351d6122440f9190adba69da3f81b7b186
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-10-27 (Thu, 27 Oct 2022)
Changed paths:
M target/s390x/tcg/translate_vx.c.inc
Log Message:
-----------
target/s390x: Fix emulation of the VISTR instruction
The element size is encoded in the M3 field, not in the M4
field.
Fixes: be6324c6b734 ("s390x/tcg: Implement VECTOR ISOLATE STRING")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1248
Message-Id: <20221012182755.1014853-3-thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 9e3eb3b29a73c35adbbe60b0fd3c8feb6c680d55
https://github.com/qemu/qemu/commit/9e3eb3b29a73c35adbbe60b0fd3c8feb6c680d55
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M tests/tcg/s390x/Makefile.target
A tests/tcg/s390x/vistr.c
Log Message:
-----------
tests/tcg/s390x: Add a test for the vistr instruction
This test can be used to verify that the change in the previous
commit is indeed fixing the problem with the M3 vs. M4 field
mixup.
Message-Id: <20221012182755.1014853-4-thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 9d711f19c5608910cdefdad24e23a2e695b312bb
https://github.com/qemu/qemu/commit/9d711f19c5608910cdefdad24e23a2e695b312bb
Author: Christian Borntraeger <borntraeger@linux.ibm.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: target/s390x/: add Ilya as reviewer
Ilya has volunteered to review TCG patches for s390x.
Signed-off-by: Christian Borntraeger <borntraeger@linux.ibm.com>
Acked-by: David Hildenbrand <david@redhat.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <20221019125640.3014143-1-borntraeger@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: daa8bb57dba5add4929dea6919858a2062101b26
https://github.com/qemu/qemu/commit/daa8bb57dba5add4929dea6919858a2062101b26
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M tests/qtest/tpm-crb-swtpm-test.c
M tests/qtest/tpm-tis-device-swtpm-test.c
M tests/qtest/tpm-tis-swtpm-test.c
M tests/qtest/tpm-util.c
M tests/qtest/tpm-util.h
Log Message:
-----------
tests/qtest/tpm: Clean up remainders of swtpm
After running "make check", there are remainders of the tpm
tests left in the /tmp directory, slowly filling it up.
Seems like "swtpm" leaves a ".lock" and a "tpm2-00.permall"
file behind, so that the g_rmdir() calls on the temporary
directories fail. Introduce a helper function to remove those
leftovers before doing the g_rmdir().
Message-Id: <20221012084334.794253-1-thuth@redhat.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 73df4f92273d80556777b9f2084898bd1889315e
https://github.com/qemu/qemu/commit/73df4f92273d80556777b9f2084898bd1889315e
Author: Thomas Huth <thuth@redhat.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M tests/qtest/cxl-test.c
Log Message:
-----------
tests/qtest/cxl-test: Remove temporary directories after testing
The cxl-test leaves some temporary directories behind. Let's
clean them up now!
Message-Id: <20221012091435.893570-1-thuth@redhat.com>
Reviewed-by: Zhang Chen <chen.zhang@intel.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 0e283d845e9040a4a20dfb2c7122c9e95afca46f
https://github.com/qemu/qemu/commit/0e283d845e9040a4a20dfb2c7122c9e95afca46f
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M hw/net/e1000_regs.h
M tests/qtest/libqos/e1000e.c
Log Message:
-----------
tests/qtest/libqos/e1000e: Use e1000_regs.h
The register definitions in tests/qtest/libqos/e1000e.c had names
different from hw/net/e1000_regs.h, which made it hard to understand
what test codes corresponds to the implementation. Use
hw/net/e1000_regs.h from tests/qtest/libqos/e1000e.c to remove
these duplications.
E1000E_CTRL_EXT_TXLSFLOW is removed from E1000E_CTRL_EXT settings
because hw/net/e1000_regs.h does not have the definition and it is for
TCP segmentation offload, which does not matter for the implemented
tests.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20221013055245.28102-1-akihiko.odaki@daynix.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 690d43a8b1fa0d6fce6f68725e823e95115cf532
https://github.com/qemu/qemu/commit/690d43a8b1fa0d6fce6f68725e823e95115cf532
Author: Brad Smith <brad@comstyle.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M tests/vm/openbsd
Log Message:
-----------
tests/vm: update openbsd to release 7.2
tests/vm: update openbsd to release 7.2
Signed-off-by: Brad Smith <brad@comstyle.com>
Message-Id: <Y1TKVwNKvk+euT/s@humpty.home.comstyle.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 8f4bcbcf110f27b3bf8b8c33b48ec321f3e136d3
https://github.com/qemu/qemu/commit/8f4bcbcf110f27b3bf8b8c33b48ec321f3e136d3
Author: Brad Smith <brad@comstyle.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M .gitlab-ci.d/cirrus/freebsd-12.vars
M .gitlab-ci.d/cirrus/freebsd-13.vars
M tests/docker/dockerfiles/alpine.docker
M tests/docker/dockerfiles/centos8.docker
M tests/docker/dockerfiles/debian-amd64-cross.docker
M tests/docker/dockerfiles/debian-amd64.docker
M tests/docker/dockerfiles/debian-arm64-cross.docker
M tests/docker/dockerfiles/debian-armel-cross.docker
M tests/docker/dockerfiles/debian-armhf-cross.docker
M tests/docker/dockerfiles/debian-mips64el-cross.docker
M tests/docker/dockerfiles/debian-mipsel-cross.docker
M tests/docker/dockerfiles/debian-ppc64el-cross.docker
M tests/docker/dockerfiles/debian-s390x-cross.docker
M tests/docker/dockerfiles/fedora.docker
M tests/docker/dockerfiles/opensuse-leap.docker
M tests/docker/dockerfiles/ubuntu2004.docker
M tests/lcitool/libvirt-ci
M tests/lcitool/projects/qemu.yml
M tests/vm/freebsd
Log Message:
-----------
tests: Add sndio to the FreeBSD CI containers / VM
Add sndio to the FreeBSD CI containers / VM
Signed-off-by: Brad Smith <brad@comstyle.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Message-Id: <Y1f6dxjvD01DtXyG@humpty.home.comstyle.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: c9923550b446e54413024117c0ed978a08e3ab1a
https://github.com/qemu/qemu/commit/c9923550b446e54413024117c0ed978a08e3ab1a
Author: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M accel/dummy-cpus.c
M accel/meson.build
M accel/qtest/meson.build
M include/hw/core/cpu.h
M softmmu/cpus.c
Log Message:
-----------
accel/qtest: Support qtest accelerator for Windows
Currently signal SIGIPI [=SIGUSR1] is used to kick the dummy CPU
when qtest accelerator is used. However SIGUSR1 is unsupported on
Windows. To support Windows, we add a QemuSemaphore CPUState::sem
to kick the dummy CPU instead for Windows.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20221028045736.679903-2-bin.meng@windriver.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 84c662d2546feda2aeac21d09d4c71e8658062c0
https://github.com/qemu/qemu/commit/84c662d2546feda2aeac21d09d4c71e8658062c0
Author: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M include/qemu/sockets.h
M tests/qtest/libqmp.c
M tests/qtest/libqtest.c
M util/osdep.c
Log Message:
-----------
tests/qtest: Use send/recv for socket communication
Socket communication in the libqtest and libqmp codes uses read()
and write() which work on any file descriptor on *nix, and sockets
in *nix are an example of a file descriptor.
However sockets on Windows do not use *nix-style file descriptors,
so read() and write() cannot be used on sockets on Windows.
Switch over to use send() and recv() instead which work on both
Windows and *nix.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20221028045736.679903-3-bin.meng@windriver.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: b1d3095ccf61e4d1bd1d6273b9b7060fe7f20934
https://github.com/qemu/qemu/commit/b1d3095ccf61e4d1bd1d6273b9b7060fe7f20934
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M tests/qtest/libqtest.c
Log Message:
-----------
tests/qtest: Support libqtest to build and run on Windows
At present the libqtest codes were written to depend on several
POSIX APIs, including fork(), kill() and waitpid(). Unfortunately
these APIs are not available on Windows.
This commit implements the corresponding functionalities using
win32 native APIs. With this change, all qtest cases can build
successfully on a Windows host, and we can start qtest testing
on Windows now.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20221028045736.679903-4-bin.meng@windriver.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: e4439e52806b797f38adf7a96b5ed74295f806b0
https://github.com/qemu/qemu/commit/e4439e52806b797f38adf7a96b5ed74295f806b0
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M tests/qtest/device-plug-test.c
Log Message:
-----------
tests/qtest: device-plug-test: Reverse the usage of double/single quotes
The usage of double/single quotes in test_q35_pci_unplug_json_request()
should be reversed to work on both win32 and non-win32 platforms:
- The value of -device parameter needs to be surrounded by "" as
Windows does not drop '' when passing it to QEMU which causes
QEMU command line option parser failure.
- The JSON key/value pairs need to be surrounded by '' to make the
JSON parser happy on Windows.
Fixes: a12f1a7e56b7 ("tests/x86: Add subtest with 'q35' machine type to
device-plug-test")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20221028045736.679903-5-bin.meng@windriver.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 1b0f1b14fe26752d628dd71920f4bb63b79765a4
https://github.com/qemu/qemu/commit/1b0f1b14fe26752d628dd71920f4bb63b79765a4
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M tests/qtest/dbus-vmstate-test.c
M tests/qtest/migration-test.c
Log Message:
-----------
tests/qtest: Use EXIT_FAILURE instead of magic number
When migration fails, QEMU exits with a status code EXIT_FAILURE.
Change qtests to use the well-defined macro instead of magic number.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20221028045736.679903-6-bin.meng@windriver.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 69c056fbc0cd57b4b2db7b3e823a9f6945756b38
https://github.com/qemu/qemu/commit/69c056fbc0cd57b4b2db7b3e823a9f6945756b38
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M tests/qtest/libqtest.c
M tests/qtest/libqtest.h
Log Message:
-----------
tests/qtest: libqtest: Introduce qtest_wait_qemu()
Introduce an API for qtest to wait for the QEMU process to terminate.
Suggested-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20221028045736.679903-7-bin.meng@windriver.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: f2d063e61ee2026700ab44bef967f663e976bec8
https://github.com/qemu/qemu/commit/f2d063e61ee2026700ab44bef967f663e976bec8
Author: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M tests/qtest/migration-test.c
Log Message:
-----------
tests/qtest: migration-test: Make sure QEMU process "to" exited after
migration is canceled
Make sure QEMU process "to" exited before launching another target
for migration in the test_multifd_tcp_cancel case.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20221028045736.679903-8-bin.meng@windriver.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 8aff9c3279087b8527fd2c3dd4cf0706892887ba
https://github.com/qemu/qemu/commit/8aff9c3279087b8527fd2c3dd4cf0706892887ba
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M tests/qtest/libqos/meson.build
Log Message:
-----------
tests/qtest: libqos: Do not build virtio-9p unconditionally
At present the virtio-9p related codes are built into libqos
unconditionally. Change to build them conditionally by testing
the 'virtfs' config option.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20221028045736.679903-9-bin.meng@windriver.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: db8fca024fa98241ed40470f87b8ecfb82c57d32
https://github.com/qemu/qemu/commit/db8fca024fa98241ed40470f87b8ecfb82c57d32
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M tests/qtest/libqtest.c
Log Message:
-----------
tests/qtest: libqtest: Correct the timeout unit of blocking receive calls for
win32
Some qtest cases don't get response from the QEMU executable under
test in time on Windows. It turns out that the socket receive call
got timeout before it receive the complete response.
The timeout value is supposed to be set to 50 seconds via the
setsockopt() call, but there is a difference among platforms.
The timeout unit of blocking receive calls is measured in
seconds on non-Windows platforms but milliseconds on Windows.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20221028045736.679903-10-bin.meng@windriver.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Commit: 4f93f071ca9e7f85f976c805142d33f6cffd2745
https://github.com/qemu/qemu/commit/4f93f071ca9e7f85f976c805142d33f6cffd2745
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: fix msgclr/msgsnd insns flags
On Power ISA v2.07, the category for these instructions became
"Embedded.Processor Control" or "Book S".
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221006200654.725390-2-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 9d950c724144770d9d092f70716da0da022926de
https://github.com/qemu/qemu/commit/9d950c724144770d9d092f70716da0da022926de
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: fix msgsync insns flags
This instruction was added by Power ISA 3.0, using PPC2_PRCNTL makes it
available for older processors, like de e5500 and e6500.
Fixes: 7af1e7b02264 ("target/ppc: add support for hypervisor doorbells on
book3s CPUs")
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221006200654.725390-3-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: e8db3cc76e9555c482ee92743bcf3560e25b1424
https://github.com/qemu/qemu/commit/e8db3cc76e9555c482ee92743bcf3560e25b1424
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: fix REQUIRE_HV macro definition
The macro is missing a '{' after the if condition. Any use of REQUIRE_HV
would cause a compilation error.
Fixes: fc34e81acd51 ("target/ppc: add macros to check privilege level")
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221006200654.725390-4-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 98f43417b66457eb9c207a2a09e0eef984dadc41
https://github.com/qemu/qemu/commit/98f43417b66457eb9c207a2a09e0eef984dadc41
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate.c
A target/ppc/translate/processor-ctrl-impl.c.inc
Log Message:
-----------
target/ppc: move msgclr/msgsnd to decodetree
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221006200654.725390-5-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: e8e09d7da7dd572e6cf62b2f12b65fb9833cf7ba
https://github.com/qemu/qemu/commit/e8e09d7da7dd572e6cf62b2f12b65fb9833cf7ba
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate.c
M target/ppc/translate/processor-ctrl-impl.c.inc
Log Message:
-----------
target/ppc: move msgclrp/msgsndp to decodetree
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221006200654.725390-6-matheus.ferst@eldorado.org.br>
[danielhb: ppc32 build fix in trans_(MSGCLRP|MSGSNDP)]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: b35bf5f2d759d97652b4acd96e62329a1657f3cb
https://github.com/qemu/qemu/commit/b35bf5f2d759d97652b4acd96e62329a1657f3cb
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate.c
M target/ppc/translate/processor-ctrl-impl.c.inc
Log Message:
-----------
target/ppc: move msgsync to decodetree
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221006200654.725390-7-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: dc46167a2225d3c0861cd4fcbc350e3e0e89bc61
https://github.com/qemu/qemu/commit/dc46167a2225d3c0861cd4fcbc350e3e0e89bc61
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate.c
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: Moved VMLADDUHM to decodetree and use gvec
This patch moves VMLADDUHM to decodetree a creates a gvec implementation
using mul_vec and add_vec.
rept loop master patch
8 12500 0,01810500 0,00903100 (-50.1%)
25 4000 0,01739400 0,00747700 (-57.0%)
100 1000 0,01843600 0,00901400 (-51.1%)
500 200 0,02574600 0,01971000 (-23.4%)
2500 40 0,05921600 0,07121800 (+20.3%)
8000 12 0,15326700 0,21725200 (+41.7%)
The significant difference in performance when REPT is low and LOOP is
high I think is due to the fact that the new implementation has a higher
translation time, as when using a helper only 5 TCGop are used but with
the patch a total of 10 TCGop are needed (Power lacks a direct mul_vec
equivalent so this instruction is implemented with the help of 5 others,
vmuleu, vmulou, vmrgh, vmrgl and vpkum).
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-2-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 306e4753354378213eddf6f4e6335ffc68186d1f
https://github.com/qemu/qemu/commit/306e4753354378213eddf6f4e6335ffc68186d1f
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vmx-ops.c.inc
Log Message:
-----------
target/ppc: Move VMH[R]ADDSHS instruction to decodetree
This patch moves VMHADDSHS and VMHRADDSHS to decodetree I couldn't find
a satisfactory implementation with TCG inline.
vmhaddshs:
rept loop master patch
8 12500 0,02983400 0,02648500 (-11.2%)
25 4000 0,02946000 0,02518000 (-14.5%)
100 1000 0,03104300 0,02638000 (-15.0%)
500 200 0,04002000 0,03502500 (-12.5%)
2500 40 0,08090100 0,07562200 (-6.5%)
8000 12 0,19242600 0,18626800 (-3.2%)
vmhraddshs:
rept loop master patch
8 12500 0,03078600 0,02851000 (-7.4%)
25 4000 0,02793200 0,02746900 (-1.7%)
100 1000 0,02886000 0,02839900 (-1.6%)
500 200 0,03714700 0,03799200 (+2.3%)
2500 40 0,07948000 0,07852200 (-1.2%)
8000 12 0,19049800 0,18813900 (-1.2%)
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-3-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 611bc69bf6bc6b23e91e4798c036b941c9958b40
https://github.com/qemu/qemu/commit/611bc69bf6bc6b23e91e4798c036b941c9958b40
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vmx-ops.c.inc
Log Message:
-----------
target/ppc: Move V(ADD|SUB)CUW to decodetree and use gvec
This patch moves VADDCUW and VSUBCUW to decodtree with gvec using an
implementation based on the helper, with the main difference being
changing the -1 (aka all bits set to 1) result returned by cmp when
true to +1. It also implemented a .fni4 version of those instructions
and dropped the helper.
vaddcuw:
rept loop master patch
8 12500 0,01008200 0,00612400 (-39.3%)
25 4000 0,01091500 0,00471600 (-56.8%)
100 1000 0,01332500 0,00593700 (-55.4%)
500 200 0,01998500 0,01275700 (-36.2%)
2500 40 0,04704300 0,04364300 (-7.2%)
8000 12 0,10748200 0,11241000 (+4.6%)
vsubcuw:
rept loop master patch
8 12500 0,01226200 0,00571600 (-53.4%)
25 4000 0,01493500 0,00462100 (-69.1%)
100 1000 0,01522700 0,00455100 (-70.1%)
500 200 0,02384600 0,01133500 (-52.5%)
2500 40 0,04935200 0,03178100 (-35.6%)
8000 12 0,09039900 0,09440600 (+4.4%)
Overall there was a gain in performance, but the TCGop code was still
slightly bigger in the new version (it went from 4 to 5).
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-4-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 90b5aadb09b1063dfc34636efe212c6862cbe32f
https://github.com/qemu/qemu/commit/90b5aadb09b1063dfc34636efe212c6862cbe32f
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vmx-ops.c.inc
Log Message:
-----------
target/ppc: Move VNEG[WD] to decodtree and use gvec
Moved the instructions VNEGW and VNEGD to decodetree and used gvec to
decode it.
vnegw:
rept loop master patch
8 12500 0,01053200 0,00548400 (-47.9%)
25 4000 0,01030500 0,00390000 (-62.2%)
100 1000 0,01096300 0,00395400 (-63.9%)
500 200 0,01472000 0,00712300 (-51.6%)
2500 40 0,03809000 0,02147700 (-43.6%)
8000 12 0,09957100 0,06202100 (-37.7%)
vnegd:
rept loop master patch
8 12500 0,00594600 0,00543800 (-8.5%)
25 4000 0,00575200 0,00396400 (-31.1%)
100 1000 0,00676100 0,00394800 (-41.6%)
500 200 0,01149300 0,00709400 (-38.3%)
2500 40 0,03441500 0,02169600 (-37.0%)
8000 12 0,09516900 0,06337000 (-33.4%)
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-5-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: d57fbd8fd9ea4f559cf4ed6c8fb6f064b73d6882
https://github.com/qemu/qemu/commit/d57fbd8fd9ea4f559cf4ed6c8fb6f064b73d6882
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vmx-ops.c.inc
Log Message:
-----------
target/ppc: Move VPRTYB[WDQ] to decodetree and use gvec
Moved VPRTYBW and VPRTYBD to use gvec and both of them and VPRTYBQ to
decodetree. VPRTYBW and VPRTYBD now also use .fni4 and .fni8,
respectively.
vprtybw:
rept loop master patch
8 12500 0,01198900 0,00703100 (-41.4%)
25 4000 0,01070100 0,00571400 (-46.6%)
100 1000 0,01123300 0,00678200 (-39.6%)
500 200 0,01601500 0,01535600 (-4.1%)
2500 40 0,03872900 0,05562100 (43.6%)
8000 12 0,10047000 0,16643000 (65.7%)
vprtybd:
rept loop master patch
8 12500 0,00757700 0,00788100 (4.0%)
25 4000 0,00652500 0,00669600 (2.6%)
100 1000 0,00714400 0,00825400 (15.5%)
500 200 0,01211000 0,01903700 (57.2%)
2500 40 0,03483800 0,07021200 (101.5%)
8000 12 0,09591800 0,21036200 (119.3%)
vprtybq:
rept loop master patch
8 12500 0,00675600 0,00667200 (-1.2%)
25 4000 0,00619400 0,00643200 (3.8%)
100 1000 0,00707100 0,00751100 (6.2%)
500 200 0,01199300 0,01342000 (11.9%)
2500 40 0,03490900 0,04092900 (17.2%)
8000 12 0,09588200 0,11465100 (19.6%)
I wasn't expecting such a performance lost in both VPRTYBD and VPRTYBQ,
I'm not sure if it's worth to move those instructions. Comparing the
assembly of the helper with the TCGop they are pretty similar, so
I'm not sure why vprtybd took so much more time.
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-6-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: c85929b2ddf6bbad737635c9b85213007ec043af
https://github.com/qemu/qemu/commit/c85929b2ddf6bbad737635c9b85213007ec043af
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vmx-ops.c.inc
Log Message:
-----------
target/ppc: Move VAVG[SU][BHW] to decodetree and use gvec
Moved the instructions VAVGUB, VAVGUH, VAVGUW, VAVGSB, VAVGSH, VAVGSW,
to decodetree and use gvec with them. For these one the right shift
had to be made before the sum as to avoid an overflow, so add 1 at the
end if any of the entries had 1 in its LSB as to replicate the "+ 1"
before the shift described by the ISA.
vavgub:
rept loop master patch
8 12500 0,02616600 0,00754200 (-71.2%)
25 4000 0,02530000 0,00637700 (-74.8%)
100 1000 0,02604600 0,00790100 (-69.7%)
500 200 0,03189300 0,01838400 (-42.4%)
2500 40 0,06006900 0,06851000 (+14.1%)
8000 12 0,13941000 0,20548500 (+47.4%)
vavguh:
rept loop master patch
8 12500 0,01818200 0,00780600 (-57.1%)
25 4000 0,01789300 0,00641600 (-64.1%)
100 1000 0,01899100 0,00787200 (-58.5%)
500 200 0,02527200 0,01828400 (-27.7%)
2500 40 0,05361800 0,06773000 (+26.3%)
8000 12 0,12886600 0,20291400 (+57.5%)
vavguw:
rept loop master patch
8 12500 0,01423100 0,00776600 (-45.4%)
25 4000 0,01780800 0,00638600 (-64.1%)
100 1000 0,02085500 0,00787000 (-62.3%)
500 200 0,02737100 0,01828800 (-33.2%)
2500 40 0,05572600 0,06774200 (+21.6%)
8000 12 0,13101700 0,20311600 (+55.0%)
vavgsb:
rept loop master patch
8 12500 0,03006000 0,00788600 (-73.8%)
25 4000 0,02882200 0,00637800 (-77.9%)
100 1000 0,02958000 0,00791400 (-73.2%)
500 200 0,03548800 0,01860400 (-47.6%)
2500 40 0,06360000 0,06850800 (+7.7%)
8000 12 0,13816500 0,20550300 (+48.7%)
vavgsh:
rept loop master patch
8 12500 0,01965900 0,00776600 (-60.5%)
25 4000 0,01875400 0,00638700 (-65.9%)
100 1000 0,01952200 0,00786900 (-59.7%)
500 200 0,02562000 0,01760300 (-31.3%)
2500 40 0,05384300 0,06742800 (+25.2%)
8000 12 0,13240800 0,20330000 (+53.5%)
vavgsw:
rept loop master patch
8 12500 0,01407700 0,00775600 (-44.9%)
25 4000 0,01762300 0,00640000 (-63.7%)
100 1000 0,02046500 0,00788500 (-61.5%)
500 200 0,02745600 0,01843000 (-32.9%)
2500 40 0,05375500 0,06820500 (+26.9%)
8000 12 0,13068300 0,20304900 (+55.4%)
These results to me seems to indicate that with gvec the results have a
slower translation but faster execution.
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-7-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 26c964f85159c78f6ecf132de8f2f0093d3f2e89
https://github.com/qemu/qemu/commit/26c964f85159c78f6ecf132de8f2f0093d3f2e89
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vmx-ops.c.inc
Log Message:
-----------
target/ppc: Move VABSDU[BHW] to decodetree and use gvec
Moved VABSDUB, VABSDUH and VABSDUW to decodetree and use gvec to
translate them.
vabsdub:
rept loop master patch
8 12500 0,03601600 0,00688500 (-80.9%)
25 4000 0,03651000 0,00532100 (-85.4%)
100 1000 0,03666900 0,00595300 (-83.8%)
500 200 0,04305800 0,01244600 (-71.1%)
2500 40 0,06893300 0,04273700 (-38.0%)
8000 12 0,14633200 0,12660300 (-13.5%)
vabsduh:
rept loop master patch
8 12500 0,02172400 0,00687500 (-68.4%)
25 4000 0,02154100 0,00531500 (-75.3%)
100 1000 0,02235400 0,00596300 (-73.3%)
500 200 0,02827500 0,01245100 (-56.0%)
2500 40 0,05638400 0,04285500 (-24.0%)
8000 12 0,13166000 0,12641400 (-4.0%)
vabsduw:
rept loop master patch
8 12500 0,01646400 0,00688300 (-58.2%)
25 4000 0,01454500 0,00475500 (-67.3%)
100 1000 0,01545800 0,00511800 (-66.9%)
500 200 0,02168200 0,01114300 (-48.6%)
2500 40 0,04571300 0,04138800 (-9.5%)
8000 12 0,12209500 0,12178500 (-0.3%)
Same as VADDCUW and VSUBCUW, overall performance gain but it uses more
TCGop (4 before the patch, 6 after).
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-8-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: a5b36805192ac12f114c45e9c8ccbe4ce9ba1cf9
https://github.com/qemu/qemu/commit/a5b36805192ac12f114c45e9c8ccbe4ce9ba1cf9
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
target/ppc: Use gvec to decode XV[N]ABS[DS]P/XVNEG[DS]P
Moved XVABSSP, XVABSDP, XVNABSSP,XVNABSDP, XVNEGSP and XVNEGDP to
decodetree and used gvec to translate them.
xvabssp:
rept loop master patch
8 12500 0,00477900 0,00476000 (-0.4%)
25 4000 0,00442800 0,00353300 (-20.2%)
100 1000 0,00478700 0,00366100 (-23.5%)
500 200 0,00973200 0,00649400 (-33.3%)
2500 40 0,03165200 0,02226700 (-29.7%)
8000 12 0,09315900 0,06674900 (-28.3%)
xvabsdp:
rept loop master patch
8 12500 0,00475000 0,00474400 (-0.1%)
25 4000 0,00355600 0,00367500 (+3.3%)
100 1000 0,00444200 0,00366000 (-17.6%)
500 200 0,00942700 0,00732400 (-22.3%)
2500 40 0,02990000 0,02308500 (-22.8%)
8000 12 0,08770300 0,06683800 (-23.8%)
xvnabssp:
rept loop master patch
8 12500 0,00494500 0,00492900 (-0.3%)
25 4000 0,00397700 0,00338600 (-14.9%)
100 1000 0,00421400 0,00353500 (-16.1%)
500 200 0,01048000 0,00707100 (-32.5%)
2500 40 0,03251500 0,02238300 (-31.2%)
8000 12 0,08889100 0,06469800 (-27.2%)
xvnabsdp:
rept loop master patch
8 12500 0,00511000 0,00492700 (-3.6%)
25 4000 0,00398800 0,00381500 (-4.3%)
100 1000 0,00390500 0,00365900 (-6.3%)
500 200 0,00924800 0,00784600 (-15.2%)
2500 40 0,03138900 0,02391600 (-23.8%)
8000 12 0,09654200 0,05684600 (-41.1%)
xvnegsp:
rept loop master patch
8 12500 0,00493900 0,00452800 (-8.3%)
25 4000 0,00369100 0,00366800 (-0.6%)
100 1000 0,00371100 0,00380000 (+2.4%)
500 200 0,00991100 0,00652300 (-34.2%)
2500 40 0,03025800 0,02422300 (-19.9%)
8000 12 0,09251100 0,06457600 (-30.2%)
xvnegdp:
rept loop master patch
8 12500 0,00474900 0,00454400 (-4.3%)
25 4000 0,00353100 0,00325600 (-7.8%)
100 1000 0,00398600 0,00366800 (-8.0%)
500 200 0,01032300 0,00702400 (-32.0%)
2500 40 0,03125000 0,02422400 (-22.5%)
8000 12 0,09475100 0,06173000 (-34.9%)
This one to me seemed the opposite of the previous instructions, as it
looks like there was an improvement in the translation time (itself not
a surprise as operations were done twice before so there was the need to
translate twice as many TCGop)
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-9-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 95a89d3118590aaed3a56b52e08246cdb51a108e
https://github.com/qemu/qemu/commit/95a89d3118590aaed3a56b52e08246cdb51a108e
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
target/ppc: Use gvec to decode XVCPSGN[SD]P
Moved XVCPSGNSP and XVCPSGNDP to decodetree and used gvec to translate
them.
xvcpsgnsp:
rept loop master patch
8 12500 0,00561400 0,00537900 (-4.2%)
25 4000 0,00562100 0,00400000 (-28.8%)
100 1000 0,00696900 0,00416300 (-40.3%)
500 200 0,02211900 0,00840700 (-62.0%)
2500 40 0,09328600 0,02728300 (-70.8%)
8000 12 0,27295300 0,06867800 (-74.8%)
xvcpsgndp:
rept loop master patch
8 12500 0,00556300 0,00584200 (+5.0%)
25 4000 0,00482700 0,00431700 (-10.6%)
100 1000 0,00585800 0,00464400 (-20.7%)
500 200 0,01565300 0,00839700 (-46.4%)
2500 40 0,05766500 0,02430600 (-57.8%)
8000 12 0,19875300 0,07947100 (-60.0%)
Like the previous instructions there seemed to be a improvement on
translation time.
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-10-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: a70a5247104d3d7a8cf584f20d73f41bef643a19
https://github.com/qemu/qemu/commit/a70a5247104d3d7a8cf584f20d73f41bef643a19
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
target/ppc: Moved XVTSTDC[DS]P to decodetree
Moved XVTSTDCSP and XVTSTDCDP to decodetree an restructured the helper
to be simpler and do all decoding in the decodetree (so XB, XT and DCMX
are all calculated outside the helper).
Obs: The tests in this one are slightly different, these are the sum of
these instructions with all possible immediate and those instructions
are repeated 10 times.
xvtstdcsp:
rept loop master patch
8 12500 2,76402100 2,70699100 (-2.1%)
25 4000 2,64867100 2,67884100 (+1.1%)
100 1000 2,73806300 2,78701000 (+1.8%)
500 200 3,44666500 3,61027600 (+4.7%)
2500 40 5,85790200 6,47475500 (+10.5%)
8000 12 15,22102100 17,46062900 (+14.7%)
xvtstdcdp:
rept loop master patch
8 12500 2,11818000 1,61065300 (-24.0%)
25 4000 2,04573400 1,60132200 (-21.7%)
100 1000 2,13834100 1,69988100 (-20.5%)
500 200 2,73977000 2,48631700 (-9.3%)
2500 40 5,05067000 5,25914100 (+4.1%)
8000 12 14,60507800 15,93704900 (+9.1%)
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-11-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: da3c53bac3d8f3040b35ef3d98a64b592bb28a66
https://github.com/qemu/qemu/commit/da3c53bac3d8f3040b35ef3d98a64b592bb28a66
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
target/ppc: Moved XSTSTDC[QDS]P to decodetree
Moved XSTSTDCSP, XSTSTDCDP and XSTSTDCQP to decodetree and moved some of
its decoding away from the helper as previously the DCMX, XB and BF were
calculated in the helper with the help of cpu_env, now that part was
moved to the decodetree with the rest.
xvtstdcsp:
rept loop master patch
8 12500 1,85393600 1,94683600 (+5.0%)
25 4000 1,78779800 1,92479000 (+7.7%)
100 1000 2,12775000 2,28895500 (+7.6%)
500 200 2,99655300 3,23102900 (+7.8%)
2500 40 6,89082200 7,44827500 (+8.1%)
8000 12 17,50585500 18,95152100 (+8.3%)
xvtstdcdp:
rept loop master patch
8 12500 1,39043100 1,33539800 (-4.0%)
25 4000 1,35731800 1,37347800 (+1.2%)
100 1000 1,51514800 1,56053000 (+3.0%)
500 200 2,21014400 2,47906000 (+12.2%)
2500 40 5,39488200 6,68766700 (+24.0%)
8000 12 13,98623900 18,17661900 (+30.0%)
xvtstdcdp:
rept loop master patch
8 12500 1,35123800 1,34455800 (-0.5%)
25 4000 1,36441200 1,36759600 (+0.2%)
100 1000 1,49763500 1,54138400 (+2.9%)
500 200 2,19020200 2,46196400 (+12.4%)
2500 40 5,39265700 6,68147900 (+23.9%)
8000 12 14,04163600 18,19669600 (+29.6%)
As some values are now decoded outside the helper and passed to it as an
argument the number of arguments of the helper increased, the number
of TCGop needed to load the arguments increased. I suspect that's why
the slow-down in the tests with a high REPT but low LOOP.
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-12-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: bbd8dd5e45b831ef3fda585cf80d08f45cdaba95
https://github.com/qemu/qemu/commit/bbd8dd5e45b831ef3fda585cf80d08f45cdaba95
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: Use gvec to decode XVTSTDC[DS]P
Used gvec to translate XVTSTDCSP and XVTSTDCDP.
xvtstdcsp:
rept loop imm master version prev version current version
25 4000 0 0,206200 0,040730 (-80.2%) 0,040740 (-80.2%)
25 4000 1 0,205120 0,053650 (-73.8%) 0,053510 (-73.9%)
25 4000 3 0,206160 0,058630 (-71.6%) 0,058570 (-71.6%)
25 4000 51 0,217110 0,191490 (-11.8%) 0,192320 (-11.4%)
25 4000 127 0,206160 0,191490 (-7.1%) 0,192640 (-6.6%)
8000 12 0 1,234719 0,418833 (-66.1%) 0,386365 (-68.7%)
8000 12 1 1,232417 1,435979 (+16.5%) 1,462792 (+18.7%)
8000 12 3 1,232760 1,766073 (+43.3%) 1,743990 (+41.5%)
8000 12 51 1,239281 1,319562 (+6.5%) 1,423479 (+14.9%)
8000 12 127 1,231708 1,315760 (+6.8%) 1,426667 (+15.8%)
xvtstdcdp:
rept loop imm master version prev version current version
25 4000 0 0,159930 0,040830 (-74.5%) 0,040610 (-74.6%)
25 4000 1 0,160640 0,053670 (-66.6%) 0,053480 (-66.7%)
25 4000 3 0,160020 0,063030 (-60.6%) 0,062960 (-60.7%)
25 4000 51 0,160410 0,128620 (-19.8%) 0,127470 (-20.5%)
25 4000 127 0,160330 0,127670 (-20.4%) 0,128690 (-19.7%)
8000 12 0 1,190365 0,422146 (-64.5%) 0,388417 (-67.4%)
8000 12 1 1,191292 1,445312 (+21.3%) 1,428698 (+19.9%)
8000 12 3 1,188687 1,980656 (+66.6%) 1,975354 (+66.2%)
8000 12 51 1,191250 1,264500 (+6.1%) 1,355083 (+13.8%)
8000 12 127 1,197313 1,266729 (+5.8%) 1,349156 (+12.7%)
Overall, these instructions are the hardest ones to measure performance
as the gvec implementation is affected by the immediate. Above there are
5 different scenarios when it comes to immediate and 2 when it comes to
rept/loop combination. The immediates scenarios are: all bits are 0
therefore the target register should just be changed to 0, with 1 bit
set, with 2 bits set in a combination the new implementation can deal
with using gvec, 4 bits set and the new implementation can't deal with
it using gvec and all bits set. The rept/loop scenarios are high loop
and low rept (so it should spend more time executing it than translating
it) and high rept low loop (so it should spend more time translating it
than executing this code).
These comparisons are between the upstream version, a previous similar
implementation and a one with a cleaner code(this one).
For a comparison with o previous different implementation:
<20221010191356.83659-13-lucas.araujo@eldorado.org.br>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221019125040.48028-13-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: f003109f710bb39a78c27ce18aa10579340f5a3f
https://github.com/qemu/qemu/commit/f003109f710bb39a78c27ce18aa10579340f5a3f
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M hw/ppc/ppc.c
M hw/ppc/trace-events
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/misc_helper.c
Log Message:
-----------
target/ppc: define PPC_INTERRUPT_* values directly
This enum defines the bit positions in env->pending_interrupts for each
interrupt. However, except for the comparison in kvmppc_set_interrupt,
the values are always used as (1 << PPC_INTERRUPT_*). Define them
directly like that to save some clutter. No functional change intended.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20221011204829.1641124-2-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 7b694df6a6deeac8ede0512f983c70463968021a
https://github.com/qemu/qemu/commit/7b694df6a6deeac8ede0512f983c70463968021a
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/excp_helper.c
M target/ppc/misc_helper.c
Log Message:
-----------
target/ppc: always use ppc_set_irq to set env->pending_interrupts
Use ppc_set_irq to raise/clear interrupts to ensure CPU_INTERRUPT_HARD
will be set/reset accordingly.
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20221011204829.1641124-3-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: de76b85c961378795a9e3044881554b25a4db333
https://github.com/qemu/qemu/commit/de76b85c961378795a9e3044881554b25a4db333
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: split interrupt masking and delivery from ppc_hw_interrupt
Split ppc_hw_interrupt into an interrupt masking method,
ppc_next_unmasked_interrupt, and an interrupt processing method,
ppc_deliver_interrupt.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-4-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: ba2898f79f9d36320abfa7c0589c796810c7186b
https://github.com/qemu/qemu/commit/ba2898f79f9d36320abfa7c0589c796810c7186b
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: prepare to split interrupt masking and delivery by excp_model
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-5-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 2dfecf01952f6d4c9c7698ae55d7a425999acaed
https://github.com/qemu/qemu/commit/2dfecf01952f6d4c9c7698ae55d7a425999acaed
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: create an interrupt masking method for POWER9/POWER10
The new method is identical to ppc_next_unmasked_interrupt_generic,
processor-specific code will be added/removed in the following patches.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-6-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: b00e9a2f2be384820a107c28ff97fb4d6ed84b8a
https://github.com/qemu/qemu/commit/b00e9a2f2be384820a107c28ff97fb4d6ed84b8a
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: remove unused interrupts from p9_next_unmasked_interrupt
Remove the following unused interrupts from the POWER9 interrupt masking
method:
- PPC_INTERRUPT_RESET: only raised for 6xx, 7xx, 970 and POWER5p;
- Debug Interrupt: removed in Power ISA v2.07;
- Critical Input, Watchdog Timer, and Fixed Interval Timer: only defined
for embedded CPUs;
- Critical Doorbell Interrupt: removed in Power ISA v3.0;
- Programmable Interval Timer: 40x-only.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-7-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 3654e238af02fb828b71aa85a4fc475770a3d91a
https://github.com/qemu/qemu/commit/3654e238af02fb828b71aa85a4fc475770a3d91a
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: create an interrupt deliver method for POWER9/POWER10
The new method is identical to ppc_deliver_interrupt, processor-specific
code will be added/removed in the following patches.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-8-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 1e75ffe40efcf07c3576a9ffb76235975ca96ce7
https://github.com/qemu/qemu/commit/1e75ffe40efcf07c3576a9ffb76235975ca96ce7
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: remove unused interrupts from p9_deliver_interrupt
Remove the following unused interrupts from the POWER9 interrupt
processing method:
- PPC_INTERRUPT_RESET: only raised for 6xx, 7xx, 970 and POWER5p;
- Debug Interrupt: removed in Power ISA v2.07;
- Critical Input, Watchdog Timer, and Fixed Interval Timer: only defined
for embedded CPUs;
- Critical Doorbell Interrupt: removed in Power ISA v3.0;
- Programmable Interval Timer: 40x-only.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-9-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: ed3a24c95a9d8d870bf671d5675b8b4b32a0db75
https://github.com/qemu/qemu/commit/ed3a24c95a9d8d870bf671d5675b8b4b32a0db75
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: remove generic architecture checks from p9_deliver_interrupt
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-10-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 0ccd9d67b1ee9289dd96f2d133a618f97f7a89ab
https://github.com/qemu/qemu/commit/0ccd9d67b1ee9289dd96f2d133a618f97f7a89ab
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: move power-saving interrupt masking out of cpu_has_work_POWER9
Move the interrupt masking logic out of cpu_has_work_POWER9 in a new
method, p9_interrupt_powersave, that only returns an interrupt if it can
wake the processor from power-saving mode.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-11-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 27796411271837b45c635c537e70d1ecfdcd4e1c
https://github.com/qemu/qemu/commit/27796411271837b45c635c537e70d1ecfdcd4e1c
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/internal.h
Log Message:
-----------
target/ppc: add power-saving interrupt masking logic to
p9_next_unmasked_interrupt
Export p9_interrupt_powersave and use it in p9_next_unmasked_interrupt.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-12-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: a9899d42012c49169074fb85b61c78aa6e17af8e
https://github.com/qemu/qemu/commit/a9899d42012c49169074fb85b61c78aa6e17af8e
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: create an interrupt masking method for POWER8
The new method is identical to ppc_next_unmasked_interrupt_generic,
processor-specific code will be added/removed in the following patches.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-13-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: f6194fdde2e37743d2833b66fc272472190e51cc
https://github.com/qemu/qemu/commit/f6194fdde2e37743d2833b66fc272472190e51cc
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: remove unused interrupts from p8_next_unmasked_interrupt
Remove the following unused interrupts from the POWER8 interrupt masking
method:
- PPC_INTERRUPT_RESET: only raised for 6xx, 7xx, 970, and POWER5p;
- Debug Interrupt: removed in Power ISA v2.07;
- Hypervisor Virtualization: introduced in Power ISA v3.0;
- Critical Input, Watchdog Timer, and Fixed Interval Timer: only defined
for embedded CPUs;
- Critical Doorbell: processor does not implement the "Embedded.Processor
Control" category;
- Programmable Interval Timer: 40x-only;
- PPC_INTERRUPT_THERM: only raised for 970 and POWER5p;
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-14-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 6527e757db546fcdc4a0a695325fb3f1fb0804d5
https://github.com/qemu/qemu/commit/6527e757db546fcdc4a0a695325fb3f1fb0804d5
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: create an interrupt deliver method for POWER8
The new method is identical to ppc_deliver_interrupt, processor-specific
code will be added/removed in the following patches.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-15-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 567372673e4e3aaaa0391bb5ea127e387f4dbd34
https://github.com/qemu/qemu/commit/567372673e4e3aaaa0391bb5ea127e387f4dbd34
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: remove unused interrupts from p8_deliver_interrupt
Remove the following unused interrupts from the POWER8 interrupt
processing method:
- PPC_INTERRUPT_RESET: only raised for 6xx, 7xx, 970 and POWER5p;
- Debug Interrupt: removed in Power ISA v2.07;
- Hypervisor Virtualization: introduced in Power ISA v3.0;
- Critical Input, Watchdog Timer, and Fixed Interval Timer: only defined
for embedded CPUs;
- Critical Doorbell: processor does not implement the
"Embedded.Processor Control" category;
- Programmable Interval Timer: 40x-only;
- PPC_INTERRUPT_THERM: only raised for 970 and POWER5p;
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-16-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: d66b441d64ca63bb9b50d5d8a054b1836297a6e3
https://github.com/qemu/qemu/commit/d66b441d64ca63bb9b50d5d8a054b1836297a6e3
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: remove generic architecture checks from p8_deliver_interrupt
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-17-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 788ff1ce44b813475ddcb95726bdd3afdaa40d6d
https://github.com/qemu/qemu/commit/788ff1ce44b813475ddcb95726bdd3afdaa40d6d
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: move power-saving interrupt masking out of cpu_has_work_POWER8
Move the interrupt masking logic out of cpu_has_work_POWER8 in a new
method, p8_interrupt_powersave, that only returns an interrupt if it can
wake the processor from power-saving mode.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-18-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 64a9b5eebef97d5b742b162625d5bc262be832ec
https://github.com/qemu/qemu/commit/64a9b5eebef97d5b742b162625d5bc262be832ec
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/internal.h
Log Message:
-----------
target/ppc: add power-saving interrupt masking logic to
p8_next_unmasked_interrupt
Export p8_interrupt_powersave and use it in p8_next_unmasked_interrupt.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-19-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: bf303fb3f11c3e131f315e44b792ad79a8ae07bb
https://github.com/qemu/qemu/commit/bf303fb3f11c3e131f315e44b792ad79a8ae07bb
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: create an interrupt masking method for POWER7
The new method is identical to ppc_next_unmasked_interrupt_generic,
processor-specific code will be added/removed in the following patches.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-20-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: c8e1de2e421fcb5ce88443bd819f919e3eab13f2
https://github.com/qemu/qemu/commit/c8e1de2e421fcb5ce88443bd819f919e3eab13f2
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: remove unused interrupts from p7_next_unmasked_interrupt
Remove the following unused interrupts from the POWER7 interrupt masking
method:
- PPC_INTERRUPT_RESET: only raised for 6xx, 7xx, 970 and POWER5p;
- Hypervisor Virtualization: introduced in Power ISA v3.0;
- Hypervisor Doorbell and Event-Based Branch: introduced in
Power ISA v2.07;
- Critical Input, Watchdog Timer, and Fixed Interval Timer: only defined
for embedded CPUs;
- Doorbell and Critical Doorbell Interrupt: processor does not implement
the Embedded.Processor Control category;
- Programmable Interval Timer: 40x-only;
- PPC_INTERRUPT_THERM: only raised for 970 and POWER5p;
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-21-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: d93a48561c59b08958c9c37191248492a7acb8e4
https://github.com/qemu/qemu/commit/d93a48561c59b08958c9c37191248492a7acb8e4
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: create an interrupt deliver method for POWER7
The new method is identical to ppc_deliver_interrupt, processor-specific
code will be added/removed in the following patches.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-22-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: ec0f351af109e2b3d94ae50f5fe560a435b544d1
https://github.com/qemu/qemu/commit/ec0f351af109e2b3d94ae50f5fe560a435b544d1
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: remove unused interrupts from p7_deliver_interrupt
Remove the following unused interrupts from the POWER7 interrupt
processing method:
- PPC_INTERRUPT_RESET: only raised for 6xx, 7xx, 970 and POWER5p;
- Hypervisor Virtualization: introduced in Power ISA v3.0;
- Hypervisor Doorbell and Event-Based Branch: introduced in
Power ISA v2.07;
- Critical Input, Watchdog Timer, and Fixed Interval Timer: only defined
for embedded CPUs;
- Doorbell and Critical Doorbell Interrupt: processor does not implement
the Embedded.Processor Control category;
- Programmable Interval Timer: 40x-only;
- PPC_INTERRUPT_THERM: only raised for 970 and POWER5p;
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-23-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 3f34e809ac856831949843d2adc45fab00f8b244
https://github.com/qemu/qemu/commit/3f34e809ac856831949843d2adc45fab00f8b244
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: remove generic architecture checks from p7_deliver_interrupt
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-24-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: b34d358a212908326a43216162e90934015b02e7
https://github.com/qemu/qemu/commit/b34d358a212908326a43216162e90934015b02e7
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: move power-saving interrupt masking out of cpu_has_work_POWER7
Move the interrupt masking logic out of cpu_has_work_POWER7 in a new
method, p7_interrupt_powersave, that only returns an interrupt if it can
wake the processor from power-saving mode.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-25-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 022b7128535d0ec963f724008a5f8b6a842d92ae
https://github.com/qemu/qemu/commit/022b7128535d0ec963f724008a5f8b6a842d92ae
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/internal.h
Log Message:
-----------
target/ppc: add power-saving interrupt masking logic to
p7_next_unmasked_interrupt
Export p7_interrupt_powersave and use it in p7_next_unmasked_interrupt.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-26-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 6a8e8188c3c99e987e3d5b9df614a68a5d4bd1e0
https://github.com/qemu/qemu/commit/6a8e8188c3c99e987e3d5b9df614a68a5d4bd1e0
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/cpu.c
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: remove ppc_store_lpcr from CONFIG_USER_ONLY builds
Writes to LPCR are hypervisor privileged.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20221011204829.1641124-27-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 2fdedcbc69564f52a1c33bedfa291707e998a132
https://github.com/qemu/qemu/commit/2fdedcbc69564f52a1c33bedfa291707e998a132
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M hw/ppc/pnv_core.c
M hw/ppc/ppc.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_rtas.c
M target/ppc/cpu.c
M target/ppc/cpu.h
M target/ppc/excp_helper.c
M target/ppc/helper.h
M target/ppc/helper_regs.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: introduce ppc_maybe_interrupt
This new method will check if any pending interrupt was unmasked and
then call cpu_interrupt/cpu_reset_interrupt accordingly. Code that
raises/lowers or masks/unmasks interrupts should call this method to
keep CPU_INTERRUPT_HARD coherent with env->pending_interrupts.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221021142156.4134411-2-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: ab9cfa04523e0312c741e16ca54c5fa4e1eee9e2
https://github.com/qemu/qemu/commit/ab9cfa04523e0312c741e16ca54c5fa4e1eee9e2
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: unify cpu->has_work based on cs->interrupt_request
Now that cs->interrupt_request indicates if there is any unmasked
interrupt, checking if the CPU has work to do can be simplified to a
single check that works for all CPU models.
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20221021142156.4134411-3-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 9c713713dac70fe7eaa9b403234a71024a729eb4
https://github.com/qemu/qemu/commit/9c713713dac70fe7eaa9b403234a71024a729eb4
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/internal.h
Log Message:
-----------
target/ppc: move the p*_interrupt_powersave methods to excp_helper.c
Move the methods to excp_helper.c and make them static.
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20221021142156.4134411-4-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 2a48dd7cbd456ac2e27b3cf66cfb7e2e1886dbf4
https://github.com/qemu/qemu/commit/2a48dd7cbd456ac2e27b3cf66cfb7e2e1886dbf4
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M hw/ppc/meson.build
M hw/ppc/ppc440_uc.c
A hw/ppc/ppc4xx_sdram.c
Log Message:
-----------
ppc440_uc.c: Move DDR2 SDRAM controller model to ppc4xx_sdram.c
In order to move PPC4xx SDRAM controller models together move out the
DDR2 controller model from ppc440_uc.c into a new ppc4xx_sdram.c file.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id:
<2f2900f93e997480e54b7bf9c32bb482a0fb1022.1666194485.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: fa446fc54082c0c87a2edf7048bd17112773f0ef
https://github.com/qemu/qemu/commit/fa446fc54082c0c87a2edf7048bd17112773f0ef
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M hw/ppc/ppc4xx_devs.c
M hw/ppc/ppc4xx_sdram.c
Log Message:
-----------
ppc4xx_devs.c: Move DDR SDRAM controller model to ppc4xx_sdram.c
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id:
<3ea98072dbeb757942e25dcfcdd6a7a47738d2ca.1666194485.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 080741abc293e79b6e860e2c8d66bfe519090c86
https://github.com/qemu/qemu/commit/080741abc293e79b6e860e2c8d66bfe519090c86
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M hw/ppc/ppc4xx_devs.c
M hw/ppc/ppc4xx_sdram.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc4xx_sdram: Move ppc4xx_sdram_banks() to ppc4xx_sdram.c
This function is only used by the ppc4xx memory controller models so
it can be made static.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id:
<b1504a82157a586aa284e8ee3b427b9a07b24169.1666194485.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: c8c6d68af7e7fba666a684c684f86ddbf9f20bee
https://github.com/qemu/qemu/commit/c8c6d68af7e7fba666a684c684f86ddbf9f20bee
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M hw/ppc/ppc4xx_sdram.c
Log Message:
-----------
ppc4xx_sdram: Use hwaddr for memory bank size
This resolves the target_ulong dependency that's clearly wrong and was
also noted in a fixme comment.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<92fdc5f9cc76bf45831428b3ec8d9fc6241b7190.1666194485.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 61cfe0df903c1c1a0654781db0788da9cd4da32a
https://github.com/qemu/qemu/commit/61cfe0df903c1c1a0654781db0788da9cd4da32a
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M hw/ppc/ppc4xx_sdram.c
Log Message:
-----------
ppc4xx_sdram: Rename local state variable for brevity
Rename the sdram local state variable to s in dcr read/write functions
and reset methods for better readability and to match realize methods.
Other places not converted will be changed or removed in subsequent
patches.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<8e7539cb1fccd7556b68351c4dcf62534c3a69cf.1666194485.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 424a660c58a6b950363d42b79a30e651c1037550
https://github.com/qemu/qemu/commit/424a660c58a6b950363d42b79a30e651c1037550
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M hw/ppc/ppc4xx_sdram.c
M hw/ppc/trace-events
Log Message:
-----------
ppc4xx_sdram: Generalise bank setup
Currently only base and size are set on initial bank creation and bcr
value is computed on mapping the region. Set bcr at init so the bcr
encoding method becomes local to the controller model and mapping and
unmapping can operate on the bank so it can be shared between
different controller models. This patch converts the DDR2 controller.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<51b957b4b2d714a1072aa2589b979e08411640df.1666194485.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 54a3527e427b7df33ffcea3ad0ab56f7a0a61dd9
https://github.com/qemu/qemu/commit/54a3527e427b7df33ffcea3ad0ab56f7a0a61dd9
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M hw/ppc/ppc4xx_sdram.c
Log Message:
-----------
ppc4xx_sdram: Convert DDR SDRAM controller to new bank handling
Use the generic bank handling introduced in previous patch in the DDR
SDRAM controller too. This also fixes previously broken region unmap
due to sdram_ddr_unmap_bcr() ignoring container region so it crashed
with an assert when the guest tried to disable the controller.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<fc7c50e365d0027a659111e9cd67f9b93113a163.1666194485.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 286787f105c3216028841fd86c4e563af6b1b9e0
https://github.com/qemu/qemu/commit/286787f105c3216028841fd86c4e563af6b1b9e0
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M hw/ppc/ppc4xx_sdram.c
Log Message:
-----------
ppc4xx_sdram: Add errp parameter to ppc4xx_sdram_banks()
Do not exit from ppc4xx_sdram_banks() but report error via an errp
parameter instead.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<04bb3445439c2f37b99e74b3fdf4e62c2e6f7e04.1666194485.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 8b3d1c49a9f0f315d2b292c1791430c0f382afa4
https://github.com/qemu/qemu/commit/8b3d1c49a9f0f315d2b292c1791430c0f382afa4
Author: Leandro Lupori <leandro.lupori@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper_regs.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Add new PMC HFLAGS
Add 2 new PMC related HFLAGS:
- HFLAGS_PMCJCE - value of MMCR0 PMCjCE bit
- HFLAGS_PMC_OTHER - set if a PMC other than PMC5-6 is enabled
These flags allow further optimization of PMC5 update code, by
allowing frequently tested conditions to be performed at
translation time.
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221025202424.195984-3-leandro.lupori@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: eeaaefe9fa8b95a7ed39ee86257f3bf1af751804
https://github.com/qemu/qemu/commit/eeaaefe9fa8b95a7ed39ee86257f3bf1af751804
Author: Leandro Lupori <leandro.lupori@eldorado.org.br>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M target/ppc/helper.h
M target/ppc/power8-pmu.c
M target/ppc/power8-pmu.h
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Increment PMC5 with inline insns
Profiling QEMU during Fedora 35 for PPC64 boot revealed that
6.39% of total time was being spent in helper_insns_inc(), on a
POWER9 machine. To avoid calling this helper every time PMCs had
to be incremented, an inline implementation of PMC5 increment and
check for overflow was developed. This led to a reduction of
about 12% in Fedora's boot time.
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221025202424.195984-4-leandro.lupori@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: c593d1cc2555c5fe6a6a558f4d2bdc3bfd6713de
https://github.com/qemu/qemu/commit/c593d1cc2555c5fe6a6a558f4d2bdc3bfd6713de
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M docs/system/ppc/ppce500.rst
Log Message:
-----------
docs/system/ppc/ppce500: Use qemu-system-ppc64 across the board(s)
The documentation suggests that there is a qemu-system-ppc32 binary
while the 32 bit version is actually just named qemu-system-ppc. Settle
on qemu-system-ppc64 which also works for 32 bit machines and causes
less clutter in the documentation.
Found-by: BALATON Zoltan <balaton@eik.bme.hu>
Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20221018210146.193159-2-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 334c388f25707a234c4a0dea05b9df08d7746638
https://github.com/qemu/qemu/commit/334c388f25707a234c4a0dea05b9df08d7746638
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M hw/block/pflash_cfi01.c
M hw/block/pflash_cfi02.c
Log Message:
-----------
hw/block/pflash_cfi0{1, 2}: Error out if device length isn't a power of two
According to the JEDEC standard the device length is communicated to an
OS as an exponent (power of two).
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221018210146.193159-3-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: c038e5745eca4851bb2ba515324f3e97c68f27ce
https://github.com/qemu/qemu/commit/c038e5745eca4851bb2ba515324f3e97c68f27ce
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M hw/sd/sdhci-internal.h
M hw/sd/sdhci.c
Log Message:
-----------
hw/sd/sdhci-internal: Unexport ESDHC defines
These defines aren't used outside of sdhci.c, so can be defined there.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221018210146.193159-4-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 1e76667f7adf48c6c3596aaa26b8886b57b8498d
https://github.com/qemu/qemu/commit/1e76667f7adf48c6c3596aaa26b8886b57b8498d
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-28 (Fri, 28 Oct 2022)
Changed paths:
M hw/sd/sdhci.c
Log Message:
-----------
hw/sd/sdhci: Rename ESDHC_* defines to USDHC_*
The device model's functions start with "usdhc_", so rename the defines
accordingly for consistency.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20221018210146.193159-5-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 63e4bf8e84721231ea447b0e4afcb0a4378763c2
https://github.com/qemu/qemu/commit/63e4bf8e84721231ea447b0e4afcb0a4378763c2
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-29 (Sat, 29 Oct 2022)
Changed paths:
M docs/system/ppc/ppce500.rst
M hw/ppc/Kconfig
M hw/ppc/e500.c
Log Message:
-----------
hw/ppc/e500: Implement pflash handling
Allows e500 boards to have their root file system reside on flash using
only builtin devices located in the eLBC memory region.
Note that the flash memory area is only created when a -pflash argument is
given, and that the size is determined by the given file. The idea is to
put users into control.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221018210146.193159-6-shentey@gmail.com>
[danielhb: use memory_region_size() in mmio_size]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: fb22d743b93b49b73930aff40d3ba9d252f81a56
https://github.com/qemu/qemu/commit/fb22d743b93b49b73930aff40d3ba9d252f81a56
Author: Leandro Lupori <leandro.lupori@eldorado.org.br>
Date: 2022-10-29 (Sat, 29 Oct 2022)
Changed paths:
M target/ppc/mmu-radix64.c
Log Message:
-----------
target/ppc: Fix regression in Radix MMU
Commit 47e83d9107 ended up unintentionally changing the control flow
of ppc_radix64_process_scoped_xlate(). When guest_visible is false,
it must not raise an exception, even if the radix configuration is
not valid.
This regression prevented Linux boot in a nested environment with
L1 using TCG and emulating KVM (cap-nested-hv=on) and L2 using
KVM. L2 would hang on Linux's futex_init(), when it tested how a
futex_atomic_cmpxchg_inatomic() handled a fault, because L1 would
start a loop of trying to perform partition scoped translations
and raising exceptions.
Fixes: 47e83d9107 ("target/ppc: Improve Radix xlate level validation")
Reported-by: Victor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Tested-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221028183617.121786-1-leandro.lupori@eldorado.org.br>
[danielhb: use %"PRIu64" to print 'nls']
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: f91c5d0f13fa3ffb230eedbee2b05bcc8f4fc296
https://github.com/qemu/qemu/commit/f91c5d0f13fa3ffb230eedbee2b05bcc8f4fc296
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tcg/sparc/tcg-target.c.inc
M tcg/sparc/tcg-target.h
M tcg/tcg.c
Log Message:
-----------
tcg/sparc: Remove support for sparc32plus
Since 9b9c37c36439, we have only supported sparc64 cpus.
Debian and Gentoo now only support 64-bit sparc64 userland,
so it is time to drop the 32-bit sparc64 userland: sparc32plus.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 18ba585f925fc8e9f6351ccdddb09865e9716553
https://github.com/qemu/qemu/commit/18ba585f925fc8e9f6351ccdddb09865e9716553
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M MAINTAINERS
M meson.build
R tcg/sparc/tcg-target-con-set.h
R tcg/sparc/tcg-target-con-str.h
R tcg/sparc/tcg-target.c.inc
R tcg/sparc/tcg-target.h
A tcg/sparc64/tcg-target-con-set.h
A tcg/sparc64/tcg-target-con-str.h
A tcg/sparc64/tcg-target.c.inc
A tcg/sparc64/tcg-target.h
Log Message:
-----------
tcg/sparc64: Rename from tcg/sparc
Emphasize that we only support full 64-bit code generation.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 5352758ad46ff0c9bbe33171684b34aad231c4f2
https://github.com/qemu/qemu/commit/5352758ad46ff0c9bbe33171684b34aad231c4f2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tcg/sparc64/tcg-target-con-set.h
M tcg/sparc64/tcg-target-con-str.h
M tcg/sparc64/tcg-target.c.inc
Log Message:
-----------
tcg/sparc64: Remove sparc32plus constraints
With sparc64 we need not distinguish between registers that
can hold 32-bit values and those that can hold 64-bit values.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 8f77f2dffcb0ddfd16411a1b72e560890cb57594
https://github.com/qemu/qemu/commit/8f77f2dffcb0ddfd16411a1b72e560890cb57594
Author: Icenowy Zheng <uwu@icenowy.me>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M tcg/tcg.c
Log Message:
-----------
tcg/tci: fix logic error when registering helpers via FFI
When registering helpers via FFI for TCI, the inner loop that iterates
parameters of the helper reuses (and thus pollutes) the same variable
used by the outer loop that iterates all helpers, thus made some helpers
unregistered.
Fix this logic error by using a dedicated temporary variable for the
inner loop.
Fixes: 22f15579fa ("tcg: Build ffi data structures for helpers")
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Message-Id: <20221028072145.1593205-1-uwu@icenowy.me>
[rth: Move declaration of j to the for loop itself]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 26655c8602413ea57bb6ee23cc23042c9236d49a
https://github.com/qemu/qemu/commit/26655c8602413ea57bb6ee23cc23042c9236d49a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M accel/tcg/internal.h
M accel/tcg/translate-all.c
M include/exec/exec-all.h
Log Message:
-----------
accel/tcg: Introduce cpu_unwind_state_data
Add a way to examine the unwind data without actually
restoring the data back into env.
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f135fdbc6cf77a612b65b9f1dc613528187b44ee
https://github.com/qemu/qemu/commit/f135fdbc6cf77a612b65b9f1dc613528187b44ee
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M target/i386/helper.c
Log Message:
-----------
target/i386: Use cpu_unwind_state_data for tpr access
Avoid cpu_restore_state, and modifying env->eip out from
underneath the translator with TARGET_TB_PCREL. There is
some slight duplication from x86_restore_state_to_opc,
but it's just a few lines.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1269
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 7de10240c99e22f1c7c8fc533e79f4d96eede86b
https://github.com/qemu/qemu/commit/7de10240c99e22f1c7c8fc533e79f4d96eede86b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M target/openrisc/sys_helper.c
Log Message:
-----------
target/openrisc: Always exit after mtspr npc
We have called cpu_restore_state asserting will_exit.
Do not go back on that promise. This affects icount.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ba56b29a262d50013d6abb49cb9ffe3eaf604629
https://github.com/qemu/qemu/commit/ba56b29a262d50013d6abb49cb9ffe3eaf604629
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M target/openrisc/sys_helper.c
Log Message:
-----------
target/openrisc: Use cpu_unwind_state_data for mfspr
Since we do not plan to exit, use cpu_unwind_state_data
and extract exactly the data requested.
This is a bug fix, in that we no longer clobber dflag.
Consider:
l.j L2 // branch
l.mfspr r1, ppc // delay
L1: boom
L2: l.lwa r3, (r4)
Here, dflag would be set by cpu_restore_state (because that is the current
state of the cpu), but but not cleared by tb_stop on exiting the TB
(because DisasContext has recorded the current value as zero).
The next TB begins at L2 with dflag incorrectly set. If the load has a
tlb miss, then the exception will be delivered as per a delay slot:
with DSX set in the status register and PC decremented (delay slots
restart by re-executing the branch). This will cause the return from
interrupt to go to L1, and boom!
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ab8d414ac8d482459998af5c1d289a20730255d1
https://github.com/qemu/qemu/commit/ab8d414ac8d482459998af5c1d289a20730255d1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M accel/tcg/cpu-exec-common.c
M accel/tcg/translate-all.c
M include/exec/exec-all.h
M target/alpha/helper.c
M target/alpha/mem_helper.c
M target/arm/op_helper.c
M target/arm/tlb_helper.c
M target/cris/helper.c
M target/i386/tcg/sysemu/svm_helper.c
M target/m68k/op_helper.c
M target/microblaze/helper.c
M target/nios2/op_helper.c
M target/openrisc/sys_helper.c
M target/ppc/excp_helper.c
M target/s390x/tcg/excp_helper.c
M target/tricore/op_helper.c
M target/xtensa/helper.c
Log Message:
-----------
accel/tcg: Remove will_exit argument from cpu_restore_state
The value passed is always true, and if the target's
synchronize_from_tb hook is non-trivial, not exiting
may be erroneous.
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6b50c0d9c5a564a437c5a5a5aadd5ed817d56312
https://github.com/qemu/qemu/commit/6b50c0d9c5a564a437c5a5a5aadd5ed817d56312
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M accel/tcg/internal.h
M accel/tcg/tb-maint.c
M accel/tcg/translate-all.c
Log Message:
-----------
accel/tcg: Remove reset_icount argument from cpu_restore_state_from_tb
The value passed is always true.
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: cb375590983fc3d23600d02ba05a05d34fe44150
https://github.com/qemu/qemu/commit/cb375590983fc3d23600d02ba05a05d34fe44150
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M target/i386/helper.h
M target/i386/tcg/cc_helper.c
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: Expand eflags updates inline
The helpers for reset_rf, cli, sti, clac, stac are
completely trivial; implement them inline.
Drop some nearby #if 0 code.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 7f8c044018555dcc36eb5af1d5d6cebc85ebd330
https://github.com/qemu/qemu/commit/7f8c044018555dcc36eb5af1d5d6cebc85ebd330
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M scripts/nsis.py
Log Message:
-----------
scripts/nsis.py: Drop the unnecessary path separator
There is no need to append a path separator to the destination
directory that is passed to "make install".
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20220908132817.1831008-2-bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Commit: 93dbca2ce9f112ee8bfd641fa2ea6ff0771c6c39
https://github.com/qemu/qemu/commit/93dbca2ce9f112ee8bfd641fa2ea6ff0771c6c39
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M scripts/nsis.py
Log Message:
-----------
scripts/nsis.py: Fix destination directory name when invoked on Windows
"make installer" on Windows fails with the following message:
Traceback (most recent call last):
File "G:\msys64\home\foo\git\qemu\scripts\nsis.py", line 89, in <module>
main()
File "G:\msys64\home\foo\git\qemu\scripts\nsis.py", line 34, in main
with open(
OSError: [Errno 22] Invalid argument:
'R:/Temp/tmpw83xhjquG:/msys64/qemu/system-emulations.nsh'
ninja: build stopped: subcommand failed.
Use os.path.splitdrive() to form a canonical path without the drive
letter on Windows. This works with cross-build on Linux too.
Fixes: 8adfeba953e0 ("meson: add NSIS building")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20220908132817.1831008-3-bmeng.cn@gmail.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Commit: a3c1e6458dbbe3647ccadfb39cbb585fdc4373a5
https://github.com/qemu/qemu/commit/a3c1e6458dbbe3647ccadfb39cbb585fdc4373a5
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M meson.build
M scripts/nsis.py
Log Message:
-----------
scripts/nsis.py: Automatically package required DLLs of QEMU executables
At present packaging the required DLLs of QEMU executables is a
manual process, and error prone.
Actually build/config-host.mak contains a GLIB_BINDIR variable
which is the directory where glib and other DLLs reside. This
works for both Windows native build and cross-build on Linux.
We can use it as the search directory for DLLs and automate
the whole DLL packaging process.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20220908132817.1831008-4-bmeng.cn@gmail.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Tested-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Commit: 588fec8a4c3fe9e0d1cb3f7ea6fdd46221e42814
https://github.com/qemu/qemu/commit/588fec8a4c3fe9e0d1cb3f7ea6fdd46221e42814
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M block/nfs.c
Log Message:
-----------
block/nfs: Fix 32-bit Windows build
libnfs.h declares nfs_fstat() as the following for win32:
int nfs_fstat(struct nfs_context *nfs, struct nfsfh *nfsfh,
struct __stat64 *st);
The 'st' parameter should be of type 'struct __stat64'. The
codes happen to build successfully for 64-bit Windows, but it
does not build for 32-bit Windows.
Fixes: 6542aa9c75bc ("block: add native support for NFS")
Fixes: 18a8056e0bc7 ("block/nfs: cache allocated filesize for read-only files")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20220908132817.1831008-6-bmeng.cn@gmail.com>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Commit: 395a90be6f0af51732540c5e632c0fe49222e28c
https://github.com/qemu/qemu/commit/395a90be6f0af51732540c5e632c0fe49222e28c
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M .gitlab-ci.d/cirrus/freebsd-12.vars
M .gitlab-ci.d/cirrus/freebsd-13.vars
M MAINTAINERS
M accel/dummy-cpus.c
M accel/meson.build
M accel/qtest/meson.build
M hw/net/e1000_regs.h
M hw/s390x/pv.c
M hw/s390x/tod-kvm.c
M include/hw/core/cpu.h
M include/qemu/sockets.h
M softmmu/cpus.c
M target/s390x/tcg/translate_vx.c.inc
M tests/docker/dockerfiles/alpine.docker
M tests/docker/dockerfiles/centos8.docker
M tests/docker/dockerfiles/debian-amd64-cross.docker
M tests/docker/dockerfiles/debian-amd64.docker
M tests/docker/dockerfiles/debian-arm64-cross.docker
M tests/docker/dockerfiles/debian-armel-cross.docker
M tests/docker/dockerfiles/debian-armhf-cross.docker
M tests/docker/dockerfiles/debian-mips64el-cross.docker
M tests/docker/dockerfiles/debian-mipsel-cross.docker
M tests/docker/dockerfiles/debian-ppc64el-cross.docker
M tests/docker/dockerfiles/debian-s390x-cross.docker
M tests/docker/dockerfiles/fedora.docker
M tests/docker/dockerfiles/opensuse-leap.docker
M tests/docker/dockerfiles/ubuntu2004.docker
M tests/lcitool/libvirt-ci
M tests/lcitool/projects/qemu.yml
M tests/qtest/cxl-test.c
M tests/qtest/dbus-vmstate-test.c
M tests/qtest/device-plug-test.c
M tests/qtest/libqmp.c
M tests/qtest/libqos/e1000e.c
M tests/qtest/libqos/meson.build
M tests/qtest/libqtest.c
M tests/qtest/libqtest.h
M tests/qtest/migration-test.c
M tests/qtest/tpm-crb-swtpm-test.c
M tests/qtest/tpm-tis-device-swtpm-test.c
M tests/qtest/tpm-tis-swtpm-test.c
M tests/qtest/tpm-util.c
M tests/qtest/tpm-util.h
M tests/tcg/s390x/Makefile.target
A tests/tcg/s390x/vistr.c
M tests/vm/freebsd
M tests/vm/openbsd
M util/osdep.c
Log Message:
-----------
Merge tag 'pull-request-2022-10-28' of https://gitlab.com/thuth/qemu into
staging
* Fix and test the VISTR instruction on s390x
* Some more small s390x fixes and maintainer updates
* Make sure to remove all temporary files from qtests
* OpenBSD VM test update to version 7.2
* Add sndio to FreeBSD tests
* More patches to enable the qtests on Windows
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# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 28 Oct 2022 09:20:31 EDT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2022-10-28' of https://gitlab.com/thuth/qemu: (21 commits)
tests/qtest: libqtest: Correct the timeout unit of blocking receive calls for
win32
tests/qtest: libqos: Do not build virtio-9p unconditionally
tests/qtest: migration-test: Make sure QEMU process "to" exited after
migration is canceled
tests/qtest: libqtest: Introduce qtest_wait_qemu()
tests/qtest: Use EXIT_FAILURE instead of magic number
tests/qtest: device-plug-test: Reverse the usage of double/single quotes
tests/qtest: Support libqtest to build and run on Windows
tests/qtest: Use send/recv for socket communication
accel/qtest: Support qtest accelerator for Windows
tests: Add sndio to the FreeBSD CI containers / VM
tests/vm: update openbsd to release 7.2
tests/qtest/libqos/e1000e: Use e1000_regs.h
tests/qtest/cxl-test: Remove temporary directories after testing
tests/qtest/tpm: Clean up remainders of swtpm
MAINTAINERS: target/s390x/: add Ilya as reviewer
tests/tcg/s390x: Add a test for the vistr instruction
target/s390x: Fix emulation of the VISTR instruction
tests/tcg/s390x: Test compiler flags only once, not every time
s390x/tod-kvm: don't save/restore the TOD in PV guests
s390x: step down as general arch maintainer
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 179938097df4de34b13527ad1fd469f501548b07
https://github.com/qemu/qemu/commit/179938097df4de34b13527ad1fd469f501548b07
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M docs/system/ppc/ppce500.rst
M hw/block/pflash_cfi01.c
M hw/block/pflash_cfi02.c
M hw/ppc/Kconfig
M hw/ppc/e500.c
M hw/ppc/meson.build
M hw/ppc/pnv_core.c
M hw/ppc/ppc.c
M hw/ppc/ppc440_uc.c
M hw/ppc/ppc4xx_devs.c
A hw/ppc/ppc4xx_sdram.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_rtas.c
M hw/ppc/trace-events
M hw/sd/sdhci-internal.h
M hw/sd/sdhci.c
M include/hw/ppc/ppc4xx.h
M target/ppc/cpu.c
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/helper_regs.c
M target/ppc/insn32.decode
M target/ppc/int_helper.c
M target/ppc/misc_helper.c
M target/ppc/mmu-radix64.c
M target/ppc/power8-pmu.c
M target/ppc/power8-pmu.h
M target/ppc/translate.c
A target/ppc/translate/processor-ctrl-impl.c.inc
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vmx-ops.c.inc
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
Merge tag 'pull-ppc-20221029' of https://gitlab.com/danielhb/qemu into staging
ppc patch queue for 2022-10-29:
This queue has the second part of the ppc4xx_sdram cleanups, doorbell
instructions for POWER8, new pflash handling for the e500 machine and a
Radix MMU regression fix.
It also has a lot of performance optimizations in the PowerPC emulation
done by the researchers of the Eldorado institute. Between using gvec
for VMX/VSX instructions, a full rework of the interrupt model and PMU
optimizations, they managed to drastically speed up the emulation of
powernv8/9/10 machines. Here's an example with avocado tests:
- with master:
tests/avocado/boot_linux_console.py:BootLinuxConsole.test_ppc_powernv8:
PASS (38.89 s)
tests/avocado/boot_linux_console.py:BootLinuxConsole.test_ppc_powernv9:
PASS (43.89 s)
- with this queue applied:
tests/avocado/boot_linux_console.py:BootLinuxConsole.test_ppc_powernv8:
PASS (21.23 s)
tests/avocado/boot_linux_console.py:BootLinuxConsole.test_ppc_powernv9:
PASS (22.58 s)
Other ppc machines, like pseries, also had a noticeable performance
boost.
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# gpg: Signature made Sat 29 Oct 2022 07:09:50 EDT
# gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>"
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164
* tag 'pull-ppc-20221029' of https://gitlab.com/danielhb/qemu: (63 commits)
target/ppc: Fix regression in Radix MMU
hw/ppc/e500: Implement pflash handling
hw/sd/sdhci: Rename ESDHC_* defines to USDHC_*
hw/sd/sdhci-internal: Unexport ESDHC defines
hw/block/pflash_cfi0{1, 2}: Error out if device length isn't a power of two
docs/system/ppc/ppce500: Use qemu-system-ppc64 across the board(s)
target/ppc: Increment PMC5 with inline insns
target/ppc: Add new PMC HFLAGS
ppc4xx_sdram: Add errp parameter to ppc4xx_sdram_banks()
ppc4xx_sdram: Convert DDR SDRAM controller to new bank handling
ppc4xx_sdram: Generalise bank setup
ppc4xx_sdram: Rename local state variable for brevity
ppc4xx_sdram: Use hwaddr for memory bank size
ppc4xx_sdram: Move ppc4xx_sdram_banks() to ppc4xx_sdram.c
ppc4xx_devs.c: Move DDR SDRAM controller model to ppc4xx_sdram.c
ppc440_uc.c: Move DDR2 SDRAM controller model to ppc4xx_sdram.c
target/ppc: move the p*_interrupt_powersave methods to excp_helper.c
target/ppc: unify cpu->has_work based on cs->interrupt_request
target/ppc: introduce ppc_maybe_interrupt
target/ppc: remove ppc_store_lpcr from CONFIG_USER_ONLY builds
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: dce4fd0c0192c35b15b16b2199b719022b901a8c
https://github.com/qemu/qemu/commit/dce4fd0c0192c35b15b16b2199b719022b901a8c
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M bsd-user/host/i386/host-signal.h
M bsd-user/host/x86_64/host-signal.h
Log Message:
-----------
Merge tag 'imp-202210-pull-request' of
https://github.com/qemu-bsd-user/qemu-bsd-user into staging
bsd-user: 7.2 misc fixes
Light quarter: only one fix due to header file shuffling in FreeBSD
# -----BEGIN PGP SIGNATURE-----
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# gpg: Signature made Fri 28 Oct 2022 13:44:32 EDT
# gpg: using RSA key 2035F894B00AA3CF7CCDE1B76C1CD1287DB01100
# gpg: Good signature from "Warner Losh <wlosh@netflix.com>" [unknown]
# gpg: aka "Warner Losh <imp@bsdimp.com>" [unknown]
# gpg: aka "Warner Losh <imp@freebsd.org>" [unknown]
# gpg: aka "Warner Losh <imp@village.org>" [unknown]
# gpg: aka "Warner Losh <wlosh@bsdimp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 2035 F894 B00A A3CF 7CCD E1B7 6C1C D128 7DB0 1100
* tag 'imp-202210-pull-request' of
https://github.com/qemu-bsd-user/qemu-bsd-user:
bsd-user: Catch up with sys/param.h requirement for machine/pmap.h
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 8e4022a8d6934d02c0d95058a6e9b0e0f93f36b2
https://github.com/qemu/qemu/commit/8e4022a8d6934d02c0d95058a6e9b0e0f93f36b2
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
hw/isa/vt82c686: Resolve chip-specific realize methods
The object creation now happens in chip-specific init methods which
allows the realize methods to be consolidated into one method. Shifting
the logic into the init methods has the addidional advantage that the
parent object's init methods are called implicitly - like constructors
in object-oriented languages.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220901114127.53914-2-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 91ba92d1a33e5a9ded66bfbaa14a98938165934f
https://github.com/qemu/qemu/commit/91ba92d1a33e5a9ded66bfbaa14a98938165934f
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
hw/isa/vt82c686: Resolve unneeded attribute
Now that also the super io device is realized in the common realize method,
the isa_bus attribute can be turned into a temporary.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220901114127.53914-3-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: dd28cc87aa0295743b577145a8afc76cc9292618
https://github.com/qemu/qemu/commit/dd28cc87aa0295743b577145a8afc76cc9292618
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
hw/isa/vt82c686: Prefer pci_address_space() over get_system_memory()
Unlike get_system_memory(), pci_address_space() respects the memory tree
available to the parent device.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220901114127.53914-4-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: c1561d1deba5a58c49b57afb72785e70ccb08dc9
https://github.com/qemu/qemu/commit/c1561d1deba5a58c49b57afb72785e70ccb08dc9
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
hw/isa/vt82c686: Reuse errp
Rather than terminating abruptly, make use of the already present errp and
propagate the error to the caller.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220901114127.53914-5-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 4b8fd0661a6c57f6a94b55e462626d522fa9c5cc
https://github.com/qemu/qemu/commit/4b8fd0661a6c57f6a94b55e462626d522fa9c5cc
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/ide/via.c
M hw/mips/fuloong2e.c
M hw/ppc/pegasos2.c
M include/hw/isa/vt82c686.h
Log Message:
-----------
hw/isa/vt82c686: Introduce TYPE_VIA_IDE define
Establishes consistency with other (VIA) devices.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220901114127.53914-6-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 9eb6abbf6aea3116b3a4a7a6fbbb89ec836c0551
https://github.com/qemu/qemu/commit/9eb6abbf6aea3116b3a4a7a6fbbb89ec836c0551
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M configs/devices/mips64el-softmmu/default.mak
M hw/isa/Kconfig
M hw/isa/vt82c686.c
M hw/mips/fuloong2e.c
M hw/ppc/Kconfig
M hw/ppc/pegasos2.c
Log Message:
-----------
hw/isa/vt82c686: Instantiate IDE function in host device
The IDE function is closely tied to the ISA function (e.g. the IDE
interrupt routing happens there), so it makes sense that the IDE
function is instantiated within the south bridge itself.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220901114127.53914-7-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 65c69e9a9f05ac407ebb2df48b5261f3da21afc9
https://github.com/qemu/qemu/commit/65c69e9a9f05ac407ebb2df48b5261f3da21afc9
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/mips/fuloong2e.c
M hw/ppc/pegasos2.c
M hw/usb/vt82c686-uhci-pci.c
M include/hw/isa/vt82c686.h
Log Message:
-----------
hw/isa/vt82c686: Introduce TYPE_VT82C686B_USB_UHCI define
Suggested-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220901114127.53914-8-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 1a99ddbe3529bc1b683ef77a1fe29bbb13bf244d
https://github.com/qemu/qemu/commit/1a99ddbe3529bc1b683ef77a1fe29bbb13bf244d
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/isa/vt82c686.c
M hw/mips/fuloong2e.c
M hw/ppc/pegasos2.c
Log Message:
-----------
hw/isa/vt82c686: Instantiate USB functions in host device
The USB functions can be enabled/disabled through the ISA function. Also
its interrupt routing can be influenced there.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220901114127.53914-9-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: d105377264a87573ba4207d05c1641bb3708710a
https://github.com/qemu/qemu/commit/d105377264a87573ba4207d05c1641bb3708710a
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/isa/vt82c686.c
M hw/mips/fuloong2e.c
M hw/ppc/pegasos2.c
M include/hw/isa/vt82c686.h
Log Message:
-----------
hw/isa/vt82c686: Instantiate PM function in host device
The PM controller has activity bits which monitor activity of other
built-in devices in the host device.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220901114127.53914-10-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 0a8d405d69394f84a28cde79949612ec36d3fcda
https://github.com/qemu/qemu/commit/0a8d405d69394f84a28cde79949612ec36d3fcda
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/isa/vt82c686.c
M hw/mips/fuloong2e.c
M hw/ppc/pegasos2.c
Log Message:
-----------
hw/isa/vt82c686: Instantiate AC97 and MC97 functions in host device
The AC97 function's wakeup status is wired to the PM function and both
the AC97 and MC97 interrupt routing is determined by the ISA function.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220901114127.53914-11-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 4ff5328bf7d503805cc1baba9e4de47216f407d0
https://github.com/qemu/qemu/commit/4ff5328bf7d503805cc1baba9e4de47216f407d0
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/mips/fuloong2e.c
Log Message:
-----------
hw/mips/fuloong2e: Inline vt82c686b_southbridge_init() and remove it
The previous patches moved most of this function into the via-isa device
model such that it has become fairly trivial. So inline it for
simplicity.
Suggested-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220901114127.53914-12-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 3ecb2e62f98b876d5134429f84437e6f6956d212
https://github.com/qemu/qemu/commit/3ecb2e62f98b876d5134429f84437e6f6956d212
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
hw/isa/vt82c686: Embed RTCState in host device
Embed the rtc in the host device, analoguous to the other child devices
and analoguous to PIIX4.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220901114127.53914-13-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: ff9105dabc5edeab8328e0b639a21c7ef555161e
https://github.com/qemu/qemu/commit/ff9105dabc5edeab8328e0b639a21c7ef555161e
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/isa/vt82c686.c
M hw/mips/fuloong2e.c
M hw/ppc/pegasos2.c
Log Message:
-----------
hw/isa/vt82c686: Create rtc-time alias in boards instead
According to good QOM practice, an object should only deal with objects
of its own sub tree. Having devices create an alias on the machine
object doesn't respect this good practice. To resolve this, create the
alias in the machine's code.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220901114127.53914-14-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 8466405eb0c77d81be5f8c2e3608fdfeb00bb1b9
https://github.com/qemu/qemu/commit/8466405eb0c77d81be5f8c2e3608fdfeb00bb1b9
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/alpha/dp264.c
M hw/hppa/machine.c
M hw/mips/fuloong2e.c
M hw/mips/malta.c
M hw/ppc/prep.c
M hw/sparc64/sun4u.c
Log Message:
-----------
hw: Remove unused MAX_IDE_BUS define
Several machines have an unused MAX_IDE_BUS define. Remove it from
these machines that don't need it.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220917115136.A32EF746E06@zero.eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: c52316925c4e3bf6aef1b12e6cfec5ba53e4ff28
https://github.com/qemu/qemu/commit/c52316925c4e3bf6aef1b12e6cfec5ba53e4ff28
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
M disas/nanomips.h
Log Message:
-----------
disas/nanomips: Remove namespace img
Since there's no namespace feature in C, namespace img has been replaced
with adding the prefix "img" to the namespace members.
Prefix "img" has been added to the function names of functions that used
to be wrapped in namespace img. Those are img::format() functions.
I.e. replaced img::format with the img_format.
Typedef address that used to belong to namespace img now is called
img_address.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-2-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: bfffba15b24582a78f956d17f155c2f18aaf001c
https://github.com/qemu/qemu/commit/bfffba15b24582a78f956d17f155c2f18aaf001c
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
M disas/nanomips.h
Log Message:
-----------
disas/nanomips: Extract enums out of the NMD class
Definitions of enums TABLE_ENTRY_TYPE and TABLE_ATTRIBUTE_TYPE are moved
out of the NMD class. The main goal is to remove NMD class completely.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-3-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 0c2a3b43a1d818b31e2fce81db2085ffeb9a4400
https://github.com/qemu/qemu/commit/0c2a3b43a1d818b31e2fce81db2085ffeb9a4400
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
M disas/nanomips.h
Log Message:
-----------
disas/nanomips: Delete NMD class field
The m_requested_instruction_categories field always has the same value,
ALL_ATTRIBUTES. The only use of that field is within the if statement.
When replaced with a specific value, the if statement is always false,
so it has been removed.
Now, when the only use of the m_requested_instruction_categories field
is removed, we can delete the field declaration and initialization in
the NMD class. Also, we're changing the way of the construction of the
NMD object in the nanomips_dis function.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-4-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 9972c8fa7c5126311417b1d3cf355d28a6955d3d
https://github.com/qemu/qemu/commit/9972c8fa7c5126311417b1d3cf355d28a6955d3d
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
M disas/nanomips.h
Log Message:
-----------
disas/nanomips: Delete NMD class second field
We're deleting the m_pc field of the NMD class. It's now part of the
Dis_info struct that this patch introduces. Currently, the Dis_info
struct has just one field, m_pc, which we need for address calculation
in the ADDRESS function.
We're filling Dis_info at the entrance of the nanoMIPS disassembler.
I.e. print_insn_nanomips. Next, we're adding that information as an
argument wherever we need to.
Since NMD class now has no more fields, the NMD constructor is
also deleted.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-5-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 2dc0c175df28cd9c9a5eeb12880219cb0f426951
https://github.com/qemu/qemu/commit/2dc0c175df28cd9c9a5eeb12880219cb0f426951
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
M disas/nanomips.h
Log Message:
-----------
disas/nanomips: Remove helper methods from class
Helper methods from NMD class like NMD::renumber_registers,
NMD::decode_gpr_gpr4... etc. are removed from the class. They're now
declared global static functions.
Following helper methods have been deleted because they're not used by
the nanomips disassembler:
- NMD::encode_msbd_from_pos_and_size,
- NMD::encode_s_from_s_hi,
- NMD::neg_copy
Global functions used by those methods:
- nanomips_dis
- sign_extend
- extract_bits
have also been defined as static global functions.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-6-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 655fc22f1bc7a16d9da6bd44c43e763bc27d0b8a
https://github.com/qemu/qemu/commit/655fc22f1bc7a16d9da6bd44c43e763bc27d0b8a
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
M disas/nanomips.h
Log Message:
-----------
disas/nanomips: Remove __cond methods from class
NMD class methods with the conditional_function type like
NMD::ADDIU_32__cond, NMD::ADDIU_RS5__cond, etc. are removed from the NMD
class. They're now declared global static functions. Therefore, typedef
of the function pointer, conditional_function is defined outside of the
class.
Now that conditional_function type functions are not part of the NMD
class we can't access them using the this pointer. Thus, the use of
the this pointer has been deleted.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-7-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 8d416f6b455d0c73667a2ffa9a0782aa07627d81
https://github.com/qemu/qemu/commit/8d416f6b455d0c73667a2ffa9a0782aa07627d81
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
M disas/nanomips.h
Log Message:
-----------
disas/nanomips: Remove disasm methods from class
NMD class methods with the disassembly_function type like
NMD::ABS_D, NMD::ABS_S, etc. are removed from the class. They're now
declared global static functions. Therefore, typedef of the function
pointer, disassembly_function is defined outside of the class.
Now that disassembly_function type functions are not part of the NMD
class we can't access them using the this pointer. Thus, the use of
the this pointer has been deleted.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-8-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: a146549034a67234d7b8c5aa66cc2552989c630a
https://github.com/qemu/qemu/commit/a146549034a67234d7b8c5aa66cc2552989c630a
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
M disas/nanomips.h
Log Message:
-----------
disas/nanomips: Remove Pool tables from the class
Pool tables are no longer declared as static fields of the NMD
class but as global static const variables. Pool struct is defined
outside of the class.
The NMD::Disassemble method is using the MAJOR Pool table variable, so
its implementation is moved to the end of the nanomips.cpp file,
right after the initialization of the MAJOR Pool table.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-9-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: beebf65bec528bcd73f704b2c93ac9c9494431c1
https://github.com/qemu/qemu/commit/beebf65bec528bcd73f704b2c93ac9c9494431c1
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
M disas/nanomips.h
Log Message:
-----------
disas/nanomips: Remove NMD class
NMD class has been deleted. The following methods are now declared as
static functions:
- public NMD::Disassemble method
- private NMD::Disassemble method
- private NMD::extract_op_code_value helper method
Also, the implementation of the print_insn_nanomips function and
nanomips_dis function is moved to the end of the nanomips.cpp file,
right after the implementation of the Disassemble function.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-10-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: f1cb3bdbc77aa719a3ea7434e3e89dd64d95508f
https://github.com/qemu/qemu/commit/f1cb3bdbc77aa719a3ea7434e3e89dd64d95508f
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
M disas/nanomips.h
Log Message:
-----------
disas/nanomips: Move typedefs etc to nanomips.cpp
The following is moved from the nanomips.h to nanomips.cpp file:
- #include line
- typedefs
- enums
- definition of the Pool struct.
Header file nanomips.h will be deleted to be consistent with the rest of
the disas/ code.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-11-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 1a1cc52a88eed130cc99f4912844cddb14a0c8af
https://github.com/qemu/qemu/commit/1a1cc52a88eed130cc99f4912844cddb14a0c8af
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
R disas/nanomips.h
Log Message:
-----------
disas/nanomips: Delete nanomips.h
Header file nanomips.h has been deleted for the nanomips disassembler to
stay consistent with the rest of the disassemblers which don't include
extra header files.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-12-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 912c95b4fae34a8fc62d383bd3f757ceda8cd20f
https://github.com/qemu/qemu/commit/912c95b4fae34a8fc62d383bd3f757ceda8cd20f
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
Log Message:
-----------
disas/nanomips: Remove #include <sstream>
<sstream> is a C++ library and it's not used by disassembler.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-13-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: b5cc052894b809cb0e6e7e70b389264b59e06072
https://github.com/qemu/qemu/commit/b5cc052894b809cb0e6e7e70b389264b59e06072
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
Log Message:
-----------
disas/nanomips: Delete copy functions
Functions that have just one parameter and simply return it have been
deleted. Calls to these functions have been replaced with the argument
itself.
We're deleting following functions:
- both versions of copy()
- encode_s_from_address()
- encode_u_from_address()
- encode_lsb_from_pos_and_size()
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-14-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: afc47e07e57e9f39a9dfdf240d67b65a284b15d8
https://github.com/qemu/qemu/commit/afc47e07e57e9f39a9dfdf240d67b65a284b15d8
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
Log Message:
-----------
disas/nanomips: Delete wrapper functions
Following functions just wrap the decode_gpr_gpr3() function:
- encode_rs3_and_check_rs3_ge_rt3()
- encode_rs3_and_check_rs3_lt_rt3()
Therefore those have been deleted. Calls to these two functions have
been replaced with calls to decode_gpr_gpr3.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-15-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 7def8a4b937262c2710d2cd5fdb21e7af4b0529a
https://github.com/qemu/qemu/commit/7def8a4b937262c2710d2cd5fdb21e7af4b0529a
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
Log Message:
-----------
disas/nanomips: Replace std::string type
The return type of typedef disassembly_function is changed to char *
instead of std::string. Therefore, for every particular
disassembly_function function signature is changed.
For example:
- static std::string ABS_D(uint64 instruction, img_address m_pc) {...}
is replaced with
- static char *ABS_D(uint64 instruction, img_address m_pc) {...}
Every helper function used to return std::string is changed to return
const char * or char *. Where the return value points to a static string
that the caller must not free, the return type is const char *. If a
function allocates memory and the caller is required to free it, the
return type is a char *. This applies to the following functions:
img_format, to_string, GPR, save_restore_list, FPR, etc.
Now that we replaced every std::string for const char * or char *, it is
possible to delete multiple versions of the img_format function. The
general version:
- static char *img_format(const char *format, ...) {...}
can handle all string formatting, so others have been deleted.
Where necessary, strings are dynamically allocated with g_strjoinv,
g_strdup, g_strdup_vprintf, and g_strdup_printf. Memory leaking will be
prevented later.
String concatenation in the save_restore_list() function is handled
using g_strjoinv() function instead of += operator.
The type of the "dis" parameter in the Disassemble function is changed
- from std::string &
- to char **
Without applying all of these changes, the nanomips disassembler may be
buildable but can't produce the appropriate output, so all of them are
made together.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-16-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 4066c152b322fad4c89872a30e6febc70a43bf73
https://github.com/qemu/qemu/commit/4066c152b322fad4c89872a30e6febc70a43bf73
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
Log Message:
-----------
disas/nanomips: Remove IMMEDIATE functions
Both versions of IMMEDIATE functions have been removed.
Before this patch, we'd been calling img_format twice, the first time
through the IMMEDIATE to get an appropriate string and the second time
to print that string. There's no more need for that. Therefore, calls to
IMMEDIATE are removed, and now we're directly printing the integer
values instead.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-17-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 043dc73cbc6e9c24c061966cd40fa3c9a702b004
https://github.com/qemu/qemu/commit/043dc73cbc6e9c24c061966cd40fa3c9a702b004
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
Log Message:
-----------
disas/nanomips: Remove CPR function
CPR functions has been removed.
Before this patch, we'd been calling img_format twice, the first time
through the CPR function to get an appropriate string and the second
time to print that formatted string. There's no more need for that.
Therefore, calls to CPR are removed, and now we're directly printing
"CP" and integer value instead.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-18-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 22e7b52acd8ffd10478167652b291db11c9c047d
https://github.com/qemu/qemu/commit/22e7b52acd8ffd10478167652b291db11c9c047d
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
Log Message:
-----------
disas/nanomips: Prevent memory leaking
g_autofree attribute is added for every dynamically allocated string to
prevent memory leaking.
The implementation of the several functions that work with dynamically
allocated strings is slightly changed so we can add those attributes.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-19-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 49ec1c98a3992952836a08b797902b9d49ae4b9d
https://github.com/qemu/qemu/commit/49ec1c98a3992952836a08b797902b9d49ae4b9d
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
Log Message:
-----------
disas/nanomips: Remove function overloading
Disassemble function that calls the other variant of it is deleted.
Where it is called, now we're directly calling the other implementation.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-20-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 3f2aec0778853afe190114bc6f1d18ab0239da09
https://github.com/qemu/qemu/commit/3f2aec0778853afe190114bc6f1d18ab0239da09
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
Log Message:
-----------
disas/nanomips: Expand Dis_info struct
This patch expands the Dis_info struct, which should hold the
necessary data for handling runtime errors. Fields fprintf_func and
stream are in charge of error printing. Field buf enables the use of
sigsetjmp() and siglongjmp() functions. Support for runtime error
handling will be added later.
We're filling Dis_info at the entrance of the nanoMIPS disassembler,
i.e. print_insn_nanomips. Next, we're adding that information as an
argument wherever we need to.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-21-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 39399c381d3bfc8f651f6d64f9f1f37d9763a8e3
https://github.com/qemu/qemu/commit/39399c381d3bfc8f651f6d64f9f1f37d9763a8e3
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
Log Message:
-----------
disas/nanomips: Replace exception handling
Since there's no support for exception handling in C, the try-catch
blocks have been deleted, and throw clauses are replaced. When a runtime
error happens, we're printing out the error message. Disassembling of
the current instruction interrupts. This behavior is achieved by adding
sigsetjmp() to discard further disassembling after the error message
prints and by adding the siglongjmp() function to imitate throwing an
error. The goal was to maintain the same output as it was.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-22-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: e8ba8ef873222178e238618d6d4b65b82cf47f41
https://github.com/qemu/qemu/commit/e8ba8ef873222178e238618d6d4b65b82cf47f41
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
Log Message:
-----------
disas/nanomips: Replace Cpp enums for C enums
Change enums to typedef enums to keep naming clear.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-23-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: a0fee129445af73c1de7b56472dff14113bc4dc7
https://github.com/qemu/qemu/commit/a0fee129445af73c1de7b56472dff14113bc4dc7
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/nanomips.cpp
Log Message:
-----------
disas/nanomips: Remove argument passing by ref
Replaced argument passing by reference with passing by address.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-24-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 2413e000bb6efd47fda78ae1dfebd946323e3d9d
https://github.com/qemu/qemu/commit/2413e000bb6efd47fda78ae1dfebd946323e3d9d
Author: Milica Lazarevic <milica.lazarevic@syrmia.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/meson.build
A disas/nanomips.c
R disas/nanomips.cpp
Log Message:
-----------
disas/nanomips: Rename nanomips.cpp to nanomips.c
Now that everything has been converted to C code the nanomips.cpp file
has been renamed. Therefore, meson.build file is also changed.
Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220912122635.74032-25-milica.lazarevic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: a6d89b454cec2de235595ea311d3cc3c49c3aaaa
https://github.com/qemu/qemu/commit/a6d89b454cec2de235595ea311d3cc3c49c3aaaa
Author: David Daney <david.daney@fungible.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M disas/mips.c
Log Message:
-----------
disas/mips: Fix branch displacement for BEQZC and BNEZC
disas/mips.c got added in commit 6643d27ea0 ("MIPS disas support")
apparently based on binutils tag 'gdb_6_1-branchpoint' [1].
Back then, MIPSr6 was not supported (added in binutils commit
7361da2c952 during 2014 [2]).
Binutils codebase diverged so much over the last 18 years, it is
not possible to simply cherry-pick their changes, so fix it BEQZC /
BNEZC 21-bit signed branch displacement locally.
[1]
https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=opcodes/mips-dis.c;hb=refs/tags/gdb_6_1-branchpoint
[2] https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=7361da2c952
Fixes: 31837be3ee ("target-mips: add compact and CP1 branches")
Signed-off-by: David Daney <david.daney@fungible.com>
Reviewed-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
[PMD: Added commit description]
Signed-off-by: Philippe Mathieu-Daudé <philmd@fungible.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221014112322.61119-1-philmd@fungible.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 503a35e7fdb75aef73d25c43589afcdff6d03ccf
https://github.com/qemu/qemu/commit/503a35e7fdb75aef73d25c43589afcdff6d03ccf
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/isa/Kconfig
M hw/isa/lpc_ich9.c
M hw/isa/piix3.c
Log Message:
-----------
hw/i386/pc: Create DMA controllers in south bridges
Just like in the real hardware (and in PIIX4), create the DMA
controllers in the south bridges.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221022150508.26830-2-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 05c049f12b88370de7289bf39b14088c7d656caa
https://github.com/qemu/qemu/commit/05c049f12b88370de7289bf39b14088c7d656caa
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/isa/piix3.c
Log Message:
-----------
hw/isa/piix3: Remove extra ';' outside of functions
Fixes the "extra-semi" clang-tidy check.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221022150508.26830-4-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 3ee15e807407defcd774586549a00674d58be970
https://github.com/qemu/qemu/commit/3ee15e807407defcd774586549a00674d58be970
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/isa/piix3.c
Log Message:
-----------
hw/isa/piix3: Add size constraints to rcr_ops
According to the PIIX3 datasheet, the reset control register is one byte in
size.
Moreover, PIIX4 has it, so add it to PIIX3 as well.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221022150508.26830-5-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: a1b05751faf7769cec3b1751da0239d2ced27b35
https://github.com/qemu/qemu/commit/a1b05751faf7769cec3b1751da0239d2ced27b35
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/isa/piix3.c
Log Message:
-----------
hw/isa/piix3: Modernize reset handling
Rather than registering the reset handler via a function which
appends the handler to a global list, prefer to implement it as
a virtual method - PIIX4 does the same already.
Note that this means that piix3_reset can now also be called writing to
the relevant configuration space register on a PCI bridge.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221022150508.26830-6-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 57654b8e98785f2188b64dd45489dc29b426663c
https://github.com/qemu/qemu/commit/57654b8e98785f2188b64dd45489dc29b426663c
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/isa/piix3.c
Log Message:
-----------
hw/isa/piix3: Prefer pci_address_space() over get_system_memory()
get_system_memory() accesses global state while pci_address_space() uses
whatever has been passed to the device instance, so avoid the global.
Moreover, PIIX4 uses pci_address_space() here as well.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221022150508.26830-7-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 0b6fdb933b04637a240bd132d626d1daf2d8d7a7
https://github.com/qemu/qemu/commit/0b6fdb933b04637a240bd132d626d1daf2d8d7a7
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/isa/piix4.c
Log Message:
-----------
hw/isa/piix4: Rename wrongly named method
This method post-loads the southbridge, not the IDE device.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221022150508.26830-8-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: bb2e9b1d660a4bf11c169388b577c851c51ffe24
https://github.com/qemu/qemu/commit/bb2e9b1d660a4bf11c169388b577c851c51ffe24
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/i386/pc_piix.c
M hw/ide/piix.c
M hw/isa/piix4.c
A include/hw/ide/piix.h
Log Message:
-----------
hw/ide/piix: Introduce TYPE_ macros for PIIX IDE controllers
Suggested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221022150508.26830-9-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 90ba5c511a7ed0c4e849bc556326c32df9876ee8
https://github.com/qemu/qemu/commit/90ba5c511a7ed0c4e849bc556326c32df9876ee8
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/isa/piix3.c
Log Message:
-----------
hw/isa/piix3: Remove unused include
Ammends commit 988fb613215993dd0ce642b89ca8182c479d39dd.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221022150508.26830-19-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: e5b6c3e2fe0564306c71ec322717101aa88835c7
https://github.com/qemu/qemu/commit/e5b6c3e2fe0564306c71ec322717101aa88835c7
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Reuse dev variable
While at it, move the assignments closer to where they are used.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221022150508.26830-26-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 195f7e77de374b6b9776be3bbbc71c7a11ae5622
https://github.com/qemu/qemu/commit/195f7e77de374b6b9776be3bbbc71c7a11ae5622
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M configs/devices/mips-softmmu/common.mak
M hw/isa/Kconfig
Log Message:
-----------
hw/isa/Kconfig: Fix dependencies of piix4 southbridge
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20221022150508.26830-27-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: a1c100d0fbdcee230341262c3874513ce70ff38f
https://github.com/qemu/qemu/commit/a1c100d0fbdcee230341262c3874513ce70ff38f
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/isa/piix4.c
Log Message:
-----------
hw/isa/piix4: Add missing initialization
PIIX3 clears its reset control register, so do the same in PIIX4.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20221022150508.26830-28-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: d240d3fb14031ed2b00b86ab8e9082ba6bebce4d
https://github.com/qemu/qemu/commit/d240d3fb14031ed2b00b86ab8e9082ba6bebce4d
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/isa/piix4.c
M hw/mips/malta.c
Log Message:
-----------
hw/isa/piix4: Move pci_ide_create_devs() call to board code
For the VIA south bridges there was a comment to have the call in board code.
Move it there for PIIX4 as well for consistency.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221022150508.26830-29-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 3c43fc333be7747a29405bdf6b3bd9e82fa22164
https://github.com/qemu/qemu/commit/3c43fc333be7747a29405bdf6b3bd9e82fa22164
Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/mips/boston.c
Log Message:
-----------
hw/mips/boston: Don't set link_up for xilinx-pcie
PCIe port 0 and 1 had link_up set as false previously,
that makes those two ports effectively useless. It can
be annoying for users to find that the device they plug
on those buses won't work at all.
As link_up is true by default, just don't set it again in
boston platform code.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20221024143540.97545-1-jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 36d7487b2aa033e9792fb310c39d106ffcadaa4f
https://github.com/qemu/qemu/commit/36d7487b2aa033e9792fb310c39d106ffcadaa4f
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/mips/bootloader.c
M hw/mips/boston.c
M hw/mips/fuloong2e.c
M include/hw/mips/bootloader.h
Log Message:
-----------
hw/mips/bootloader: Allow bl_gen_jump_kernel to optionally set register
When one of the $sp/$a[0..3] register is already set, we might
want bl_gen_jump_kernel() to NOT set it again. Pass a boolean
argument for each register, to allow to optionally set them.
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221026191821.28167-2-philmd@linaro.org>
Commit: fe1f2f4e92782b00ed7edb355c227a2073cfa45b
https://github.com/qemu/qemu/commit/fe1f2f4e92782b00ed7edb355c227a2073cfa45b
Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips: Use bl_gen_kernel_jump to generate bootloaders
Replace embedded binary with generated code.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210127065424.114125-3-jiaxun.yang@flygoat.com>
[PMD: Pass semihosting_get_argc() to bl_gen_jump_kernel()]
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221026191821.28167-3-philmd@linaro.org>
Commit: 0c8427baf0f66bdaecae41891304f6e15242e682
https://github.com/qemu/qemu/commit/0c8427baf0f66bdaecae41891304f6e15242e682
Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Use bootloader helper to set BAR registers
Translate embedded assembly into IO writes which is more
readable.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210127065424.114125-4-jiaxun.yang@flygoat.com>
[PMD: Explode addresses/values to ease review/maintainance]
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221026191821.28167-4-philmd@linaro.org>
Commit: 95539e546759e9cdd87ae6c8f9b314d881789435
https://github.com/qemu/qemu/commit/95539e546759e9cdd87ae6c8f9b314d881789435
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M configs/devices/mips-softmmu/common.mak
M configs/devices/mips64el-softmmu/default.mak
M disas/meson.build
M disas/mips.c
A disas/nanomips.c
R disas/nanomips.cpp
R disas/nanomips.h
M hw/alpha/dp264.c
M hw/hppa/machine.c
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/ide/piix.c
M hw/ide/via.c
M hw/isa/Kconfig
M hw/isa/lpc_ich9.c
M hw/isa/piix3.c
M hw/isa/piix4.c
M hw/isa/vt82c686.c
M hw/mips/bootloader.c
M hw/mips/boston.c
M hw/mips/fuloong2e.c
M hw/mips/malta.c
M hw/ppc/Kconfig
M hw/ppc/pegasos2.c
M hw/ppc/prep.c
M hw/sparc64/sun4u.c
M hw/usb/vt82c686-uhci-pci.c
A include/hw/ide/piix.h
M include/hw/isa/vt82c686.h
M include/hw/mips/bootloader.h
Log Message:
-----------
Merge tag 'mips-20221030' of https://github.com/philmd/qemu into staging
MIPS patches queue
- Convert nanoMIPS disassembler from C++ to C (Milica Lazarevic)
- Consolidate VT82xx/PIIX south bridges (Bernhard Beschow)
- Remove unused MAX_IDE_BUS definition (Zoltan Balaton)
- Fix branch displacement for BEQZC/BNEZC (David Daney)
- Don't set link_up for Boston's xilinx-pcie (Jiaxun Yang)
- Use bootloader API to set BAR registers in Malta (Jiaxun Yang)
# -----BEGIN PGP SIGNATURE-----
#
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# gpg: Signature made Mon 31 Oct 2022 06:35:27 EDT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'mips-20221030' of https://github.com/philmd/qemu: (55 commits)
hw/mips/malta: Use bootloader helper to set BAR registers
hw/mips: Use bl_gen_kernel_jump to generate bootloaders
hw/mips/bootloader: Allow bl_gen_jump_kernel to optionally set register
hw/mips/boston: Don't set link_up for xilinx-pcie
hw/isa/piix4: Move pci_ide_create_devs() call to board code
hw/isa/piix4: Add missing initialization
hw/isa/Kconfig: Fix dependencies of piix4 southbridge
hw/mips/malta: Reuse dev variable
hw/isa/piix3: Remove unused include
hw/ide/piix: Introduce TYPE_ macros for PIIX IDE controllers
hw/isa/piix4: Rename wrongly named method
hw/isa/piix3: Prefer pci_address_space() over get_system_memory()
hw/isa/piix3: Modernize reset handling
hw/isa/piix3: Add size constraints to rcr_ops
hw/isa/piix3: Remove extra ';' outside of functions
hw/i386/pc: Create DMA controllers in south bridges
disas/mips: Fix branch displacement for BEQZC and BNEZC
disas/nanomips: Rename nanomips.cpp to nanomips.c
disas/nanomips: Remove argument passing by ref
disas/nanomips: Replace Cpp enums for C enums
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 0c7a8c0150d660de055b14db2b495d6c7c8a5f01
https://github.com/qemu/qemu/commit/0c7a8c0150d660de055b14db2b495d6c7c8a5f01
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M MAINTAINERS
M accel/tcg/cpu-exec-common.c
M accel/tcg/internal.h
M accel/tcg/tb-maint.c
M accel/tcg/translate-all.c
M include/exec/exec-all.h
M meson.build
M target/alpha/helper.c
M target/alpha/mem_helper.c
M target/arm/op_helper.c
M target/arm/tlb_helper.c
M target/cris/helper.c
M target/i386/helper.c
M target/i386/helper.h
M target/i386/tcg/cc_helper.c
M target/i386/tcg/sysemu/svm_helper.c
M target/i386/tcg/translate.c
M target/m68k/op_helper.c
M target/microblaze/helper.c
M target/nios2/op_helper.c
M target/openrisc/sys_helper.c
M target/ppc/excp_helper.c
M target/s390x/tcg/excp_helper.c
M target/tricore/op_helper.c
M target/xtensa/helper.c
R tcg/sparc/tcg-target-con-set.h
R tcg/sparc/tcg-target-con-str.h
R tcg/sparc/tcg-target.c.inc
R tcg/sparc/tcg-target.h
A tcg/sparc64/tcg-target-con-set.h
A tcg/sparc64/tcg-target-con-str.h
A tcg/sparc64/tcg-target.c.inc
A tcg/sparc64/tcg-target.h
M tcg/tcg.c
Log Message:
-----------
Merge tag 'pull-tcg-20221031' of https://gitlab.com/rth7680/qemu into staging
Remove sparc32plus support from tcg/sparc.
target/i386: Use cpu_unwind_state_data for tpr access.
target/i386: Expand eflags updates inline
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# -----END PGP SIGNATURE-----
# gpg: Signature made Sun 30 Oct 2022 20:43:18 EDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20221031' of https://gitlab.com/rth7680/qemu:
target/i386: Expand eflags updates inline
accel/tcg: Remove reset_icount argument from cpu_restore_state_from_tb
accel/tcg: Remove will_exit argument from cpu_restore_state
target/openrisc: Use cpu_unwind_state_data for mfspr
target/openrisc: Always exit after mtspr npc
target/i386: Use cpu_unwind_state_data for tpr access
accel/tcg: Introduce cpu_unwind_state_data
tcg/tci: fix logic error when registering helpers via FFI
tcg/sparc64: Remove sparc32plus constraints
tcg/sparc64: Rename from tcg/sparc
tcg/sparc: Remove support for sparc32plus
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 13c29a3f39fa293e6927db80ddb209b9693ed1ab
https://github.com/qemu/qemu/commit/13c29a3f39fa293e6927db80ddb209b9693ed1ab
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-10-31 (Mon, 31 Oct 2022)
Changed paths:
M meson.build
M scripts/nsis.py
Log Message:
-----------
Merge tag 'pull-qemu-20221031' of https://gitlab.com/stweil/qemu into staging
Patches for Windows
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# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 31 Oct 2022 05:06:53 EDT
# gpg: using RSA key 49236FEA75C95D698EC2B78AE08C21D5677450AD
# gpg: Good signature from "Stefan Weil <sw@weilnetz.de>" [unknown]
# gpg: aka "Stefan Weil (Universitätsbibliothek Mannheim)
<stefan.weil@uni-mannheim.de>" [unknown]
# gpg: aka "Stefan Weil <stefan.weil@bib.uni-mannheim.de>"
[unknown]
# gpg: aka "Stefan Weil <stefan.weil@weilnetz.de>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4923 6FEA 75C9 5D69 8EC2 B78A E08C 21D5 6774 50AD
* tag 'pull-qemu-20221031' of https://gitlab.com/stweil/qemu:
block/nfs: Fix 32-bit Windows build
scripts/nsis.py: Automatically package required DLLs of QEMU executables
scripts/nsis.py: Fix destination directory name when invoked on Windows
scripts/nsis.py: Drop the unnecessary path separator
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/720842922396...13c29a3f39fa
- [Qemu-commits] [qemu/qemu] 41bf93: bsd-user: Catch up with sys/param.h requirement fo...,
Paolo Bonzini <=