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[Qemu-commits] [qemu/qemu] 3648d3: hw/i2c/aspeed: Fix old reg slave rece
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From: |
Paolo Bonzini |
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Subject: |
[Qemu-commits] [qemu/qemu] 3648d3: hw/i2c/aspeed: Fix old reg slave receive |
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Date: |
Wed, 26 Oct 2022 07:06:05 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 3648d31fa81c4a391b8cd74e9fcd410a74f72383
https://github.com/qemu/qemu/commit/3648d31fa81c4a391b8cd74e9fcd410a74f72383
Author: Peter Delevoryas <peter@pjd.dev>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M hw/i2c/aspeed_i2c.c
M include/hw/i2c/aspeed_i2c.h
Log Message:
-----------
hw/i2c/aspeed: Fix old reg slave receive
I think when Klaus ported his slave mode changes from the original patch
series to the rewritten I2C module, he changed the behavior of the first
byte that is received by the slave device.
What's supposed to happen is that the AspeedI2CBus's slave device's
i2c_event callback should run, and if the event is "send_async", then it
should populate the byte buffer with the 8-bit I2C address that is being
sent to. Since we only support "send_async", the lowest bit should
always be 0 (indicating that the master is requesting to send data).
This is the code Klaus had previously, for reference. [1]
switch (event) {
case I2C_START_SEND:
bus->buf = bus->dev_addr << 1;
bus->buf &= I2CD_BYTE_BUF_RX_MASK;
bus->buf <<= I2CD_BYTE_BUF_RX_SHIFT;
bus->intr_status |= (I2CD_INTR_SLAVE_ADDR_RX_MATCH | I2CD_INTR_RX_DONE);
aspeed_i2c_set_state(bus, I2CD_STXD);
break;
[1]:
https://lore.kernel.org/qemu-devel/20220331165737.1073520-4-its@irrelevant.dk/
Fixes: a8d48f59cd021b25 ("hw/i2c/aspeed: add slave device in old register mode")
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Message-Id: <20220820225712.713209-2-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 7b5093b85b74158efda30798ffff6da973a353c4
https://github.com/qemu/qemu/commit/7b5093b85b74158efda30798ffff6da973a353c4
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M tests/avocado/machine_aspeed.py
Log Message:
-----------
tests/avocado/machine_aspeed.py: Fix typos on buildroot
Replace 'buidroot' and 'builroot' by 'buildroot'.
Fixes: f7bc7da0724f ("test/avocado/machine_aspeed.py: Add tests using buildroot
images")
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20220923084803.498337-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: db96605a49b334eeb2a5d1cc12981778f7d792aa
https://github.com/qemu/qemu/commit/db96605a49b334eeb2a5d1cc12981778f7d792aa
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M hw/ssi/ssi.c
M include/hw/ssi/ssi.h
Log Message:
-----------
ssi: cache SSIPeripheralClass to avoid GET_CLASS()
Investigating why some BMC models are so slow compared to a plain ARM
virt machines I did some profiling of:
./qemu-system-arm -M romulus-bmc -nic user \
-drive
file=obmc-phosphor-image-romulus.static.mtd,format=raw,if=mtd \
-nographic -serial mon:stdio
And saw that object_class_dynamic_cast_assert was dominating the
profile times. We have a number of cases in this model of the SSI bus.
As the class is static once the object is created we just cache it and
use it instead of the dynamic case macros.
Profiling against:
./tests/venv/bin/avocado run \
tests/avocado/machine_aspeed.py:test_arm_ast2500_romulus_openbmc_v2_9_0
Before: 35.565 s ± 0.087 s
After: 15.713 s ± 0.287 s
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220811151413.3350684-6-alex.bennee@linaro.org>
Message-Id: <20220923084803.498337-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: b84a9482a3c9e3b6fbdf1fd4b0477e4a7a51683e
https://github.com/qemu/qemu/commit/b84a9482a3c9e3b6fbdf1fd4b0477e4a7a51683e
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M hw/ssi/aspeed_smc.c
M include/hw/ssi/aspeed_smc.h
Log Message:
-----------
aspeed/smc: Cache AspeedSMCClass
Store a reference on the AspeedSMC class under the flash object and
use it when accessing the flash contents. Avoiding the class cast
checkers in these hot paths improves performance by 10% when running
the aspeed avocado tests.
Message-Id: <20220923084803.498337-7-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: e5c1b489acac6e2d264c67d5c0665ef940f85e86
https://github.com/qemu/qemu/commit/e5c1b489acac6e2d264c67d5c0665ef940f85e86
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M hw/arm/aspeed_ast2600.c
Log Message:
-----------
ast2600: Drop NEON from the CPU features
Currently, the CPU features exposed to the AST2600 QEMU machines are :
half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt
vfpd32 lpae evtstrm
But, the features of the Cortex A7 CPU on the Aspeed AST2600 A3 SoC
are :
half thumb fastmult vfp edsp vfpv3 vfpv3d16 tls vfpv4 idiva idivt
lpae evtstrm
Drop NEON support in the Aspeed AST2600 SoC.
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20220928164719.655586-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 104bdaffd753042c652a3731753fc3b391e32d87
https://github.com/qemu/qemu/commit/104bdaffd753042c652a3731753fc3b391e32d87
Author: Patrick Williams <patrick@stwcx.xyz>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: increase Bletchley memory size
For the PVT-class hardware we have increased the memory size of
this device to 2 GiB. Adjust the device model accordingly.
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20221007110529.3657749-1-patrick@stwcx.xyz>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2389bcc259df915d1b244b270e9c3d3d7e097a88
https://github.com/qemu/qemu/commit/2389bcc259df915d1b244b270e9c3d3d7e097a88
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M MAINTAINERS
M hw/block/m25p80.c
A hw/block/m25p80_sfdp.h
M hw/block/trace-events
Log Message:
-----------
m25p80: Add basic support for the SFDP command
JEDEC STANDARD JESD216 for Serial Flash Discovery Parameters (SFDP)
provides a mean to describe the features of a serial flash device
using a set of internal parameter tables.
This is the initial framework for the RDSFDP command giving access to
a private SFDP area under the flash. This area now needs to be
populated with the flash device characteristics, using a new
'sfdp_read' handler under FlashPartInfo.
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-2-clg@kaod.org>
Message-Id: <20221013161241.2805140-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 5eb24fbd8c82fc71282fa6db5184a40e560ed25c
https://github.com/qemu/qemu/commit/5eb24fbd8c82fc71282fa6db5184a40e560ed25c
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M hw/block/m25p80.c
A hw/block/m25p80_sfdp.c
M hw/block/m25p80_sfdp.h
M hw/block/meson.build
Log Message:
-----------
m25p80: Add the n25q256a SFDP table
The same values were collected on 4 differents OpenPower systems,
palmettos, romulus and tacoma.
The SFDP table size is defined as being 0x100 bytes but it could be
bigger. Only the mandatory table for basic features is available at
byte 0x30.
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-3-clg@kaod.org>
Message-Id: <20221013161241.2805140-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 0c14a3c7da01d7a7343824ed08c664e98b9c4057
https://github.com/qemu/qemu/commit/0c14a3c7da01d7a7343824ed08c664e98b9c4057
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
m25p80: Add erase size for mx25l25635e
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20221013161241.2805140-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: dc907a667cbd2689a3618608c0c079fb03926ec3
https://github.com/qemu/qemu/commit/dc907a667cbd2689a3618608c0c079fb03926ec3
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M hw/block/m25p80.c
M hw/block/m25p80_sfdp.c
M hw/block/m25p80_sfdp.h
Log Message:
-----------
m25p80: Add the mx25l25635e SFPD table
The SFDP table is 0x80 bytes long. The mandatory table for basic
features is available at byte 0x30 and an extra Macronix specific
table is available at 0x60.
4B opcodes are not supported.
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-4-clg@kaod.org>
Message-Id: <20221013161241.2805140-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 51f4613d6514b4cfb132997b81d6d70be86fef8a
https://github.com/qemu/qemu/commit/51f4613d6514b4cfb132997b81d6d70be86fef8a
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M hw/block/m25p80.c
M hw/block/m25p80_sfdp.c
M hw/block/m25p80_sfdp.h
Log Message:
-----------
m25p80: Add the mx25l25635f SFPD table
The mx25l25635e and mx25l25635f chips have the same JEDEC id but the
mx25l25635f has more capabilities reported in the SFDP table. Support
for 4B opcodes is of interest because it is exploited by the Linux
kernel.
The SFDP table size is 0x200 bytes long. The mandatory table for basic
features is available at byte 0x30 and an extra Macronix specific
table is available at 0x60.
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-5-clg@kaod.org>
Message-Id: <20221013161241.2805140-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 52514908ffb35bcd2f443fe5fe7c3b8f8d83ae33
https://github.com/qemu/qemu/commit/52514908ffb35bcd2f443fe5fe7c3b8f8d83ae33
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M hw/block/m25p80.c
M hw/block/m25p80_sfdp.c
M hw/block/m25p80_sfdp.h
Log Message:
-----------
m25p80: Add the mx66l1g45g SFDP table
The SFDP table size is 0x200 bytes long. The mandatory table for basic
features is available at byte 0x30 plus some more Macronix specific
tables.
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-6-clg@kaod.org>
Message-Id: <20221013161241.2805140-7-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: e9041884d273928286733a3e966cd89d7cc2d1c4
https://github.com/qemu/qemu/commit/e9041884d273928286733a3e966cd89d7cc2d1c4
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M hw/block/m25p80.c
M hw/block/m25p80_sfdp.c
M hw/block/m25p80_sfdp.h
Log Message:
-----------
m25p80: Add the w25q256 SFPD table
The SFDP table size is 0x100 bytes long. Only the mandatory table for
basic features is available at byte 0x80.
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-7-clg@kaod.org>
Message-Id: <20221013161241.2805140-8-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 8e57da5856e47904029d982240ed25c3cdef5e80
https://github.com/qemu/qemu/commit/8e57da5856e47904029d982240ed25c3cdef5e80
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M hw/block/m25p80.c
M hw/block/m25p80_sfdp.c
M hw/block/m25p80_sfdp.h
Log Message:
-----------
m25p80: Add the w25q512jv SFPD table
The SFDP table size is 0x100 bytes long. The mandatory table for basic
features is available at byte 0x80 and two extra Winbond specifics
table are available at 0xC0 and 0xF0.
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-8-clg@kaod.org>
Message-Id: <20221013161241.2805140-9-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a34b0d5315522159ba723feecf507a4d07e043f3
https://github.com/qemu/qemu/commit/a34b0d5315522159ba723feecf507a4d07e043f3
Author: Patrick Williams <patrick@stwcx.xyz>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M hw/block/m25p80.c
M hw/block/m25p80_sfdp.c
M hw/block/m25p80_sfdp.h
Log Message:
-----------
m25p80: Add the w25q01jvq SFPD table
Generated from hardware using the following command and then padding
with 0xff to fill out a power-of-2:
hexdump -v -e '8/1 "0x%02x, " "\n"' sfdp`
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
[ clg: removed extern ]
Message-Id: <20221006224424.3556372-1-patrick@stwcx.xyz>
Message-Id: <20221013161241.2805140-10-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 703229132bb05327044368fc6d19f6acf7dde848
https://github.com/qemu/qemu/commit/703229132bb05327044368fc6d19f6acf7dde848
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
arm/aspeed: Replace mx25l25635e chip model
A mx25l25635f chip model is generally found on these machines. It's
newer and uses 4B opcodes which is better to exercise the support in
the Linux kernel.
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-9-clg@kaod.org>
Message-Id: <20221013161241.2805140-11-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: e41ed29bcee5cb16715317bcf290f6b5c196eb0a
https://github.com/qemu/qemu/commit/e41ed29bcee5cb16715317bcf290f6b5c196eb0a
Author: Janosch Frank <frankja@linux.ibm.com>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M dump/dump.c
M include/sysemu/dump.h
Log Message:
-----------
dump: Use a buffer for ELF section data and headers
Currently we're writing the NULL section header if we overflow the
physical header number in the ELF header. But in the future we'll add
custom section headers AND section data.
To facilitate this we need to rearange section handling a bit. As with
the other ELF headers we split the code into a prepare and a write
step.
Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20221017083822.43118-2-frankja@linux.ibm.com>
Commit: cb415fd61e48d52f81dcf38956e3f913651cff1c
https://github.com/qemu/qemu/commit/cb415fd61e48d52f81dcf38956e3f913651cff1c
Author: Janosch Frank <frankja@linux.ibm.com>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M dump/dump.c
Log Message:
-----------
dump: Write ELF section headers right after ELF header
Let's start bundling the writes of the headers and of the data so we
have a clear ordering between them. Since the ELF header uses offsets
to the headers we can freely order them.
Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20221017083822.43118-3-frankja@linux.ibm.com>
Commit: 8384b73c46fd474847d7e74d121318e344edc3c4
https://github.com/qemu/qemu/commit/8384b73c46fd474847d7e74d121318e344edc3c4
Author: Janosch Frank <frankja@linux.ibm.com>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M include/sysemu/dump.h
Log Message:
-----------
dump: Reorder struct DumpState
Let's move ELF related members into one block and guest memory related
ones into another to improve readability.
Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20221017083822.43118-4-frankja@linux.ibm.com>
Commit: 13fd417ddc81a1685c6a8f4e1c80bbfe7150f164
https://github.com/qemu/qemu/commit/13fd417ddc81a1685c6a8f4e1c80bbfe7150f164
Author: Janosch Frank <frankja@linux.ibm.com>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M dump/dump.c
Log Message:
-----------
dump: Reintroduce memory_offset and section_offset
section_offset will later be used to store the offset to the section
data which will be stored last. For now memory_offset is only needed
to make section_offset look nicer.
Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20221017083822.43118-5-frankja@linux.ibm.com>
Commit: 9b72224f44612ddd5b434a1bccf79346946d11da
https://github.com/qemu/qemu/commit/9b72224f44612ddd5b434a1bccf79346946d11da
Author: Janosch Frank <frankja@linux.ibm.com>
Date: 2022-10-24 (Mon, 24 Oct 2022)
Changed paths:
M dump/dump.c
M include/sysemu/dump-arch.h
M include/sysemu/dump.h
Log Message:
-----------
dump: Add architecture section and section string table support
Add hooks which architectures can use to add arbitrary data to custom
sections.
Also add a section name string table in order to identify section
contents
Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20221017113210.41674-1-frankja@linux.ibm.com>
Commit: 0585105c806d3bf301eebc33115a0790fcfc1d9c
https://github.com/qemu/qemu/commit/0585105c806d3bf301eebc33115a0790fcfc1d9c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M accel/tcg/tcg-accel-ops-mttcg.c
M accel/tcg/tcg-accel-ops-rr.c
Log Message:
-----------
Revert "accel/tcg: Init TCG cflags in vCPU thread handler"
Commit a82fd5a4ec24d was intended to be a code cleanup, but
unfortunately it has a bug. It moves the initialization of the
TCG cflags from the "start a new vcpu" function to the
thread handler; this is fine when each vcpu has its own thread,
but when we are doing round-robin of vcpus on a single thread
we end up only initializing the cflags for CPU 0, not for any
of the others.
The most obvious effect of this bug is that running in icount
mode with more than one CPU is broken; typically the guest
hangs shortly after it brings up the secondary CPUs.
This reverts commit a82fd5a4ec24d923ff1e6da128c0fd4a74079d99.
Cc: qemu-stable@nongnu.org
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20221021163409.3674911-1-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f072a1ae7fb47db75eb3c6b960759c908884f585
https://github.com/qemu/qemu/commit/f072a1ae7fb47db75eb3c6b960759c908884f585
Author: Qi Hu <huqi@loongson.cn>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M tcg/loongarch64/tcg-target.c.inc
M tcg/loongarch64/tcg-target.h
Log Message:
-----------
tcg/loongarch64: Add direct jump support
Similar to the ARM64, LoongArch has PC-relative instructions such as
PCADDU18I. These instructions can be used to support direct jump for
LoongArch. Additionally, if instruction "B offset" can cover the target
address(target is within ±128MB range), a single "B offset" plus a nop
will be used by "tb_target_set_jump_target".
Signed-off-by: Qi Hu <huqi@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: WANG Xuerui <git@xen0n.name>
Message-Id: <20221015092754.91971-1-huqi@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 122167659c50958f98cb2a153de97541f03462ff
https://github.com/qemu/qemu/commit/122167659c50958f98cb2a153de97541f03462ff
Author: Qi Hu <huqi@loongson.cn>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Remove unused code in tcg_out_op
AArch64 defines the TCG_TARGET_HAS_direct_jump. So the "else" block is
useless in the case of "INDEX_op_goto_tb" in function "tcg_out_op". Add
an assertion and delete these codes for clarity.
Suggested-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Qi Hu <huqi@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221017020826.990729-1-huqi@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e894ee2d787ce7253ef8d8091d9a26571ca8b9a5
https://github.com/qemu/qemu/commit/e894ee2d787ce7253ef8d8091d9a26571ca8b9a5
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/ptw.c
Log Message:
-----------
target/arm: Implement FEAT_E0PD
FEAT_E0PD adds new bits E0PD0 and E0PD1 to TCR_EL1, which allow the
OS to forbid EL0 access to half of the address space. Since this is
an EL0-specific variation on the existing TCR_ELx.{EPD0,EPD1}, we can
implement it entirely in aa64_va_parameters().
This requires moving the existing regime_is_user() to internals.h
so that the code in helper.c can get at it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221021160131.3531787-1-peter.maydell@linaro.org
Commit: 6d3377b627c435c3458d9088c3c7e724f0492b2c
https://github.com/qemu/qemu/commit/6d3377b627c435c3458d9088c3c7e724f0492b2c
Author: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Fix devicetree warnings about the virtio-iommu node
The "PCI Bus Binding to: IEEE Std 1275-1994" defines the compatible
string for a PCIe bus or endpoint as "pci<vendorid>,<deviceid>" or
similar. Since the initial binding for PCI virtio-iommu didn't follow
this rule, it was modified to accept both strings and ensure backward
compatibility. Also, the unit-name for the node should be
"device,function".
Fix corresponding dt-validate and dtc warnings:
pcie@10000000: virtio_iommu@16:compatible: ['virtio,pci-iommu'] does not
contain items matching the given schema
pcie@10000000: Unevaluated properties are not allowed (... 'virtio_iommu@16'
were unexpected)
From schema: linux/Documentation/devicetree/bindings/pci/host-generic-pci.yaml
virtio_iommu@16: compatible: 'oneOf' conditional failed, one must be fixed:
['virtio,pci-iommu'] is too short
'pci1af4,1057' was expected
From schema: dtschema/schemas/pci/pci-bus.yaml
Warning (pci_device_reg): /pcie@10000000/virtio_iommu@16: PCI unit address
format error, expected "2,0"
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5541fb18a2ea65754c7c3d14511e9d1ff375c278
https://github.com/qemu/qemu/commit/5541fb18a2ea65754c7c3d14511e9d1ff375c278
Author: Ake Koomsin <ake@igel.co.jp>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: honor HCR_E2H and HCR_TGE in arm_excp_unmasked()
An exception targeting EL2 from lower EL is actually maskable when
HCR_E2H and HCR_TGE are both set. This applies to both secure and
non-secure Security state.
We can remove the conditions that try to suppress masking of
interrupts when we are Secure and the exception targets EL2 and
Secure EL2 is disabled. This is OK because in that situation
arm_phys_excp_target_el() will never return 2 as the target EL. The
'not if secure' check in this function was originally written before
arm_hcr_el2_eff(), and back then the target EL returned by
arm_phys_excp_target_el() could be 2 even if we were in Secure
EL0/EL1; but it is no longer needed.
Signed-off-by: Ake Koomsin <ake@igel.co.jp>
Message-id: 20221017092432.546881-1-ake@igel.co.jp
[PMM: Add commit message paragraph explaining why it's OK to
remove the checks on secure and SCR_EEL2]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 02b4a234cf4d2a2800789b2519b08c439c80b30d
https://github.com/qemu/qemu/commit/02b4a234cf4d2a2800789b2519b08c439c80b30d
Author: Damien Hedde <damien.hedde@greensocs.com>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M docs/devel/reset.rst
M hw/core/resettable.c
Log Message:
-----------
hw/core/resettable: fix reset level counting
The code for handling the reset level count in the Resettable code
has two issues:
The reset count is only decremented for the 1->0 case. This means
that if there's ever a nested reset that takes the count to 2 then it
will never again be decremented. Eventually the count will exceed
the '50' limit in resettable_phase_enter() and QEMU will trip over
the assertion failure. The repro case in issue 1266 is an example of
this that happens now the SCSI subsystem uses three-phase reset.
Secondly, the count is decremented only after the exit phase handler
is called. Moving the reset count decrement from "just after" to
"just before" calling the exit phase handler allows
resettable_is_in_reset() to return false during the handler
execution.
This simplifies reset handling in resettable devices. Typically, a
function that updates the device state will just need to read the
current reset state and not anymore treat the "in a reset-exit
transition" as a special case.
Note that the semantics change to the *_is_in_reset() functions
will have no effect on the current codebase, because only two
devices (hw/char/cadence_uart.c and hw/misc/zynq_sclr.c) currently
call those functions, and in neither case do they do it from the
device's exit phase methed.
Fixes: 4a5fc890 ("scsi: Use device_cold_reset() and bus_cold_reset()")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1266
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reported-by: Michael Peter <michael.peter@hensoldt-cyber.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221020142749.3357951-1-peter.maydell@linaro.org
Buglink: https://bugs.launchpad.net/qemu/+bug/1905297
Reported-by: Michael Peter <michael.peter@hensoldt-cyber.com>
[PMM: adjust the docs paragraph changed to get the name of the
'enter' phase right and to clarify exactly when the count is
adjusted; rewrite the commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ac8ae54d07d36da1e0ad08aa1c187b2ee44d945c
https://github.com/qemu/qemu/commit/ac8ae54d07d36da1e0ad08aa1c187b2ee44d945c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M hw/hyperv/hyperv.c
Log Message:
-----------
hw/hyperv/hyperv.c: Use device_cold_reset() instead of device_legacy_reset()
The semantic difference between the deprecated device_legacy_reset()
function and the newer device_cold_reset() function is that the new
function resets both the device itself and any qbuses it owns,
whereas the legacy function resets just the device itself and nothing
else. In hyperv_synic_reset() we reset a SynICState, which has no
qbuses, so for this purpose the two functions behave identically and
we can stop using the deprecated one.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Message-id: 20221013171817.1447562-1-peter.maydell@linaro.org
Commit: 617ebefd25b4a806f0cfe9878d1007254980101d
https://github.com/qemu/qemu/commit/617ebefd25b4a806f0cfe9878d1007254980101d
Author: Axel Heider <axel.heider@hensoldt.net>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M hw/timer/imx_epit.c
Log Message:
-----------
target/imx: reload cmp timer outside of the reload ptimer transaction
When running seL4 tests (https://docs.sel4.systems/projects/sel4test)
on the sabrelight platform, the timer tests fail. The arm/imx6 EPIT
timer interrupt does not fire properly, instead of a e.g. second in
can take up to a minute to finally see the interrupt.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1263
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Message-id: 166663118138.13362.1229967229046092876-0@git.sr.ht
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e0e6e25ad23005b4980a8e61296d6f4ae9f7cbf5
https://github.com/qemu/qemu/commit/e0e6e25ad23005b4980a8e61296d6f4ae9f7cbf5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
M target/arm/ptw.c
Log Message:
-----------
target/arm: Introduce regime_is_stage2
Reduce the amount of typing required for this check.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221024051851.3074715-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4a3321dab936086e3dc1528d5924a68494a47ea6
https://github.com/qemu/qemu/commit/4a3321dab936086e3dc1528d5924a68494a47ea6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Add ptw_idx to S1Translate
Hoist the computation of the mmu_idx for the ptw up to
get_phys_addr_with_struct and get_phys_addr_twostage.
This removes the duplicate check for stage2 disabled
from the middle of the walk, performing it only once.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20221024051851.3074715-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3cc3b338dea6c78953e00210bbda603b60416eac
https://github.com/qemu/qemu/commit/3cc3b338dea6c78953e00210bbda603b60416eac
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Add isar predicates for FEAT_HAFDBS
The MMFR1 field may indicate support for hardware update of
access flag alone, or access flag and dirty bit.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221024051851.3074715-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0926f0ef962aaf09aae2f4f9a4a23b37e57426d6
https://github.com/qemu/qemu/commit/0926f0ef962aaf09aae2f4f9a4a23b37e57426d6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Extract HA and HD in aa64_va_parameters
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20221024051851.3074715-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 585c32f33137b739c246c9f7cee2d3fe606b0e0d
https://github.com/qemu/qemu/commit/585c32f33137b739c246c9f7cee2d3fe606b0e0d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw
Separate S1 translation from the actual lookup.
Will enable lpae hardware updates.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221024051851.3074715-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e3a1e3530631de7833cf2abca76de4a75be1db3d
https://github.com/qemu/qemu/commit/e3a1e3530631de7833cf2abca76de4a75be1db3d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M target/arm/internals.h
Log Message:
-----------
target/arm: Add ARMFault_UnsuppAtomicUpdate
This fault type is to be used with FEAT_HAFDBS when
the guest enables hw updates, but places the tables
in memory where atomic updates are unsupported.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20221024051851.3074715-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7377d400c71f0491e23f908d4cd73eb847cf88d9
https://github.com/qemu/qemu/commit/7377d400c71f0491e23f908d4cd73eb847cf88d9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Remove loop from get_phys_addr_lpae
The unconditional loop was used both to iterate over levels
and to control parsing of attributes. Use an explicit goto
in both cases.
While this appears less clean for iterating over levels, we
will need to jump back into the middle of this loop for
atomic updates, which is even uglier.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221024051851.3074715-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: eadf98f836bcbfb0ed561312addfdfcbd3f36804
https://github.com/qemu/qemu/commit/eadf98f836bcbfb0ed561312addfdfcbd3f36804
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Fix fault reporting in get_phys_addr_lpae
Always overriding fi->type was incorrect, as we would not properly
propagate the fault type from S1_ptw_translate, or arm_ldq_ptw.
Simplify things by providing a new label for a translation fault.
For other faults, store into fi directly.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20221024051851.3074715-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 086d13aaabbbd7faf8178d501b7c931e718e61a6
https://github.com/qemu/qemu/commit/086d13aaabbbd7faf8178d501b7c931e718e61a6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Don't shift attrs in get_phys_addr_lpae
Leave the upper and lower attributes in the place they originate
from in the descriptor. Shifting them around is confusing, since
one cannot read the bit numbers out of the manual. Also, new
attributes have been added which would alter the shifts.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221024051851.3074715-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4f0019497a28d4d722ef9cc1dfa71aadcdfe9f8a
https://github.com/qemu/qemu/commit/4f0019497a28d4d722ef9cc1dfa71aadcdfe9f8a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Consider GP an attribute in get_phys_addr_lpae
Both GP and DBM are in the upper attribute block.
Extend the computation of attrs to include them,
then simplify the setting of guarded.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20221024051851.3074715-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ae4eb20778c98d6f6cb109e9bc1429138d40dde2
https://github.com/qemu/qemu/commit/ae4eb20778c98d6f6cb109e9bc1429138d40dde2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Tidy merging of attributes from descriptor and table
Replace some gotos with some nested if statements.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20221024051851.3074715-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0d14c40d8625d4b226367b984eca4d4e033b98e2
https://github.com/qemu/qemu/commit/0d14c40d8625d4b226367b984eca4d4e033b98e2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
M target/arm/ptw.c
Log Message:
-----------
target/arm: Implement FEAT_HAFDBS, access flag portion
Perform the atomic update for hardware management of the access flag.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221024051851.3074715-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 185c79d719f507689acee89f144c4d0afb1b8798
https://github.com/qemu/qemu/commit/185c79d719f507689acee89f144c4d0afb1b8798
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M target/arm/cpu64.c
M target/arm/ptw.c
Log Message:
-----------
target/arm: Implement FEAT_HAFDBS, dirty bit portion
Perform the atomic update for hardware management of the dirty bit.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221024051851.3074715-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3f78ef7cb94a52522eff7208a8c0087fb7d2e0b7
https://github.com/qemu/qemu/commit/3f78ef7cb94a52522eff7208a8c0087fb7d2e0b7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Use the max page size in a 2-stage ptw
We had only been reporting the stage2 page size. This causes
problems if stage1 is using a larger page size (16k, 2M, etc),
but stage2 is using a smaller page size, because cputlb does
not set large_page_{addr,mask} properly.
Fix by using the max of the two page sizes.
Reported-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221024051851.3074715-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 699cbbd85f45e6b8c28cf8bede01c02905d33b0b
https://github.com/qemu/qemu/commit/699cbbd85f45e6b8c28cf8bede01c02905d33b0b
Author: Jason A. Donenfeld <Jason@zx2c4.com>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/mps2-tz.c
M hw/core/reset.c
M hw/hppa/machine.c
M hw/i386/microvm.c
M hw/i386/pc.c
M hw/ppc/pegasos2.c
M hw/ppc/pnv.c
M hw/ppc/spapr.c
M hw/s390x/s390-virtio-ccw.c
M include/hw/boards.h
M include/sysemu/reset.h
M migration/savevm.c
M qapi/run-state.json
M softmmu/runstate.c
Log Message:
-----------
reset: allow registering handlers that aren't called by snapshot loading
Snapshot loading only expects to call deterministic handlers, not
non-deterministic ones. So introduce a way of registering handlers that
won't be called when reseting for snapshots.
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Message-id: 20221025004327.568476-2-Jason@zx2c4.com
[PMM: updated json doc comment with Markus' text; fixed
checkpatch style nit]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5db9dbcd94538c1a880d90886fb56a70c11e863c
https://github.com/qemu/qemu/commit/5db9dbcd94538c1a880d90886fb56a70c11e863c
Author: Jason A. Donenfeld <Jason@zx2c4.com>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M include/sysemu/device_tree.h
M softmmu/device_tree.c
Log Message:
-----------
device-tree: add re-randomization helper function
When the system reboots, the rng-seed that the FDT has should be
re-randomized, so that the new boot gets a new seed. Several
architectures require this functionality, so export a function for
injecting a new seed into the given FDT.
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20221025004327.568476-3-Jason@zx2c4.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 79e7f00525f0340df5cdda4a5ea1b84fcbf33eed
https://github.com/qemu/qemu/commit/79e7f00525f0340df5cdda4a5ea1b84fcbf33eed
Author: Jason A. Donenfeld <Jason@zx2c4.com>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M hw/i386/x86.c
Log Message:
-----------
x86: do not re-randomize RNG seed on snapshot load
Snapshot loading is supposed to be deterministic, so we shouldn't
re-randomize the various seeds used.
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Message-id: 20221025004327.568476-4-Jason@zx2c4.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 354f7c937c91b35d664d1be3e2d80ebb88da33c5
https://github.com/qemu/qemu/commit/354f7c937c91b35d664d1be3e2d80ebb88da33c5
Author: Jason A. Donenfeld <Jason@zx2c4.com>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M hw/arm/boot.c
Log Message:
-----------
arm: re-randomize rng-seed on reboot
When the system reboots, the rng-seed that the FDT has should be
re-randomized, so that the new boot gets a new seed. Since the FDT is in
the ROM region at this point, we add a hook right after the ROM has been
added, so that we have a pointer to that copy of the FDT.
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Message-id: 20221025004327.568476-5-Jason@zx2c4.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a3b59c3bbe63d283aa59814d8ff3f3b9014d41bf
https://github.com/qemu/qemu/commit/a3b59c3bbe63d283aa59814d8ff3f3b9014d41bf
Author: Jason A. Donenfeld <Jason@zx2c4.com>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M hw/riscv/boot.c
Log Message:
-----------
riscv: re-randomize rng-seed on reboot
When the system reboots, the rng-seed that the FDT has should be
re-randomized, so that the new boot gets a new seed. Since the FDT is in
the ROM region at this point, we add a hook right after the ROM has been
added, so that we have a pointer to that copy of the FDT.
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bin.meng@windriver.com>
Cc: qemu-riscv@nongnu.org
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20221025004327.568476-6-Jason@zx2c4.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1c9c61f7bdcb3b2ebaf1b5eb1cda6f099c3bb4eb
https://github.com/qemu/qemu/commit/1c9c61f7bdcb3b2ebaf1b5eb1cda6f099c3bb4eb
Author: Jason A. Donenfeld <Jason@zx2c4.com>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M hw/m68k/virt.c
Log Message:
-----------
m68k/virt: do not re-randomize RNG seed on snapshot load
Snapshot loading is supposed to be deterministic, so we shouldn't
re-randomize the various seeds used.
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Message-id: 20221025004327.568476-7-Jason@zx2c4.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a86a79c163ae1c21798834498f212d9f3e1f8fc0
https://github.com/qemu/qemu/commit/a86a79c163ae1c21798834498f212d9f3e1f8fc0
Author: Jason A. Donenfeld <Jason@zx2c4.com>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M hw/m68k/q800.c
Log Message:
-----------
m68k/q800: do not re-randomize RNG seed on snapshot load
Snapshot loading is supposed to be deterministic, so we shouldn't
re-randomize the various seeds used.
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Message-id: 20221025004327.568476-8-Jason@zx2c4.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0a3ac01929d04544d6e42d5e999abdb557cbc053
https://github.com/qemu/qemu/commit/0a3ac01929d04544d6e42d5e999abdb557cbc053
Author: Jason A. Donenfeld <Jason@zx2c4.com>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M hw/mips/boston.c
Log Message:
-----------
mips/boston: re-randomize rng-seed on reboot
When the system reboots, the rng-seed that the FDT has should be
re-randomized, so that the new boot gets a new seed. Since the FDT is in
the ROM region at this point, we add a hook right after the ROM has been
added, so that we have a pointer to that copy of the FDT.
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Message-id: 20221025004327.568476-9-Jason@zx2c4.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5862f312b3849f798c2748623a5ed22e8e9e4ff9
https://github.com/qemu/qemu/commit/5862f312b3849f798c2748623a5ed22e8e9e4ff9
Author: Jason A. Donenfeld <Jason@zx2c4.com>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M hw/openrisc/boot.c
Log Message:
-----------
openrisc: re-randomize rng-seed on reboot
When the system reboots, the rng-seed that the FDT has should be
re-randomized, so that the new boot gets a new seed. Since the FDT is in
the ROM region at this point, we add a hook right after the ROM has been
added, so that we have a pointer to that copy of the FDT.
Cc: Stafford Horne <shorne@gmail.com>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Message-id: 20221025004327.568476-11-Jason@zx2c4.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e2114f701c78f76246e4b1872639dad94a6bdd21
https://github.com/qemu/qemu/commit/e2114f701c78f76246e4b1872639dad94a6bdd21
Author: Jason A. Donenfeld <Jason@zx2c4.com>
Date: 2022-10-25 (Tue, 25 Oct 2022)
Changed paths:
M hw/rx/rx-gdbsim.c
Log Message:
-----------
rx: re-randomize rng-seed on reboot
When the system reboots, the rng-seed that the FDT has should be
re-randomized, so that the new boot gets a new seed. Since the FDT is in
the ROM region at this point, we add a hook right after the ROM has been
added, so that we have a pointer to that copy of the FDT.
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Message-id: 20221025004327.568476-12-Jason@zx2c4.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 69993c4e627a4e4d4d084bef643b446c97fee0f5
https://github.com/qemu/qemu/commit/69993c4e627a4e4d4d084bef643b446c97fee0f5
Author: Leandro Lupori <leandro.lupori@eldorado.org.br>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/cpu-exec.c
Log Message:
-----------
accel/tcg: Add a quicker check for breakpoints
Profiling QEMU during Fedora 35 for PPC64 boot revealed that a
considerable amount of time was being spent in
check_for_breakpoints() (0.61% of total time on PPC64 and 2.19% on
amd64), even though it was just checking that its queue was empty
and returning, when no breakpoints were set. It turns out this
function is not inlined by the compiler and it's always called by
helper_lookup_tb_ptr(), one of the most called functions.
By leaving only the check for empty queue in
check_for_breakpoints() and moving the remaining code to
check_for_breakpoints_slow(), called only when the queue is not
empty, it's possible to avoid the call overhead. An improvement of
about 3% in total time was measured on POWER9.
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221025202424.195984-2-leandro.lupori@eldorado.org.br>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d44e3737f937c0d0da1ad18d7b48bfc3ed885e1a
https://github.com/qemu/qemu/commit/d44e3737f937c0d0da1ad18d7b48bfc3ed885e1a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M include/qemu/osdep.h
Log Message:
-----------
include/qemu/osdep: Add qemu_build_assert
This differs from assert, in that with optimization enabled it
triggers at build-time. It differs from QEMU_BUILD_BUG_ON,
aka _Static_assert, in that it is sensitive to control flow
and is subject to dead-code elimination.
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 590536369f8eb2f3410fa3a1af329891f3fc58e3
https://github.com/qemu/qemu/commit/590536369f8eb2f3410fa3a1af329891f3fc58e3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M include/qemu/atomic.h
Log Message:
-----------
include/qemu/atomic: Use qemu_build_assert
Change from QEMU_BUILD_BUG_ON, which requires ifdefs to avoid
problematic code, to qemu_build_assert, which can use C ifs.
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 7ed9e721cce2ccf6a1da22cd0e713c2a0d187457
https://github.com/qemu/qemu/commit/7ed9e721cce2ccf6a1da22cd0e713c2a0d187457
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M include/qemu/thread.h
Log Message:
-----------
include/qemu/thread: Use qatomic_* functions
Use qatomic_*, which expands to __atomic_* in preference
to the "legacy" __sync_* functions.
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 50d4c8c1d433ae843a6b86a65467c507095f65f1
https://github.com/qemu/qemu/commit/50d4c8c1d433ae843a6b86a65467c507095f65f1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/translate-all.c
M include/exec/cpu-all.h
M target/arm/cpu.h
M target/arm/internals.h
M target/arm/mte_helper.c
Log Message:
-----------
accel/tcg: Make page_alloc_target_data allocation constant
Use a constant target data allocation size for all pages.
This will be necessary to reduce overhead of page tracking.
Since TARGET_PAGE_DATA_SIZE is now required, we can use this
to omit data tracking for targets that don't require it.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f5e80399748c735d7bddab12f734348942992276
https://github.com/qemu/qemu/commit/f5e80399748c735d7bddab12f734348942992276
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/translate-all.c
Log Message:
-----------
accel/tcg: Remove disabled debug in translate-all.c
These items printf, and could be replaced with proper
tracepoints if we really cared.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 55098769bfdefaed29796bc5104cfc8a202962fc
https://github.com/qemu/qemu/commit/55098769bfdefaed29796bc5104cfc8a202962fc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/internal.h
M accel/tcg/translate-all.c
Log Message:
-----------
accel/tcg: Split out PageDesc to internal.h
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 8a14b62c3fc89a46fbf61c9cc96cb470a6ad9de5
https://github.com/qemu/qemu/commit/8a14b62c3fc89a46fbf61c9cc96cb470a6ad9de5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/internal.h
M accel/tcg/meson.build
A accel/tcg/tb-maint.c
M accel/tcg/translate-all.c
Log Message:
-----------
accel/tcg: Split out tb-maint.c
Move all of the TranslationBlock flushing and page linking
code from translate-all.c to tb-maint.c.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: cc05368ad999a5e06890a829b2ccba7ae4e0fe8b
https://github.com/qemu/qemu/commit/cc05368ad999a5e06890a829b2ccba7ae4e0fe8b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/internal.h
M include/exec/exec-all.h
Log Message:
-----------
accel/tcg: Move assert_no_pages_locked to internal.h
There are no users outside of accel/tcg; this function
does not need to be defined in exec-all.h.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 8516e2a92c9011fed1d1601dd69872dba083d5c6
https://github.com/qemu/qemu/commit/8516e2a92c9011fed1d1601dd69872dba083d5c6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/tb-maint.c
Log Message:
-----------
accel/tcg: Drop cpu_get_tb_cpu_state from TARGET_HAS_PRECISE_SMC
The results of the calls to cpu_get_tb_cpu_state,
current_{pc,cs_base,flags}, are not used.
In tb_invalidate_phys_page, use bool for current_tb_modified.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4c88475c9fe501b5c886a963647670f929c65400
https://github.com/qemu/qemu/commit/4c88475c9fe501b5c886a963647670f929c65400
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/tb-maint.c
Log Message:
-----------
accel/tcg: Remove duplicate store to tb->page_addr[]
When we added the fast path, we initialized page_addr[] early.
These stores in and around tb_page_add() are redundant; remove them.
Fixes: 50627f1b7b1 ("accel/tcg: Add fast path for translator_ld*")
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 28905cfbd521c40ebc6d7b4c5941c0ec1ca935eb
https://github.com/qemu/qemu/commit/28905cfbd521c40ebc6d7b4c5941c0ec1ca935eb
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/tb-maint.c
M accel/tcg/translate-all.c
M accel/tcg/translator.c
M include/exec/exec-all.h
Log Message:
-----------
accel/tcg: Introduce tb_{set_}page_addr{0,1}
This data structure will be replaced for user-only: add accessors.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 67aabbb312eda2316011aab5b54c37d08c82f933
https://github.com/qemu/qemu/commit/67aabbb312eda2316011aab5b54c37d08c82f933
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/internal.h
M accel/tcg/tb-maint.c
M accel/tcg/translate-all.c
Log Message:
-----------
accel/tcg: Rename tb_invalidate_phys_page
Rename to tb_invalidate_phys_page_unwind to emphasize that
we also detect invalidating the current TB, and also to free
up that name for other usage.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d6d1fd29733c1b575bd928066024be6f2bb05d42
https://github.com/qemu/qemu/commit/d6d1fd29733c1b575bd928066024be6f2bb05d42
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/tb-maint.c
M cpu.c
M include/exec/translate-all.h
Log Message:
-----------
accel/tcg: Rename tb_invalidate_phys_page_range and drop end parameter
This function is is never called with a real range,
only for a single page. Drop the second parameter
and rename to tb_invalidate_phys_page.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 65cd34e8c445079279abf16d127f138141a360e4
https://github.com/qemu/qemu/commit/65cd34e8c445079279abf16d127f138141a360e4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/tb-maint.c
M include/exec/exec-all.h
M include/exec/ram_addr.h
Log Message:
-----------
accel/tcg: Unify declarations of tb_invalidate_phys_range
We missed this function when we introduced tb_page_addr_t.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 24ace1ac3cf4d64bc76b543224c1c0379fa34b51
https://github.com/qemu/qemu/commit/24ace1ac3cf4d64bc76b543224c1c0379fa34b51
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/translate-all.c
Log Message:
-----------
accel/tcg: Use tb_invalidate_phys_page in page_set_flags
We do not require detection of overlapping TBs here,
so use the more appropriate function.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 8f39e01db9f82033543f707f7b06f81cb675ff67
https://github.com/qemu/qemu/commit/8f39e01db9f82033543f707f7b06f81cb675ff67
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/translate-all.c
M bsd-user/mmap.c
M linux-user/mmap.c
Log Message:
-----------
accel/tcg: Call tb_invalidate_phys_page for PAGE_RESET
When PAGE_RESET is set, we are replacing pages with new
content, which means that we need to invalidate existing
cached data, such as TranslationBlocks. Perform the
reset invalidate while we're doing other invalidates,
which allows us to remove the separate invalidates from
the user-only mmap/munmap/mprotect routines.
In addition, restrict invalidation to PAGE_EXEC pages.
Since cdf713085131, we have validated PAGE_EXEC is present
before translation, which means we can assume that if the
bit is not present, there are no translations to invalidate.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 43301e05669e19f41fb8530e77ac0c8953195bbf
https://github.com/qemu/qemu/commit/43301e05669e19f41fb8530e77ac0c8953195bbf
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/translate-all.c
Log Message:
-----------
accel/tcg: Use page_reset_target_data in page_set_flags
Use the existing function for clearing target data.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e786509f29c3b4ea7e295f79e8e73e7a3b2f2818
https://github.com/qemu/qemu/commit/e786509f29c3b4ea7e295f79e8e73e7a3b2f2818
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/translate-all.c
Log Message:
-----------
accel/tcg: Use tb_invalidate_phys_range in page_set_flags
Flush translation blocks in bulk, rather than page-by-page.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 0fe6108432ebbabbe12e53fba462770acb858a87
https://github.com/qemu/qemu/commit/0fe6108432ebbabbe12e53fba462770acb858a87
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/translate-all.c
M accel/tcg/user-exec.c
Log Message:
-----------
accel/tcg: Move TARGET_PAGE_DATA_SIZE impl to user-exec.c
Since "target data" is always user-only, move it out of
translate-all.c to user-exec.c.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 8269c01417a3e0bdb444b1bdac1d9b6c8bc9e667
https://github.com/qemu/qemu/commit/8269c01417a3e0bdb444b1bdac1d9b6c8bc9e667
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/user-exec.c
M include/exec/cpu-all.h
M target/arm/mte_helper.c
Log Message:
-----------
accel/tcg: Simplify page_get/alloc_target_data
Since the only user, Arm MTE, always requires allocation,
merge the get and alloc functions to always produce a
non-null result. Also assume that the user has already
checked page validity.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d29256896f563683419ae4af04d94d7d0f07c225
https://github.com/qemu/qemu/commit/d29256896f563683419ae4af04d94d7d0f07c225
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/translate-all.c
M include/exec/exec-all.h
M include/hw/core/tcg-cpu-ops.h
Log Message:
-----------
accel/tcg: Add restore_state_to_opc to TCGCPUOps
Add a tcg_ops hook to replace the restore_state_to_opc
function call. Because these generic hooks cannot depend
on target-specific types, temporarily, copy the current
target_ulong data[] into uint64_t d64[].
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c0cd068f32bb056d02c3ab0c62ebd08bbda83b84
https://github.com/qemu/qemu/commit/c0cd068f32bb056d02c3ab0c62ebd08bbda83b84
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/alpha/cpu.c
M target/alpha/translate.c
Log Message:
-----------
target/alpha: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 56c6c98df85cb03b1e72ef92111c4f9dde542d74
https://github.com/qemu/qemu/commit/56c6c98df85cb03b1e72ef92111c4f9dde542d74
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/arm/cpu.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f06c1ad4c62b8c91608c36cd3c870524979a278e
https://github.com/qemu/qemu/commit/f06c1ad4c62b8c91608c36cd3c870524979a278e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/avr/cpu.c
M target/avr/translate.c
Log Message:
-----------
target/avr: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4060474284cd6c7012c50dda743c6c151b92be87
https://github.com/qemu/qemu/commit/4060474284cd6c7012c50dda743c6c151b92be87
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/cris/cpu.c
M target/cris/translate.c
Log Message:
-----------
target/cris: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 9015781416012af1e44b4710a15a2bf1fe800bb5
https://github.com/qemu/qemu/commit/9015781416012af1e44b4710a15a2bf1fe800bb5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/hexagon/cpu.c
Log Message:
-----------
target/hexagon: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e9cc3aca111e286a444ac2d82ae92dceac7e6d7a
https://github.com/qemu/qemu/commit/e9cc3aca111e286a444ac2d82ae92dceac7e6d7a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/hppa/cpu.c
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 434382e640ba1b6fdd06f70e0fe70270bab9cce3
https://github.com/qemu/qemu/commit/434382e640ba1b6fdd06f70e0fe70270bab9cce3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/i386/tcg/tcg-cpu.c
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ab27940f8e6a0e092c72b0602c5a8cc379f26d99
https://github.com/qemu/qemu/commit/ab27940f8e6a0e092c72b0602c5a8cc379f26d99
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/loongarch/cpu.c
M target/loongarch/translate.c
Log Message:
-----------
target/loongarch: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 584fd3422f83350f93bd332bd6b10effaf150cf9
https://github.com/qemu/qemu/commit/584fd3422f83350f93bd332bd6b10effaf150cf9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/m68k/cpu.c
M target/m68k/translate.c
Log Message:
-----------
target/m68k: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 52b8d9a630c2e8f54b23857264365202aa760967
https://github.com/qemu/qemu/commit/52b8d9a630c2e8f54b23857264365202aa760967
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/microblaze/cpu.c
M target/microblaze/translate.c
Log Message:
-----------
target/microblaze: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3766855c9b729411ac898fe874cecf6f44a7eecf
https://github.com/qemu/qemu/commit/3766855c9b729411ac898fe874cecf6f44a7eecf
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/mips/cpu.c
M target/mips/tcg/tcg-internal.h
M target/mips/tcg/translate.c
Log Message:
-----------
target/mips: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: fbd5bd4ebcc8235475263a88e190444c264206b4
https://github.com/qemu/qemu/commit/fbd5bd4ebcc8235475263a88e190444c264206b4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/nios2/cpu.c
M target/nios2/translate.c
Log Message:
-----------
target/nios2: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3eb2c184bf900e17c1f8f0a09fba26e7c954cca0
https://github.com/qemu/qemu/commit/3eb2c184bf900e17c1f8f0a09fba26e7c954cca0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/openrisc/cpu.c
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 61bd1d29421ad0304fa7043a2e4968b652c4223f
https://github.com/qemu/qemu/commit/61bd1d29421ad0304fa7043a2e4968b652c4223f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ad1e84f5046c3dded43e0b056095938ce127a758
https://github.com/qemu/qemu/commit/ad1e84f5046c3dded43e0b056095938ce127a758
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 5439d7a68ce3449d4091e0b4c084579b9467a683
https://github.com/qemu/qemu/commit/5439d7a68ce3449d4091e0b4c084579b9467a683
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/rx/cpu.c
M target/rx/translate.c
Log Message:
-----------
target/rx: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3479783b3960a76c04aa76fce7869f94e864e6b0
https://github.com/qemu/qemu/commit/3479783b3960a76c04aa76fce7869f94e864e6b0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/s390x/cpu.c
M target/s390x/s390x-internal.h
M target/s390x/tcg/translate.c
Log Message:
-----------
target/s390x: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e7977326cd6648183ececce211c6330d4b9465df
https://github.com/qemu/qemu/commit/e7977326cd6648183ececce211c6330d4b9465df
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/sh4/cpu.c
M target/sh4/translate.c
Log Message:
-----------
target/sh4: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f36aaa53c66c613228c1a9f517cb357160049b25
https://github.com/qemu/qemu/commit/f36aaa53c66c613228c1a9f517cb357160049b25
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/sparc/cpu.c
M target/sparc/cpu.h
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b765e427b0050c497bd0393ef1f0cbd223bd90ba
https://github.com/qemu/qemu/commit/b765e427b0050c497bd0393ef1f0cbd223bd90ba
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/tricore/cpu.c
M target/tricore/translate.c
Log Message:
-----------
target/tricore: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 044dcfc5aab2f2679148c9eca41441dd6cf276a0
https://github.com/qemu/qemu/commit/044dcfc5aab2f2679148c9eca41441dd6cf276a0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/xtensa/cpu.c
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 04f105758b0089f73ee47260671580cde35f96cc
https://github.com/qemu/qemu/commit/04f105758b0089f73ee47260671580cde35f96cc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/translate-all.c
M include/exec/exec-all.h
Log Message:
-----------
accel/tcg: Remove restore_state_to_opc function
All targets have been updated. Use the tcg_ops target hook
exclusively, which allows the compat code to be removed.
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ad3b2e693daac6ed92db7361236028851d37c77c
https://github.com/qemu/qemu/commit/ad3b2e693daac6ed92db7361236028851d37c77c
Author: Janosch Frank <frankja@linux.ibm.com>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M target/s390x/kvm/kvm.c
M target/s390x/kvm/kvm_s390x.h
M target/s390x/kvm/meson.build
A target/s390x/kvm/stubs.c
Log Message:
-----------
s390x: Add protected dump cap
Add a protected dump capability for later feature checking.
Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Steffen Eiden <seiden@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Janis Schoetterl-Glausch <scgl@linux.ibm.com>
Message-Id: <20221017083822.43118-7-frankja@linux.ibm.com>
[ Marc-André - Add missing stubs when !kvm ]
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Commit: 03d83ecfae46bf5e0074cb5808043b30df34064b
https://github.com/qemu/qemu/commit/03d83ecfae46bf5e0074cb5808043b30df34064b
Author: Janosch Frank <frankja@linux.ibm.com>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M hw/s390x/pv.c
M hw/s390x/s390-virtio-ccw.c
M include/hw/s390x/pv.h
Log Message:
-----------
s390x: Introduce PV query interface
Introduce an interface over which we can get information about UV data.
Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Steffen Eiden <seiden@linux.ibm.com>
Reviewed-by: Janis Schoetterl-Glausch <scgl@linux.ibm.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20221017083822.43118-8-frankja@linux.ibm.com>
Commit: 5433669c7a1884cc0394c360148965edf7519884
https://github.com/qemu/qemu/commit/5433669c7a1884cc0394c360148965edf7519884
Author: Janosch Frank <frankja@linux.ibm.com>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M include/elf.h
Log Message:
-----------
include/elf.h: add s390x note types
Adding two s390x note types
Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20221017083822.43118-9-frankja@linux.ibm.com>
Commit: 753ca06f4706cd6e57750a606afb08c5c5299643
https://github.com/qemu/qemu/commit/753ca06f4706cd6e57750a606afb08c5c5299643
Author: Janosch Frank <frankja@linux.ibm.com>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M hw/s390x/pv.c
M include/hw/s390x/pv.h
Log Message:
-----------
s390x: Add KVM PV dump interface
Let's add a few bits of code which hide the new KVM PV dump API from
us via new functions.
Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Janis Schoetterl-Glausch <scgl@linux.ibm.com>
Reviewed-by: Steffen Eiden <seiden@linux.ibm.com>
[ Marc-André: fix up for compilation issue ]
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20221017083822.43118-10-frankja@linux.ibm.com>
Commit: 113d8f4e95cf0450bea421263de6ec016c779ad0
https://github.com/qemu/qemu/commit/113d8f4e95cf0450bea421263de6ec016c779ad0
Author: Janosch Frank <frankja@linux.ibm.com>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M dump/dump.c
M include/sysemu/dump.h
M target/s390x/arch_dump.c
Log Message:
-----------
s390x: pv: Add dump support
Sometimes dumping a guest from the outside is the only way to get the
data that is needed. This can be the case if a dumping mechanism like
KDUMP hasn't been configured or data needs to be fetched at a specific
point. Dumping a protected guest from the outside without help from
fw/hw doesn't yield sufficient data to be useful. Hence we now
introduce PV dump support.
The PV dump support works by integrating the firmware into the dump
process. New Ultravisor calls are used to initiate the dump process,
dump cpu data, dump memory state and lastly complete the dump process.
The UV calls are exposed by KVM via the new KVM_PV_DUMP command and
its subcommands. The guest's data is fully encrypted and can only be
decrypted by the entity that owns the customer communication key for
the dumped guest. Also dumping needs to be allowed via a flag in the
SE header.
On the QEMU side of things we store the PV dump data in the newly
introduced architecture ELF sections (storage state and completion
data) and the cpu notes (for cpu dump data).
Users can use the zgetdump tool to convert the encrypted QEMU dump to an
unencrypted one.
Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Steffen Eiden <seiden@linux.ibm.com>
Message-Id: <20221017083822.43118-11-frankja@linux.ibm.com>
Commit: e38c24cb580735883769558801d9e2f2ba9f04c1
https://github.com/qemu/qemu/commit/e38c24cb580735883769558801d9e2f2ba9f04c1
Author: Viktor Prutyanov <viktor.prutyanov@redhat.com>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M dump/win_dump.c
Log Message:
-----------
dump/win_dump: limit number of processed PRCBs
When number of CPUs utilized by guest Windows is less than defined in
QEMU (i.e., desktop versions of Windows severely limits number of CPU
sockets), patch_and_save_context routine accesses non-existent PRCB and
fails. So, limit number of processed PRCBs by NumberProcessors taken
from guest Windows driver.
Signed-off-by: Viktor Prutyanov <viktor.prutyanov@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20221019235948.656411-1-viktor.prutyanov@redhat.com>
Commit: 7c02614ec97f02aef888c1ecdcfbf396035d4871
https://github.com/qemu/qemu/commit/7c02614ec97f02aef888c1ecdcfbf396035d4871
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M MAINTAINERS
M hw/arm/aspeed.c
M hw/arm/aspeed_ast2600.c
M hw/block/m25p80.c
A hw/block/m25p80_sfdp.c
A hw/block/m25p80_sfdp.h
M hw/block/meson.build
M hw/block/trace-events
M hw/i2c/aspeed_i2c.c
M hw/ssi/aspeed_smc.c
M hw/ssi/ssi.c
M include/hw/i2c/aspeed_i2c.h
M include/hw/ssi/aspeed_smc.h
M include/hw/ssi/ssi.h
M tests/avocado/machine_aspeed.py
Log Message:
-----------
Merge tag 'pull-aspeed-20221025' of https://github.com/legoater/qemu into
staging
aspeed queue :
* Performance improvement with Object class caching
* Serial Flash Discovery Parameters support for m25p80 device
* Various small adjustments on intructions and models
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# kmQK3MFfJPkTu0ddu1cWhCIgTO7EuLuZL7gzj1oxoeXiU3YcVh8=
# =u7pS
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 25 Oct 2022 11:14:41 EDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20221025' of https://github.com/legoater/qemu:
arm/aspeed: Replace mx25l25635e chip model
m25p80: Add the w25q01jvq SFPD table
m25p80: Add the w25q512jv SFPD table
m25p80: Add the w25q256 SFPD table
m25p80: Add the mx66l1g45g SFDP table
m25p80: Add the mx25l25635f SFPD table
m25p80: Add the mx25l25635e SFPD table
m25p80: Add erase size for mx25l25635e
m25p80: Add the n25q256a SFDP table
m25p80: Add basic support for the SFDP command
hw/arm/aspeed: increase Bletchley memory size
ast2600: Drop NEON from the CPU features
aspeed/smc: Cache AspeedSMCClass
ssi: cache SSIPeripheralClass to avoid GET_CLASS()
tests/avocado/machine_aspeed.py: Fix typos on buildroot
hw/i2c/aspeed: Fix old reg slave receive
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: cf8c4e597c198bd61aef0c7a1b6c08407b1f5c39
https://github.com/qemu/qemu/commit/cf8c4e597c198bd61aef0c7a1b6c08407b1f5c39
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M docs/devel/reset.rst
M docs/system/arm/emulation.rst
M hw/arm/aspeed.c
M hw/arm/boot.c
M hw/arm/mps2-tz.c
M hw/arm/virt.c
M hw/core/reset.c
M hw/core/resettable.c
M hw/hppa/machine.c
M hw/hyperv/hyperv.c
M hw/i386/microvm.c
M hw/i386/pc.c
M hw/i386/x86.c
M hw/m68k/q800.c
M hw/m68k/virt.c
M hw/mips/boston.c
M hw/openrisc/boot.c
M hw/ppc/pegasos2.c
M hw/ppc/pnv.c
M hw/ppc/spapr.c
M hw/riscv/boot.c
M hw/rx/rx-gdbsim.c
M hw/s390x/s390-virtio-ccw.c
M hw/timer/imx_epit.c
M include/hw/boards.h
M include/sysemu/device_tree.h
M include/sysemu/reset.h
M migration/savevm.c
M qapi/run-state.json
M softmmu/device_tree.c
M softmmu/runstate.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/ptw.c
Log Message:
-----------
Merge tag 'pull-target-arm-20221025' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Implement FEAT_E0PD
* Implement FEAT_HAFDBS
* honor HCR_E2H and HCR_TGE in arm_excp_unmasked()
* hw/arm/virt: Fix devicetree warnings about the virtio-iommu node
* hw/core/resettable: fix reset level counting
* hw/hyperv/hyperv.c: Use device_cold_reset() instead of device_legacy_reset()
* imx: reload cmp timer outside of the reload ptimer transaction
* x86: do not re-randomize RNG seed on snapshot load
* m68k/virt: do not re-randomize RNG seed on snapshot load
* m68k/q800: do not re-randomize RNG seed on snapshot load
* arm: re-randomize rng-seed on reboot
* riscv: re-randomize rng-seed on reboot
* mips/boston: re-randomize rng-seed on reboot
* openrisc: re-randomize rng-seed on reboot
* rx: re-randomize rng-seed on reboot
# -----BEGIN PGP SIGNATURE-----
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# /PId4qodO4ZwFdLI1lKFLg==
# =Dqmm
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 25 Oct 2022 12:36:13 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20221025' of
https://git.linaro.org/people/pmaydell/qemu-arm: (30 commits)
rx: re-randomize rng-seed on reboot
openrisc: re-randomize rng-seed on reboot
mips/boston: re-randomize rng-seed on reboot
m68k/q800: do not re-randomize RNG seed on snapshot load
m68k/virt: do not re-randomize RNG seed on snapshot load
riscv: re-randomize rng-seed on reboot
arm: re-randomize rng-seed on reboot
x86: do not re-randomize RNG seed on snapshot load
device-tree: add re-randomization helper function
reset: allow registering handlers that aren't called by snapshot loading
target/arm: Use the max page size in a 2-stage ptw
target/arm: Implement FEAT_HAFDBS, dirty bit portion
target/arm: Implement FEAT_HAFDBS, access flag portion
target/arm: Tidy merging of attributes from descriptor and table
target/arm: Consider GP an attribute in get_phys_addr_lpae
target/arm: Don't shift attrs in get_phys_addr_lpae
target/arm: Fix fault reporting in get_phys_addr_lpae
target/arm: Remove loop from get_phys_addr_lpae
target/arm: Add ARMFault_UnsuppAtomicUpdate
target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 87f6a13a05053aaeeafe3c33697d6e31647cfc16
https://github.com/qemu/qemu/commit/87f6a13a05053aaeeafe3c33697d6e31647cfc16
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/internal.h
M accel/tcg/meson.build
A accel/tcg/tb-maint.c
M accel/tcg/tcg-accel-ops-mttcg.c
M accel/tcg/tcg-accel-ops-rr.c
M accel/tcg/translate-all.c
M accel/tcg/translator.c
M accel/tcg/user-exec.c
M bsd-user/mmap.c
M cpu.c
M include/exec/cpu-all.h
M include/exec/exec-all.h
M include/exec/ram_addr.h
M include/exec/translate-all.h
M include/hw/core/tcg-cpu-ops.h
M include/qemu/atomic.h
M include/qemu/osdep.h
M include/qemu/thread.h
M linux-user/mmap.c
M target/alpha/cpu.c
M target/alpha/translate.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/internals.h
M target/arm/mte_helper.c
M target/arm/translate.c
M target/avr/cpu.c
M target/avr/translate.c
M target/cris/cpu.c
M target/cris/translate.c
M target/hexagon/cpu.c
M target/hppa/cpu.c
M target/hppa/translate.c
M target/i386/tcg/tcg-cpu.c
M target/i386/tcg/translate.c
M target/loongarch/cpu.c
M target/loongarch/translate.c
M target/m68k/cpu.c
M target/m68k/translate.c
M target/microblaze/cpu.c
M target/microblaze/translate.c
M target/mips/cpu.c
M target/mips/tcg/tcg-internal.h
M target/mips/tcg/translate.c
M target/nios2/cpu.c
M target/nios2/translate.c
M target/openrisc/cpu.c
M target/openrisc/translate.c
M target/ppc/cpu_init.c
M target/ppc/translate.c
M target/riscv/cpu.c
M target/rx/cpu.c
M target/rx/translate.c
M target/s390x/cpu.c
M target/s390x/s390x-internal.h
M target/s390x/tcg/translate.c
M target/sh4/cpu.c
M target/sh4/translate.c
M target/sparc/cpu.c
M target/sparc/cpu.h
M target/sparc/translate.c
M target/tricore/cpu.c
M target/tricore/translate.c
M target/xtensa/cpu.c
M target/xtensa/translate.c
M tcg/aarch64/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/loongarch64/tcg-target.h
Log Message:
-----------
Merge tag 'pull-tcg-20221026' of https://gitlab.com/rth7680/qemu into staging
Revert incorrect cflags initialization.
Add direct jumps for tcg/loongarch64.
Speed up breakpoint check.
Improve assertions for atomic.h.
Move restore_state_to_opc to TCGCPUOps.
Cleanups to TranslationBlock maintenance.
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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 25 Oct 2022 22:08:14 EDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20221026' of https://gitlab.com/rth7680/qemu: (47 commits)
accel/tcg: Remove restore_state_to_opc function
target/xtensa: Convert to tcg_ops restore_state_to_opc
target/tricore: Convert to tcg_ops restore_state_to_opc
target/sparc: Convert to tcg_ops restore_state_to_opc
target/sh4: Convert to tcg_ops restore_state_to_opc
target/s390x: Convert to tcg_ops restore_state_to_opc
target/rx: Convert to tcg_ops restore_state_to_opc
target/riscv: Convert to tcg_ops restore_state_to_opc
target/ppc: Convert to tcg_ops restore_state_to_opc
target/openrisc: Convert to tcg_ops restore_state_to_opc
target/nios2: Convert to tcg_ops restore_state_to_opc
target/mips: Convert to tcg_ops restore_state_to_opc
target/microblaze: Convert to tcg_ops restore_state_to_opc
target/m68k: Convert to tcg_ops restore_state_to_opc
target/loongarch: Convert to tcg_ops restore_state_to_opc
target/i386: Convert to tcg_ops restore_state_to_opc
target/hppa: Convert to tcg_ops restore_state_to_opc
target/hexagon: Convert to tcg_ops restore_state_to_opc
target/cris: Convert to tcg_ops restore_state_to_opc
target/avr: Convert to tcg_ops restore_state_to_opc
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: f8536f836c3f1eda6ae0286de6feb08fc72cee0f
https://github.com/qemu/qemu/commit/f8536f836c3f1eda6ae0286de6feb08fc72cee0f
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-10-26 (Wed, 26 Oct 2022)
Changed paths:
M dump/dump.c
M dump/win_dump.c
M hw/s390x/pv.c
M hw/s390x/s390-virtio-ccw.c
M include/elf.h
M include/hw/s390x/pv.h
M include/sysemu/dump-arch.h
M include/sysemu/dump.h
M target/s390x/arch_dump.c
M target/s390x/kvm/kvm.c
M target/s390x/kvm/kvm_s390x.h
M target/s390x/kvm/meson.build
A target/s390x/kvm/stubs.c
Log Message:
-----------
Merge tag 'dump-pull-request' of https://gitlab.com/marcandre.lureau/qemu
into staging
dump queue
Hi
The "dump" queue, with:
- [PATCH v3/v4 0/9] dump: Cleanup and consolidation
- [PATCH v4 0/4] dump: add 32-bit guest Windows support
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# gpg: Signature made Wed 26 Oct 2022 04:55:31 EDT
# gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5
# gpg: issuer "marcandre.lureau@redhat.com"
# gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>"
[full]
# gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>"
[full]
# Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5
* tag 'dump-pull-request' of https://gitlab.com/marcandre.lureau/qemu:
dump/win_dump: limit number of processed PRCBs
s390x: pv: Add dump support
s390x: Add KVM PV dump interface
include/elf.h: add s390x note types
s390x: Introduce PV query interface
s390x: Add protected dump cap
dump: Add architecture section and section string table support
dump: Reintroduce memory_offset and section_offset
dump: Reorder struct DumpState
dump: Write ELF section headers right after ELF header
dump: Use a buffer for ELF section data and headers
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/79fc2fb685f3...f8536f836c3f
- [Qemu-commits] [qemu/qemu] 3648d3: hw/i2c/aspeed: Fix old reg slave receive,
Paolo Bonzini <=