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[Qemu-commits] [qemu/qemu] 31cb76: hw/char/pl011: fix baud rate calculat
From: |
Paolo Bonzini |
Subject: |
[Qemu-commits] [qemu/qemu] 31cb76: hw/char/pl011: fix baud rate calculation |
Date: |
Thu, 20 Oct 2022 11:36:52 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 31cb769c317e0623cbe2a3e8da437b6cd7ddef9b
https://github.com/qemu/qemu/commit/31cb769c317e0623cbe2a3e8da437b6cd7ddef9b
Author: Baruch Siach <baruch@tkos.co.il>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M hw/char/pl011.c
Log Message:
-----------
hw/char/pl011: fix baud rate calculation
The PL011 TRM says that "UARTIBRD = 0 is invalid and UARTFBRD is ignored
when this is the case". But the code looks at FBRD for the invalid case.
Fix this.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Message-id:
1408f62a2e45665816527d4845ffde650957d5ab.1665051588.git.baruchs-c@neureality.ai
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 947692e708bc61ca724429b5198f0b0f5f68102d
https://github.com/qemu/qemu/commit/947692e708bc61ca724429b5198f0b0f5f68102d
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: update the cortex-a15 MIDR to latest rev
QEMU doesn't model micro-architectural details which includes most
chip errata. The ARM_ERRATA_798181 work around in the Linux
kernel (see erratum_a15_798181_init) currently detects QEMU's
cortex-a15 as broken and triggers additional expensive TLB flushes as
a result.
Change the MIDR to report what the latest silicon would (r4p0). We
explicitly set the IMPDEF revidr bits to 0 because we don't need to
set anything other than the silicon revision to indicate these flushes
are not needed. This cuts about 5s from my Debian kernel boot with the
latest 6.0rc1 kernel (29s->24s).
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Anders Roxell <anders.roxell@linaro.org>
Message-id: 20221010153225.506394-1-alex.bennee@linaro.org
Cc: Arnd Bergmann <arnd@linaro.org>
Cc: Anders Roxell <anders.roxell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Anders Roxell <anders.roxell@linaro.org>
Message-Id: <20220906172257.2776521-1-alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 24d18d5d7e31462b7bd5bb2c6ee19856699e34ed
https://github.com/qemu/qemu/commit/24d18d5d7e31462b7bd5bb2c6ee19856699e34ed
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/cpu-param.h
M target/arm/tlb_helper.c
Log Message:
-----------
target/arm: Enable TARGET_PAGE_ENTRY_EXTRA
Copy attrs and shareability, into the TLB. This will eventually
be used by S1_ptw_translate to report stage1 translation failures,
and by do_ats_write to fill in PAR_EL1.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b8967ddf393aaf35fdbc07b4cb538a40f8b6fe37
https://github.com/qemu/qemu/commit/b8967ddf393aaf35fdbc07b4cb538a40f8b6fe37
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/cpu.h
M target/arm/mte_helper.c
M target/arm/sve_helper.c
M target/arm/sve_ldst_internal.h
M target/arm/tlb_helper.c
Log Message:
-----------
target/arm: Use probe_access_full for MTE
The CPUTLBEntryFull structure now stores the original pte attributes, as
well as the physical address. Therefore, we no longer need a separate
bit in MemTxAttrs, nor do we need to walk the tree of memory regions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 937f2245596de9026ca8ae017ef47889523c4326
https://github.com/qemu/qemu/commit/937f2245596de9026ca8ae017ef47889523c4326
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/cpu-param.h
M target/arm/cpu.h
M target/arm/internals.h
M target/arm/ptw.c
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use probe_access_full for BTI
Add a field to TARGET_PAGE_ENTRY_EXTRA to hold the guarded bit.
In is_guarded_page, use probe_access_full instead of just guessing
that the tlb entry is still present. Also handles the FIXME about
executing from device memory.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a1ce3084c572e39d588a7978002d83fee01edd60
https://github.com/qemu/qemu/commit/a1ce3084c572e39d588a7978002d83fee01edd60
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/cpu-param.h
M target/arm/cpu.h
M target/arm/ptw.c
Log Message:
-----------
target/arm: Add ARMMMUIdx_Phys_{S,NS}
Not yet used, but add mmu indexes for 1-1 mapping
to physical addresses.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 575a94af3c113157cf749364a921336ddd346e9a
https://github.com/qemu/qemu/commit/575a94af3c113157cf749364a921336ddd346e9a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/cpu-param.h
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx
We had been marking this ARM_MMU_IDX_NOTLB, move it to a real tlb.
Flush the tlb when invalidating stage 1+2 translations. Re-use
alle1_tlbmask() for other instances of EL1&0 + Stage2.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221011031911.2408754-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 00b20ee42ea97f2329779851a7f8a290712109ee
https://github.com/qemu/qemu/commit/00b20ee42ea97f2329779851a7f8a290712109ee
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Restrict tlb flush from vttbr_write to vmid change
Compare only the VMID field when considering whether we need to flush.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221011031911.2408754-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6d2654ffacea813916176c5df27958098b20af6a
https://github.com/qemu/qemu/commit/6d2654ffacea813916176c5df27958098b20af6a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Split out S1Translate type
Consolidate most of the inputs and outputs of S1_ptw_translate
into a single structure. Plumb this through arm_ld*_ptw from
the controlling get_phys_addr_* routine.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221011031911.2408754-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4a35855682cebb89f9630b07aa9fd37c4e8c733b
https://github.com/qemu/qemu/commit/4a35855682cebb89f9630b07aa9fd37c4e8c733b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Plumb debug into S1Translate
Before using softmmu page tables for the ptw, plumb down
a debug parameter so that we can query page table entries
from gdbstub without modifying cpu state.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4e7a2c9860eabd21376da522ef11e6b39fe36f85
https://github.com/qemu/qemu/commit/4e7a2c9860eabd21376da522ef11e6b39fe36f85
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Move be test for regime into S1TranslateResult
Hoist this test out of arm_ld[lq]_ptw into S1_ptw_translate.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f3639a64f602ea5c1436eb9c9b89f42028e3a4a8
https://github.com/qemu/qemu/commit/f3639a64f602ea5c1436eb9c9b89f42028e3a4a8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/cpu.h
M target/arm/ptw.c
M target/arm/tlb_helper.c
Log Message:
-----------
target/arm: Use softmmu tlbs for page table walking
So far, limit the change to S1_ptw_translate, arm_ldl_ptw, and
arm_ldq_ptw. Use probe_access_full to find the host address,
and if so use a host load. If the probe fails, we've got our
fault info already. On the off chance that page tables are not
in RAM, continue to use the address_space_ld* functions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3f5a74c543b491556b4a0020b1683b16659b178f
https://github.com/qemu/qemu/commit/3f5a74c543b491556b4a0020b1683b16659b178f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Split out get_phys_addr_twostage
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6b72c5424a4a725bc0bacd09bd83f7e8be649345
https://github.com/qemu/qemu/commit/6b72c5424a4a725bc0bacd09bd83f7e8be649345
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Use bool consistently for get_phys_addr subroutines
The return type of the functions is already bool, but in a few
instances we used an integer type with the return statement.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221011031911.2408754-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8df87279739a30c2f70832f880fd03cb65950775
https://github.com/qemu/qemu/commit/8df87279739a30c2f70832f880fd03cb65950775
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/translate-vfp.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Introduce curr_insn_len
A simple helper to retrieve the length of the current insn.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 168122419ed1c4087748e21131a523c6d9b632e1
https://github.com/qemu/qemu/commit/168122419ed1c4087748e21131a523c6d9b632e1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/translate-a64.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Change gen_goto_tb to work on displacements
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c44c8b8b99959068801726be97b6a444ee2989bc
https://github.com/qemu/qemu/commit/c44c8b8b99959068801726be97b6a444ee2989bc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/translate-a32.h
M target/arm/translate-a64.c
M target/arm/translate-vfp.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Change gen_*set_pc_im to gen_*update_pc
In preparation for TARGET_TB_PCREL, reduce reliance on
absolute values by passing in pc difference.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 55086e628ffcb35c71317b310d9caf6f718ae870
https://github.com/qemu/qemu/commit/55086e628ffcb35c71317b310d9caf6f718ae870
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/translate-a64.c
M target/arm/translate-m-nocp.c
M target/arm/translate-mve.c
M target/arm/translate-vfp.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Change gen_exception_insn* to work on displacements
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b4f8d987f6a9ff2733bcd6e5fa78f6582dc84771
https://github.com/qemu/qemu/commit/b4f8d987f6a9ff2733bcd6e5fa78f6582dc84771
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/translate-a64.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Remove gen_exception_internal_insn pc argument
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Since we always pass dc->pc_curr, fold the arithmetic to zero displacement.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: bb0356170a60ce31d992ad273bdede2075724a29
https://github.com/qemu/qemu/commit/bb0356170a60ce31d992ad273bdede2075724a29
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Change gen_jmp* to work on displacements
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 19f6b76baa10b96d37d545897c94f8738393481e
https://github.com/qemu/qemu/commit/19f6b76baa10b96d37d545897c94f8738393481e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Introduce gen_pc_plus_diff for aarch64
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 35dbeb81778d5c772e7ce42ea06429c419e707f1
https://github.com/qemu/qemu/commit/35dbeb81778d5c772e7ce42ea06429c419e707f1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Introduce gen_pc_plus_diff for aarch32
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: abb80995d722814c2e3f314629ef4c5700424ae7
https://github.com/qemu/qemu/commit/abb80995d722814c2e3f314629ef4c5700424ae7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M target/arm/cpu-param.h
M target/arm/cpu.c
M target/arm/translate-a64.c
M target/arm/translate-m-nocp.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Enable TARGET_TB_PCREL
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221020030641.2066807-10-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5db899303799e49209016a93289b8694afa1449e
https://github.com/qemu/qemu/commit/5db899303799e49209016a93289b8694afa1449e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M hw/ide/microdrive.c
Log Message:
-----------
hw/ide/microdrive: Use device_cold_reset() for self-resets
Currently the microdrive code uses device_legacy_reset() to reset
itself, and has its reset method call reset on the IDE bus as the
last thing it does. Switch to using device_cold_reset().
The only concrete microdrive device is the TYPE_DSCM1XXXX; it is not
command-line pluggable, so it is used only by the old pxa2xx Arm
boards 'akita', 'borzoi', 'spitz', 'terrier' and 'tosa'.
You might think that this would result in the IDE bus being
reset automatically, but it does not, because the IDEBus type
does not set the BusClass::reset method. Instead the controller
must explicitly call ide_bus_reset(). We therefore leave that
call in md_reset().
Note also that because the PCMCIA card device is a direct subclass of
TYPE_DEVICE and we don't model the PCMCIA controller-to-card
interface as a qbus, PCMCIA cards are not on any qbus and so they
don't get reset when the system is reset. The reset only happens via
the dscm1xxxx_attach() and dscm1xxxx_detach() functions during
machine creation.
Because our aim here is merely to try to get rid of calls to the
device_legacy_reset() function, we leave these other dubious
reset-related issues alone. (They all stem from this code being
absolutely ancient.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221013174042.1602926-1-peter.maydell@linaro.org
Commit: 0529245488865038344d64fff7ee05864d3d17f6
https://github.com/qemu/qemu/commit/0529245488865038344d64fff7ee05864d3d17f6
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-10-20 (Thu, 20 Oct 2022)
Changed paths:
M hw/char/pl011.c
M hw/ide/microdrive.c
M target/arm/cpu-param.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu_tcg.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/mte_helper.c
M target/arm/ptw.c
M target/arm/sve_helper.c
M target/arm/sve_ldst_internal.h
M target/arm/tlb_helper.c
M target/arm/translate-a32.h
M target/arm/translate-a64.c
M target/arm/translate-m-nocp.c
M target/arm/translate-mve.c
M target/arm/translate-vfp.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
Merge tag 'pull-target-arm-20221020' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Switch to TARGET_TB_PCREL
* More pagetable-walk refactoring preparatory to HAFDBS
* update the cortex-a15 MIDR to latest rev
* hw/char/pl011: fix baud rate calculation
* hw/ide/microdrive: Use device_cold_reset() for self-resets
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# gpg: Signature made Thu 20 Oct 2022 08:20:30 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20221020' of
https://git.linaro.org/people/pmaydell/qemu-arm: (24 commits)
hw/ide/microdrive: Use device_cold_reset() for self-resets
target/arm: Enable TARGET_TB_PCREL
target/arm: Introduce gen_pc_plus_diff for aarch32
target/arm: Introduce gen_pc_plus_diff for aarch64
target/arm: Change gen_jmp* to work on displacements
target/arm: Remove gen_exception_internal_insn pc argument
target/arm: Change gen_exception_insn* to work on displacements
target/arm: Change gen_*set_pc_im to gen_*update_pc
target/arm: Change gen_goto_tb to work on displacements
target/arm: Introduce curr_insn_len
target/arm: Use bool consistently for get_phys_addr subroutines
target/arm: Split out get_phys_addr_twostage
target/arm: Use softmmu tlbs for page table walking
target/arm: Move be test for regime into S1TranslateResult
target/arm: Plumb debug into S1Translate
target/arm: Split out S1Translate type
target/arm: Restrict tlb flush from vttbr_write to vmid change
target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx
target/arm: Add ARMMMUIdx_Phys_{S,NS}
target/arm: Use probe_access_full for BTI
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/214a8da23651...052924548886
- [Qemu-commits] [qemu/qemu] 31cb76: hw/char/pl011: fix baud rate calculation,
Paolo Bonzini <=