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[Qemu-commits] [qemu/qemu] 8cc558: virtio-scsi: Send "REPORTED LUNS CHAN
From: |
Paolo Bonzini |
Subject: |
[Qemu-commits] [qemu/qemu] 8cc558: virtio-scsi: Send "REPORTED LUNS CHANGED" sense da... |
Date: |
Tue, 18 Oct 2022 13:01:23 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 8cc5583abe6419e7faaebc9fbd109f34f4c850f2
https://github.com/qemu/qemu/commit/8cc5583abe6419e7faaebc9fbd109f34f4c850f2
Author: Venu Busireddy <venu.busireddy@oracle.com>
Date: 2022-10-13 (Thu, 13 Oct 2022)
Changed paths:
M hw/scsi/scsi-bus.c
M hw/scsi/virtio-scsi.c
M include/hw/scsi/scsi.h
Log Message:
-----------
virtio-scsi: Send "REPORTED LUNS CHANGED" sense data upon disk hotplug events
Section 5.6.6.3 of VirtIO specification states, "Events will also
be reported via sense codes..." However, no sense data is sent when
VIRTIO_SCSI_EVT_RESET_RESCAN or VIRTIO_SCSI_EVT_RESET_REMOVED events
are reported (when disk hotplug/hotunplug events occur). SCSI layer
on Solaris depends on this sense data, and hence does not handle disk
hotplug/hotunplug events.
When the disk inventory changes, use the bus unit attention mechanism
to return a CHECK_CONDITION status with sense data of 0x06/0x3F/0x0E
(sense code REPORTED_LUNS_CHANGED). The first device on the bus to
execute a command successfully will report and consume the unit
attention status.
Signed-off-by: Venu Busireddy <venu.busireddy@oracle.com>
Message-Id: <20221006194946.24134-1-venu.busireddy@oracle.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: b0877575bd6cb0c2fd30c9d38a86826d61701c8f
https://github.com/qemu/qemu/commit/b0877575bd6cb0c2fd30c9d38a86826d61701c8f
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: step back from PPC
I am not active anymore on the PPC maintainership, degrade my self as
standard Reviewer. Also degrade PowerNV and XIVE status since I am not
funded for this work.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220929180946.848721-1-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 9364df267fed0ba079f1f679849b5808f146a257
https://github.com/qemu/qemu/commit/9364df267fed0ba079f1f679849b5808f146a257
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: restore powerpc_excp_booke doorbell interrupts
This partially reverts commit 9dc20cc37db9 ("target/ppc: Simplify
powerpc_excp_booke"), which removed DOORI and DOORCI interrupts.
Without this patch, a -cpu e5500 -smp 2 machine booting Linux
crashes with:
qemu: fatal: Invalid PowerPC exception 36. Aborting
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220924114436.1422786-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 1049ff55fe99df87dbec47db27749a88f494e846
https://github.com/qemu/qemu/commit/1049ff55fe99df87dbec47db27749a88f494e846
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/ppc440_bamboo.c
M hw/ppc/ppc4xx_devs.c
Log Message:
-----------
ppc440_bamboo: Remove unnecessary memsets
In ppc4xx_sdram_init() the struct is allocated with g_new0() so no
need to clear its elements. In the bamboo machine init memset can be
replaced with array initialiser which is shorter.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id:
<529adc7705fb3e3e777439895bdaa136bacb9403.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 8626982301dc8dbbe49e0fb1730461955df879c8
https://github.com/qemu/qemu/commit/8626982301dc8dbbe49e0fb1730461955df879c8
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/ppc440_uc.c
M hw/ppc/ppc4xx_devs.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc4xx: Introduce Ppc4xxSdramBank struct
Instead of storing sdram bank parameters in unrelated arrays put them
in a struct so it's clear they belong to the same bank and simplify
the state struct using this bank type.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<5eb82d0424c584b2b9e6f7bc51560f8189ed21bb.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 68b9a2e38d7183f64dddc5faec9a16c70a4f095c
https://github.com/qemu/qemu/commit/68b9a2e38d7183f64dddc5faec9a16c70a4f095c
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
M hw/ppc/ppc440_bamboo.c
M hw/ppc/ppc4xx_devs.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc4xx_sdram: Get rid of the init RAM hack
The do_init parameter of ppc4xx_sdram_init() is used to map memory
regions that is normally done by the firmware by programming the SDRAM
controller. Do this from board code emulating what firmware would do
when booting a kernel directly from -kernel without a firmware so we
can get rid of this do_init hack.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id:
<d6c44c870befa1a075e21f1a59926dcdaff63f6b.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 734c44ea13272c3b3d5cd9345cc4df7ce9bd30b3
https://github.com/qemu/qemu/commit/734c44ea13272c3b3d5cd9345cc4df7ce9bd30b3
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_uc.c
M hw/ppc/ppc440.h
M hw/ppc/ppc440_bamboo.c
M hw/ppc/ppc440_uc.c
M hw/ppc/ppc4xx_devs.c
M hw/ppc/sam460ex.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks()
Change ppc4xx_sdram_banks() to take one Ppc4xxSdramBank array instead
of the separate arrays and adjust ppc4xx_sdram_init() and
ppc440_sdram_init() accordingly as well as machines using these.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id:
<e3a1fea51f29779fd6a61be90a29c684f3299544.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 2cdfa6ef5ca56227372c7d0c0cd0f6a631842c04
https://github.com/qemu/qemu/commit/2cdfa6ef5ca56227372c7d0c0cd0f6a631842c04
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/ppc440_bamboo.c
Log Message:
-----------
ppc440_bamboo: Add missing 4 MiB valid memory size
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id:
<05836e38be84729c1c6b5b609e7aa2ea60435033.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 0aedcc8a8db88967d3abbff433bdd1f5a4b9ce6d
https://github.com/qemu/qemu/commit/0aedcc8a8db88967d3abbff433bdd1f5a4b9ce6d
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
M hw/ppc/ppc440_bamboo.c
M hw/ppc/ppc4xx_devs.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc4xx_sdram: Move size check to ppc4xx_sdram_init()
Instead of checking if memory size is valid in board code move this
check to ppc4xx_sdram_init() as this is a restriction imposed by the
SDRAM controller.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<39e5129dd095b285676a6267c5753786da1bc30d.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 4fc30e153a0fbb11bd6826cf67d52b1d9122bac3
https://github.com/qemu/qemu/commit/4fc30e153a0fbb11bd6826cf67d52b1d9122bac3
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
M hw/ppc/ppc440_bamboo.c
M hw/ppc/ppc4xx_devs.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc4xx_sdram: QOM'ify
Change the ppc4xx_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr. This is mostly
modelling the DDR SDRAM controller found in the 440EP (used on the
bamboo board) but also backward compatible with the older DDR
controllers on some 405 SoCs so we also use it for those now. This
likely does not cause problems for guests we run as the new features
are just not accessed but to model 405 SoC accurately some features
may have to be disabled or the model split between 440 and older.
Newer SoCs (regardless of their PPC core, e.g. 405EX) may have an
updated DDR2 SDRAM controller implemented by the ppc440_sdram model
(only partially, enough for the 460EX on the sam460ex) that is not yet
QOM'ified in this patch. That is intended to become ppc4xx-sdram-ddr2
when QOM'ified later.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id:
<8f820487fc9011343032c422ecdf3e8ee74d8c11.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 052ae5dcc0f5bb5a6644236a91064d0548b703f1
https://github.com/qemu/qemu/commit/052ae5dcc0f5bb5a6644236a91064d0548b703f1
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/ppc4xx_devs.c
Log Message:
-----------
ppc4xx_sdram: Drop extra zeros for readability
Constants that are written zero padded for no good reason are hard to
read, it's easier to see what is meant if it's just 0 or 1 instead.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<93974622c3d398c7d3a3488b678b74c3807849de.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 17221012b19a2100335bb7993befd9b38f944f3f
https://github.com/qemu/qemu/commit/17221012b19a2100335bb7993befd9b38f944f3f
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/ppc440_uc.c
Log Message:
-----------
ppc440_sdram: Split off map/unmap of sdram banks for later reuse
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<23560b6a71682d513f3dd8e9ed3852f51d5eb309.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: ea74acee988e5849ec5b7aa89edc3e676b66d2c4
https://github.com/qemu/qemu/commit/ea74acee988e5849ec5b7aa89edc3e676b66d2c4
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/ppc440_uc.c
Log Message:
-----------
ppc440_sdram: Implement enable bit in the DDR2 SDRAM controller
To allow removing the do_init hack we need to improve the DDR2 SDRAM
controller model to handle the enable/disable bit that it ignored so
far.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id:
<f8900aadb1a4426a6444741e6876c898b3b77f7b.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 03f7041bfdc45f6c981a83fd2d932bad161769ad
https://github.com/qemu/qemu/commit/03f7041bfdc45f6c981a83fd2d932bad161769ad
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/ppc440.h
M hw/ppc/ppc440_uc.c
M hw/ppc/sam460ex.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc440_sdram: Get rid of the init RAM hack
Remove the do_init parameter of ppc440_sdram_init and enable SDRAM
controller from the board. Firmware does this so it may only be needed
when booting with -kernel without firmware but we enable SDRAM
unconditionally to preserve previous behaviour.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id:
<c2eda8f83c82f655aa7821a5a8c9310484bd6a1d.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 3db19f124a14e8029d693dc10e031f3611a119bb
https://github.com/qemu/qemu/commit/3db19f124a14e8029d693dc10e031f3611a119bb
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/ppc440_uc.c
Log Message:
-----------
ppc440_sdram: Rename local variable for readability
Rename local sdram variable in ppc440_sdram_init to s for readability.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id:
<7351b80fa321c32a6229e685dfdc940232f8b788.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 1e545fbc88bb5abe21553972a2244f272153476d
https://github.com/qemu/qemu/commit/1e545fbc88bb5abe21553972a2244f272153476d
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc440_bamboo.c
M hw/ppc/ppc440_uc.c
M hw/ppc/ppc4xx_devs.c
M hw/ppc/sam460ex.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc4xx_sdram: Rename functions to prevent name clashes
Rename functions to avoid name clashes when moving the DDR2 controller
model currently called ppc440_sdram to ppc4xx_devs. This also more
clearly shows which function belongs to which model.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<9c09d10fbf36940ebbe30d7038d69cf3f2e58371.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: ef10aebb9a71f0c60f0b7aae808498333bb7bfd9
https://github.com/qemu/qemu/commit/ef10aebb9a71f0c60f0b7aae808498333bb7bfd9
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/ppc440.h
M hw/ppc/ppc440_uc.c
M hw/ppc/sam460ex.c
Log Message:
-----------
ppc440_sdram: Move RAM size check to ppc440_sdram_init
Move the check for valid memory sizes from board to sdram controller
init. This adds the missing valid memory sizes of 16 and 8 MiB to the
DoC and the board now only checks for additional restrictions imposed
by its firmware then sdram init checks for valid sizes for SoC.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id:
<41da3797392acaacc7963b79512c8af8005fa4b0.1664021647.git.balaton@eik.bme.hu>
[danielhb: avoid 4*GiB size due to 32 bit build problems]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 5f7effe4df91702add08e3e3dc1871fd35a8903f
https://github.com/qemu/qemu/commit/5f7effe4df91702add08e3e3dc1871fd35a8903f
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/ppc440.h
M hw/ppc/ppc440_uc.c
M hw/ppc/sam460ex.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc440_sdram: QOM'ify
Change the ppc440_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr2. This is mostly
modelling the DDR2 SDRAM controller found in the 460EX (used on the
sam460ex board). Newer SoCs (regardless of their PPC core, e.g. 405EX)
may have this controller but we only emulate enough of it for the
sam460ex u-boot firmware.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id:
<3e82ae575c7c41e464a0082d55ecb4ebcc4d4329.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 2196d337c553a17b1578ada42ab24adaca579ab7
https://github.com/qemu/qemu/commit/2196d337c553a17b1578ada42ab24adaca579ab7
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/ppc440_uc.c
M include/hw/ppc/ppc4xx.h
Log Message:
-----------
ppc440_uc.c: Move some macros to ppc4xx.h
These are used by both the SDRAM controller model and system DCRs. In
preparation to move SDRAM controller in its own file move these macros
to the ppc4xx.h header.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id:
<74d9bf4891e2ccceb52bb6ca6b54fd3f37a9fb04.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: eb0b242d36685c361a53f5069aefcdc6631b4ff1
https://github.com/qemu/qemu/commit/eb0b242d36685c361a53f5069aefcdc6631b4ff1
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/ppc440_uc.c
Log Message:
-----------
ppc440_uc.c: Remove unneeded parenthesis
Remove unneeded parenthesis around case labels.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id:
<19db326bea989c03e08f2853f789315bbe806fe9.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 8cf7b3277d705976a6c9dce90b481824cf8f10ff
https://github.com/qemu/qemu/commit/8cf7b3277d705976a6c9dce90b481824cf8f10ff
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M configs/devices/ppc-softmmu/default.mak
M hw/ppc/Kconfig
M hw/ppc/meson.build
Log Message:
-----------
hw/ppc/meson: Allow e500 boards to be enabled separately
Gives users more fine-grained control over what should be compiled into
QEMU.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221003203142.24355-2-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 2c860abfb6c097ba8cf22316ff9957485d0ff4ad
https://github.com/qemu/qemu/commit/2c860abfb6c097ba8cf22316ff9957485d0ff4ad
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/gpio/Kconfig
M hw/gpio/meson.build
M hw/ppc/Kconfig
Log Message:
-----------
hw/gpio/meson: Introduce dedicated config switch for hw/gpio/mpc8xxx
Having a dedicated config switch makes dependency handling cleaner.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221003203142.24355-3-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: e018489d8b4c1d85a3851fbe48b0befd2ccfc647
https://github.com/qemu/qemu/commit/e018489d8b4c1d85a3851fbe48b0befd2ccfc647
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M docs/system/ppc/ppce500.rst
Log Message:
-----------
docs/system/ppc/ppce500: Add heading for networking chapter
The sudden change of topics is slightly confusing and makes the
networking information less visible. So separate the networking chapter
to improve comprehensibility.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221003203142.24355-4-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: bacb4eb87608b398b5a261a5a9224758350add1d
https://github.com/qemu/qemu/commit/bacb4eb87608b398b5a261a5a9224758350add1d
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/e500.c
Log Message:
-----------
hw/ppc/e500: Reduce usage of sysbus API
PlatformBusDevice has an mmio attribute which gets aliased to
SysBusDevice::mmio[0]. So PlatformbusDevice::mmio can be used directly,
avoiding the sysbus API.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20221003203142.24355-5-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 35ad5b7492cae5da86f652e8a32ba23bbd14eaa3
https://github.com/qemu/qemu/commit/35ad5b7492cae5da86f652e8a32ba23bbd14eaa3
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/mpc8544ds.c
Log Message:
-----------
hw/ppc/mpc8544ds: Rename wrongly named method
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221003203142.24355-6-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 47a0b1dff7e9c32808ca2c8a007a4dfa7bf273f1
https://github.com/qemu/qemu/commit/47a0b1dff7e9c32808ca2c8a007a4dfa7bf273f1
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/mpc8544ds.c
Log Message:
-----------
hw/ppc/mpc8544ds: Add platform bus
Models the real device more closely.
Address and size values are taken from mpc8544.dts from the linux-5.17.7
tree. The IRQ range is taken from e500plat.c.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20221003203142.24355-7-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 9f6621bd161e95f4fe25c97bffc4f1a97a536138
https://github.com/qemu/qemu/commit/9f6621bd161e95f4fe25c97bffc4f1a97a536138
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/e500.c
M hw/ppc/e500.h
M hw/ppc/e500plat.c
M hw/ppc/mpc8544ds.c
Log Message:
-----------
hw/ppc/e500: Remove if statement which is now always true
Now that the MPC8544DS board also has a platform bus, the if statement
is always true.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221003203142.24355-8-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: c348e09fb077553469f3d9be41ba671e63733a9b
https://github.com/qemu/qemu/commit/c348e09fb077553469f3d9be41ba671e63733a9b
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: Fix xvcmp* clearing FI bit
Vector instructions in general are not supposed to change the FI bit.
However, xvcmp* instructions are calling gen_helper_float_check_status,
which is leading to a cleared FI flag where it should be kept
unchanged.
As helper_float_check_status only affects inexact, overflow and
underflow, and the xvcmp* instructions don't change these flags, this
issue can be fixed by removing the call to helper_float_check_status.
By doing this, the FI bit in FPSCR will be preserved as expected.
Fixes: 00084a25adf ("target/ppc: introduce separate VSX_CMP macro for xvcmp*
instructions")
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221005121551.27957-1-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 0a3364043d84632f7a5661cdffa5e557f5ceb250
https://github.com/qemu/qemu/commit/0a3364043d84632f7a5661cdffa5e557f5ceb250
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/spapr_pci.c
Log Message:
-----------
hw/ppc/spapr_pci.c: Use device_cold_reset() rather than device_legacy_reset()
In spapr_phb_children_reset() we call device_legacy_reset() to reset any
QOM children of the SPAPR PCI host bridge device. This will not reset
any qbus such a child might own. Switch to device_cold_reset(), which will
reset both the device and its buses. (If the child has no qbuses then
there will be no change in behaviour.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221014142841.2092784-1-peter.maydell@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: bf353ad55590f227d8b96b35e4c8bd6ab1a3d8de
https://github.com/qemu/qemu/commit/bf353ad55590f227d8b96b35e4c8bd6ab1a3d8de
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hmp-commands.hx
M include/sysemu/device_tree.h
M monitor/misc.c
M qapi/machine.json
M softmmu/device_tree.c
Log Message:
-----------
qmp/hmp, device_tree.c: introduce dumpdtb
To save the FDT blob we have the '-machine dumpdtb=<file>' property.
With this property set, the machine saves the FDT in <file> and exit.
The created file can then be converted to plain text dts format using
'dtc'.
There's nothing particularly sophisticated into saving the FDT that
can't be done with the machine at any state, as long as the machine has
a valid FDT to be saved.
The 'dumpdtb' command receives a 'filename' parameter and, if the FDT is
available via current_machine->fdt, save it in dtb format to 'filename'.
In short, this is a '-machine dumpdtb' that can be fired on demand via
QMP/HMP.
This command will always be executed in-band (i.e. holding BQL),
avoiding potential race conditions with machines that might change the
FDT during runtime (e.g. PowerPC 'pseries' machine).
Cc: Dr. David Alan Gilbert <dgilbert@redhat.com>
Cc: Markus Armbruster <armbru@redhat.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: David Gibson <david@gibson.dropbear.id.au>
Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-2-danielhb413@gmail.com>
Commit: 610cba317c28d1b4ecb6ea36c754c225f4b917ad
https://github.com/qemu/qemu/commit/610cba317c28d1b4ecb6ea36c754c225f4b917ad
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/nios2/boot.c
M hw/nios2/meson.build
Log Message:
-----------
hw/nios2: set machine->fdt in nios2_load_dtb()
This will enable support for 'dumpdtb' QMP/HMP command for all nios2
machines that uses nios2_load_dtb().
Cc: Chris Wulff <crwulff@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-7-danielhb413@gmail.com>
Commit: 8d42c851ed2f8a86e2f830d453d4c4f288007cb8
https://github.com/qemu/qemu/commit/8d42c851ed2f8a86e2f830d453d4c4f288007cb8
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/ppc440_bamboo.c
Log Message:
-----------
hw/ppc: set machine->fdt in bamboo_load_device_tree()
This will enable support for 'dumpdtb' QMP/HMP command for the bamboo
machine.
Setting machine->fdt requires a MachineState pointer to be used inside
bamboo_load_device_tree(). Let's change the function to receive this
pointer from the caller. 'ramsize' and 'kernel_cmdline' can be retrieved
directly from the 'machine' pointer.
Cc: Cédric Le Goater <clg@kaod.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-9-danielhb413@gmail.com>
Commit: 698af4cb35061d87bbc40d24fa6ccde10030300e
https://github.com/qemu/qemu/commit/698af4cb35061d87bbc40d24fa6ccde10030300e
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/sam460ex.c
Log Message:
-----------
hw/ppc: set machine->fdt in sam460ex_load_device_tree()
This will enable support for 'dumpdtb' QMP/HMP command for the sam460ex
machine.
Setting machine->fdt requires a MachineState pointer to be used inside
sam460ex_load_device_tree(). Let's change the function to receive this
pointer from the caller. 'ramsize' and 'kernel_cmdline' can be retrieved
directly from the 'machine' pointer.
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-10-danielhb413@gmail.com>
Commit: 4b326f8985ad21dc135843a6c1682bbd76fd5f36
https://github.com/qemu/qemu/commit/4b326f8985ad21dc135843a6c1682bbd76fd5f36
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/virtex_ml507.c
Log Message:
-----------
hw/ppc: set machine->fdt in xilinx_load_device_tree()
This will enable support for 'dumpdtb' QMP/HMP command for the
virtex_ml507 machine.
Setting machine->fdt requires a MachineState pointer to be used inside
xilinx_load_device_tree(). Let's change the function to receive this
pointer from the caller. kernel_cmdline' can be retrieved directly from
the 'machine' pointer. 'ramsize' wasn't being used so can be removed.
Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-11-danielhb413@gmail.com>
Commit: 8d55f8768817f1ccc2b4b99e00e3901b9be139d0
https://github.com/qemu/qemu/commit/8d55f8768817f1ccc2b4b99e00e3901b9be139d0
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/pegasos2.c
Log Message:
-----------
hw/ppc: set machine->fdt in pegasos2_machine_reset()
We'll introduce a QMP/HMP command that requires machine->fdt to be set
properly.
Cc: BALATON Zoltan <balaton@eik.bme.hu>
Cc: qemu-ppc@nongnu.org
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-12-danielhb413@gmail.com>
Commit: adb779965354638c43d26bf197fb06aa49d1f8cf
https://github.com/qemu/qemu/commit/adb779965354638c43d26bf197fb06aa49d1f8cf
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
hw/ppc: set machine->fdt in pnv_reset()
This will enable support for the 'dumpdtb' QMP/HMP command for
all powernv machines.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-13-danielhb413@gmail.com>
Commit: d890f2fa9f1e17a86f4e0891f175ae214a8596bf
https://github.com/qemu/qemu/commit/d890f2fa9f1e17a86f4e0891f175ae214a8596bf
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
Log Message:
-----------
hw/ppc: set machine->fdt in spapr machine
The pSeries machine never bothered with the common machine->fdt
attribute. We do all the FDT related work using spapr->fdt_blob.
We're going to introduce a QMP/HMP command to dump the FDT, which will
rely on setting machine->fdt properly to work across all machine
archs/types.
Let's set machine->fdt in two places where we manipulate the FDT:
spapr_machine_reset() and CAS. There are other places where the FDT is
manipulated in the pSeries machines, most notably the hotplug/unplug
path. For now we'll acknowledge that we won't have the most accurate
representation of the FDT, depending on the current machine state, when
using this QMP/HMP fdt command. Making the internal FDT representation
always match the actual FDT representation that the guest is using is a
problem for another day.
spapr->fdt_blob is left untouched for now. To replace it with
machine->fdt, since we're migrating spapr->fdt_blob, we would need to
migrate machine->fdt as well. This is something that we would like to to
do keep our code simpler but it's also a work we'll leave for later.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-14-danielhb413@gmail.com>
Commit: cf79892f4b19ee19c9f5e99fd9d425ab453c1217
https://github.com/qemu/qemu/commit/cf79892f4b19ee19c9f5e99fd9d425ab453c1217
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/riscv/sifive_u.c
Log Message:
-----------
hw/riscv: set machine->fdt in sifive_u_machine_init()
This will enable support for 'dumpdtb' QMP/HMP command for the sifive_u
machine.
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Bin Meng <bin.meng@windriver.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-15-danielhb413@gmail.com>
Commit: 719b718ce27f52b2da600cc1abf6a41ac54dfa36
https://github.com/qemu/qemu/commit/719b718ce27f52b2da600cc1abf6a41ac54dfa36
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-10-17 (Mon, 17 Oct 2022)
Changed paths:
M hw/riscv/spike.c
Log Message:
-----------
hw/riscv: set machine->fdt in spike_board_init()
This will enable support for the 'dumpdtb' QMP/HMP command for the spike
machine.
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220926173855.1159396-16-danielhb413@gmail.com>
Commit: 35fd22b01de00015ca7367c16f1621ff33b4ba95
https://github.com/qemu/qemu/commit/35fd22b01de00015ca7367c16f1621ff33b4ba95
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M configure
Log Message:
-----------
configure: don't enable firmware for targets that are not built
This avoids the unfortunate effect of building pc-bios blobs
even for targets the user isn't interested in.
Due to the bi-arch nature of x86 and PPC firmware, check for the
desired target by hand, and don't just look for the compilation target
in $target_list.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 4a5fc890b1d3609f7b22d2094d094e80c24bcf40
https://github.com/qemu/qemu/commit/4a5fc890b1d3609f7b22d2094d094e80c24bcf40
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M hw/scsi/esp.c
M hw/scsi/lsi53c895a.c
M hw/scsi/megasas.c
M hw/scsi/mptsas.c
M hw/scsi/spapr_vscsi.c
M hw/scsi/virtio-scsi.c
M hw/scsi/vmw_pvscsi.c
Log Message:
-----------
scsi: Use device_cold_reset() and bus_cold_reset()
In the SCSI subsystem we currently use the legacy functions
qdev_reset_all() and qbus_reset_all(). These perform a recursive
reset, starting from either a qbus or a qdev. However they do not
permit any of the devices in the tree to use three-phase reset,
because device reset goes through the device_legacy_reset() function
that only calls the single DeviceClass::reset method.
Switch to using the device_cold_reset() and bus_cold_reset()
functions. These also perform a recursive reset, where first the
children are reset and then finally the parent, but they use the new
(...in 2020...) Resettable mechanism, which supports both the old
style single-reset method and also the new 3-phase reset handling.
Since no devices attached to SCSI buses currently try to use 3-phase
reset, this should be a no-behaviour-change commit which just reduces
the use of a deprecated API.
Commit created with:
sed -i -e
's/qdev_reset_all/device_cold_reset/g;s/qbus_reset_all/bus_cold_reset/g'
hw/scsi/*.c
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20221013160623.1296109-2-peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 8b5335e381e7fd7554a65c6d591875ade1cea062
https://github.com/qemu/qemu/commit/8b5335e381e7fd7554a65c6d591875ade1cea062
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M hw/scsi/vmw_pvscsi.c
Log Message:
-----------
hw/scsi/vmw_pvscsi.c: Use device_cold_reset() to reset SCSI devices
Currently the vwm_pvscsi controller resets individual SCSI devices
with the device_legacy_reset() function. The only difference between
this and device_cold_reset() is that device_legacy_reset() resets the
device but not any child qbuses it might have.
In this case, no SCSI device has a child qbus, so the functions have
the same behaviour. Switch to device_cold_reset() to move away from
using the deprecated function, and bring this SCSI controller in to
line with what all the others do.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20221013160623.1296109-3-peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: ec19444a53ef221954128e36e1387592a2273dc2
https://github.com/qemu/qemu/commit/ec19444a53ef221954128e36e1387592a2273dc2
Author: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M hw/i386/microvm.c
M hw/i386/pc.c
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/hyperv.c
M target/i386/kvm/kvm.c
M target/i386/kvm/kvm_i386.h
Log Message:
-----------
hyperv: fix SynIC SINT assertion failure on guest reset
Resetting a guest that has Hyper-V VMBus support enabled triggers a QEMU
assertion failure:
hw/hyperv/hyperv.c:131: synic_reset: Assertion
`QLIST_EMPTY(&synic->sint_routes)' failed.
This happens both on normal guest reboot or when using "system_reset" HMP
command.
The failing assertion was introduced by commit 64ddecc88bcf ("hyperv: SControl
is optional to enable SynIc")
to catch dangling SINT routes on SynIC reset.
The root cause of this problem is that the SynIC itself is reset before
devices using SINT routes have chance to clean up these routes.
Since there seems to be no existing mechanism to force reset callbacks (or
methods) to be executed in specific order let's use a similar method that
is already used to reset another interrupt controller (APIC) after devices
have been reset - by invoking the SynIC reset from the machine reset
handler via a new x86_cpu_after_reset() function co-located with
the existing x86_cpu_reset() in target/i386/cpu.c.
Opportunistically move the APIC reset handler there, too.
Fixes: 64ddecc88bcf ("hyperv: SControl is optional to enable SynIc") # exposed
the bug
Signed-off-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Message-Id:
<cb57cee2e29b20d06f81dce054cbcea8b5d497e8.1664552976.git.maciej.szmigiero@oracle.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 33ab5f24913db8d5590fe4155829bd38e7902506
https://github.com/qemu/qemu/commit/33ab5f24913db8d5590fe4155829bd38e7902506
Author: Michal Privoznik <mprivozn@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M configure
Log Message:
-----------
configure: Avoid using strings binary
When determining the endiandness of the target architecture we're
building for a small program is compiled, which in an obfuscated
way declares two strings. Then, we look which string is in
correct order (using strings binary) and deduct the endiandness.
But using the strings binary is problematic, because it's part of
toolchain (strings is just a symlink to
x86_64-pc-linux-gnu-strings or llvm-strings). And when
(cross-)compiling, it requires users to set the symlink to the
correct toolchain.
Fortunately, we have a better alternative anyways. We can mimic
what compiler.h is already doing: comparing __BYTE_ORDER__
against values for little/big endiandness.
Bug: https://bugs.gentoo.org/876933
Signed-off-by: Michal Privoznik <mprivozn@redhat.com>
Message-Id:
<d6d9c7043cfe6d976d96694f2b4ecf85cf3206f1.1665732504.git.mprivozn@redhat.com>
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 08c4f4db60f8744e7aec107b056ea1a9d6d20265
https://github.com/qemu/qemu/commit/08c4f4db60f8744e7aec107b056ea1a9d6d20265
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: Use device_cold_reset() to reset the APIC
The semantic difference between the deprecated device_legacy_reset()
function and the newer device_cold_reset() function is that the new
function resets both the device itself and any qbuses it owns,
whereas the legacy function resets just the device itself and nothing
else.
The x86_cpu_after_reset() function uses device_legacy_reset() to reset
the APIC; this is an APICCommonState and does not have any qbuses, so
for this purpose the two functions behave identically and we can stop
using the deprecated one.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20221013171926.1447899-1-peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 913f0836f69f67ffb5678fa148b9df85d3f46539
https://github.com/qemu/qemu/commit/913f0836f69f67ffb5678fa148b9df85d3f46539
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: Save and restore pc_save before tcg_remove_ops_after
Restore pc_save while undoing any state change that may have
happened while decoding the instruction. Leave a TODO about
removing all of that when the table-based decoder is complete.
Cc: Paolo Bonzini <pbonzini@redhat.com>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221016222303.288551-1-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 487d11333ae9797bd9b33b1827f9830d970e48f8
https://github.com/qemu/qemu/commit/487d11333ae9797bd9b33b1827f9830d970e48f8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/sysemu/excp_helper.c
Log Message:
-----------
target/i386: Use MMUAccessType across excp_helper.c
Replace int is_write1 and magic numbers with the proper
MMUAccessType access_type and enumerators.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221002172956.265735-2-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: e4ddff5262422257eadbd09bec30e2cc81613835
https://github.com/qemu/qemu/commit/e4ddff5262422257eadbd09bec30e2cc81613835
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/sysemu/excp_helper.c
Log Message:
-----------
target/i386: Direct call get_hphys from mmu_translate
Use a boolean to control the call to get_hphys instead
of passing a null function pointer.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221002172956.265735-3-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 3563362ddfaefcb2866c91abed4294e3a187d6d3
https://github.com/qemu/qemu/commit/3563362ddfaefcb2866c91abed4294e3a187d6d3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/sysemu/excp_helper.c
Log Message:
-----------
target/i386: Introduce structures for mmu_translate
Create TranslateParams for inputs, TranslateResults for successful
outputs, and TranslateFault for error outputs; return true on success.
Move stage1 error paths from handle_mmu_fault to x86_cpu_tlb_fill;
reorg the rest of handle_mmu_fault into get_physical_address.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221002172956.265735-4-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 9bbcf372193a2064743461aea5bf59cc83e37aa9
https://github.com/qemu/qemu/commit/9bbcf372193a2064743461aea5bf59cc83e37aa9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/sysemu/excp_helper.c
Log Message:
-----------
target/i386: Reorg GET_HPHYS
Replace with PTE_HPHYS for the page table walk, and a direct call
to mmu_translate for the final stage2 translation. Hoist the check
for HF2_NPT_MASK out to get_physical_address, which avoids the
recursive call when stage2 is disabled.
We can now return all the way out to x86_cpu_tlb_fill before raising
an exception, which means probe works.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221002172956.265735-5-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 98281984a373a68a3c497dfb88e42195f3a1cc93
https://github.com/qemu/qemu/commit/98281984a373a68a3c497dfb88e42195f3a1cc93
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/cpu-param.h
M target/i386/cpu.h
M target/i386/tcg/sysemu/excp_helper.c
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Add MMU_PHYS_IDX and MMU_NESTED_IDX
These new mmu indexes will be helpful for improving
paging and code throughout the target.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221002172956.265735-6-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 726ea335313ecb0c8c464a5fe2b796ceff59d7b0
https://github.com/qemu/qemu/commit/726ea335313ecb0c8c464a5fe2b796ceff59d7b0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/cpu.h
M target/i386/tcg/sysemu/excp_helper.c
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Use MMU_NESTED_IDX for vmload/vmsave
Use MMU_NESTED_IDX for each memory access, rather than
just a single translation to physical. Adjust svm_save_seg
and svm_load_seg to pass in mmu_idx.
This removes the last use of get_hphys so remove it.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221002172956.265735-7-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 11b4e971dc3f830584dffb4b8287229d842152c7
https://github.com/qemu/qemu/commit/11b4e971dc3f830584dffb4b8287229d842152c7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/sysemu/excp_helper.c
Log Message:
-----------
target/i386: Combine 5 sets of variables in mmu_translate
We don't need one variable set per translation level,
which requires copying into pte/pte_addr for huge pages.
Standardize on pte/pte_addr for all levels.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221002172956.265735-8-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 4a1e9d4d11cd5c0f05f7f04467088ff09fcdafac
https://github.com/qemu/qemu/commit/4a1e9d4d11cd5c0f05f7f04467088ff09fcdafac
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/sysemu/excp_helper.c
Log Message:
-----------
target/i386: Use atomic operations for pte updates
Use probe_access_full in order to resolve to a host address,
which then lets us use a host cmpxchg to update the pte.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/279
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221002172956.265735-9-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 8629e77be5f8106b3497cc197fbd57a12ae6333f
https://github.com/qemu/qemu/commit/8629e77be5f8106b3497cc197fbd57a12ae6333f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/sysemu/excp_helper.c
Log Message:
-----------
target/i386: Use probe_access_full for final stage2 translation
Rather than recurse directly on mmu_translate, go through the
same softmmu lookup that we did for the page table walk.
This centralizes all knowledge of MMU_NESTED_IDX, with respect
to setup of TranslationParams, to get_physical_address.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221002172956.265735-10-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 75f107a8569fb968d1595dd631d96101a763a50a
https://github.com/qemu/qemu/commit/75f107a8569fb968d1595dd631d96101a763a50a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/cpu.h
Log Message:
-----------
target/i386: Define XMMReg and access macros, align ZMM registers
This will be used for emission and endian adjustments of gvec operations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822223722.1697758-2-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 12a2c9c72c86baa6840eb416877bf55b554153f3
https://github.com/qemu/qemu/commit/12a2c9c72c86baa6840eb416877bf55b554153f3
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: make ldo/sto operations consistent with ldq
ldq takes a pointer to the first byte to load the 64-bit word in;
ldo takes a pointer to the first byte of the ZMMReg. Make them
consistent, which will be useful in the new SSE decoder's
load/writeback routines.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: a61ef762f976e58363efd6124b3a2992a2d0cdca
https://github.com/qemu/qemu/commit/a61ef762f976e58363efd6124b3a2992a2d0cdca
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: make rex_w available even in 32-bit mode
REX.W can be used even in 32-bit mode by AVX instructions, where it is
retroactively
renamed to VEX.W. Make the field available even in 32-bit mode but keep the
REX_W()
macro as it was; this way, that the handling of dflag does not use it by
mistake and
the AVX code more clearly points at the special VEX behavior of the bit.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: b3e22b2318afcaff6fe6e0e031dda11d324c8b4a
https://github.com/qemu/qemu/commit/b3e22b2318afcaff6fe6e0e031dda11d324c8b4a
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
A target/i386/tcg/decode-new.c.inc
A target/i386/tcg/decode-new.h
A target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: add core of new i386 decoder
The new decoder is based on three principles:
- use mostly table-driven decoding, using tables derived as much as possible
from the Intel manual. Centralizing the decode the operands makes it
more homogeneous, for example all immediates are signed. All modrm
handling is in one function, and can be shared between SSE and ALU
instructions (including XMM<->GPR instructions). The SSE/AVX decoder
will also not have duplicated code between the 0F, 0F38 and 0F3A tables.
- keep the code as "non-branchy" as possible. Generally, the code for
the new decoder is more verbose, but the control flow is simpler.
Conditionals are not nested and have small bodies. All instruction
groups are resolved even before operands are decoded, and code
generation is separated as much as possible within small functions
that only handle one instruction each.
- keep address generation and (for ALU operands) memory loads and writeback
as much in common code as possible. All ALU operations for example
are implemented as T0=f(T0,T1). For non-ALU instructions,
read-modify-write memory operations are rare, but registers do not
have TCGv equivalents: therefore, the common logic sets up pointer
temporaries with the operands, while load and writeback are handled
by gvec or by helpers.
These principles make future code review and extensibility simpler, at
the cost of having a relatively large amount of code in the form of this
patch. Even EVEX should not be _too_ hard to implement (it's just a crazy
large amount of possibilities).
This patch introduces the main decoder flow, and integrates the old
decoder with the new one. The old decoder takes care of parsing
prefixes and then optionally drops to the new one. The changes to the
old decoder are minimal and allow it to be replaced incrementally with
the new one.
There is a debugging mechanism through a "LIMIT" environment variable.
In user-mode emulation, the variable is the number of instructions
decoded by the new decoder before permanently switching to the old one.
In system emulation, the variable is the highest opcode that is decoded
by the new decoder (this is less friendly, but it's the best that can
be done without requiring deterministic execution).
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 6ba13999be293c4183879b75a5343bc6a8c98c00
https://github.com/qemu/qemu/commit/6ba13999be293c4183879b75a5343bc6a8c98c00
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/decode-new.h
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: add ALU load/writeback core
Add generic code generation that takes care of preparing operands
around calls to decode.e.gen in a table-driven manner, so that ALU
operations need not take care of that.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 268dc4648fd7b3e48de93d43397dd8478ebbd02d
https://github.com/qemu/qemu/commit/268dc4648fd7b3e48de93d43397dd8478ebbd02d
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: add CPUID[EAX=7,ECX=0].ECX to DisasContext
TCG will shortly implement VAES instructions, so add the relevant feature
word to the DisasContext.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: caa01fadbef15f0e2a5ac7bfc7372a4b4244687f
https://github.com/qemu/qemu/commit/caa01fadbef15f0e2a5ac7bfc7372a4b4244687f
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/decode-new.h
Log Message:
-----------
target/i386: add CPUID feature checks to new decoder
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 608db8dbfb80d43ec3a29626a805e39cc4934988
https://github.com/qemu/qemu/commit/608db8dbfb80d43ec3a29626a805e39cc4934988
Author: Paul Brook <paul@nowt.org>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/cpu.h
M target/i386/helper.c
M target/i386/tcg/fpu_helper.c
Log Message:
-----------
target/i386: add AVX_EN hflag
Add a new hflag bit to determine whether AVX instructions are allowed
Signed-off-by: Paul Brook <paul@nowt.org>
Message-Id: <20220424220204.2493824-4-paul@nowt.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 20581aadec5e5a9d6836e4612b6f44a7cbda7d16
https://github.com/qemu/qemu/commit/20581aadec5e5a9d6836e4612b6f44a7cbda7d16
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/decode-new.h
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: validate VEX prefixes via the instructions' exception classes
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 55a3328669b57b1b093b93d2d63167f6dd6b767f
https://github.com/qemu/qemu/commit/55a3328669b57b1b093b93d2d63167f6dd6b767f
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/decode-new.h
Log Message:
-----------
target/i386: validate SSE prefixes directly in the decoding table
Many SSE and AVX instructions are only valid with specific prefixes
(none, 66, F3, F2). Introduce a direct way to encode this in the
decoding table to avoid using decode groups too much.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 1d0b926150e5180a6eef11745317f6af79d869c2
https://github.com/qemu/qemu/commit/1d0b926150e5180a6eef11745317f6af79d869c2
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder
Because these are the only VEX instructions that QEMU supports, the
new decoder is entered on the first byte of a valid VEX prefix, and VEX
decoding only needs to be done in decode-new.c.inc.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 30f419219abd6cb242f565fc54767ac021845abe
https://github.com/qemu/qemu/commit/30f419219abd6cb242f565fc54767ac021845abe
Author: Paul Brook <paul@nowt.org>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/ops_sse_header.h
Log Message:
-----------
target/i386: Prepare ops_sse_header.h for 256 bit AVX
Adjust all #ifdefs to match the ones in ops_sse.h.
Signed-off-by: Paul Brook <paul@nowt.org>
Message-Id: <20220424220204.2493824-23-paul@nowt.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: f05f9789f57d5394fc118fe31aa2a9f563311140
https://github.com/qemu/qemu/commit/f05f9789f57d5394fc118fe31aa2a9f563311140
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/ops_sse.h
M target/i386/ops_sse_header.h
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: extend helpers to support VEX.V 3- and 4- operand encodings
Add to the helpers all the operands that are needed to implement AVX.
Extracted from a patch by Paul Brook <paul@nowt.org>.
Message-Id: <20220424220204.2493824-26-paul@nowt.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 1de9e7e61212e332e9bd7145c744bd3f411c7847
https://github.com/qemu/qemu/commit/1de9e7e61212e332e9bd7145c744bd3f411c7847
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/ops_sse.h
Log Message:
-----------
target/i386: support operand merging in binary scalar helpers
Compared to Paul's implementation, the new decoder will use a different approach
to implement AVX's merging of dst with src1 on scalar operations. Adjust the
helpers to provide this functionality.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 620f75566a5d81d7b82b3788b83d0b95c7d21dcd
https://github.com/qemu/qemu/commit/620f75566a5d81d7b82b3788b83d0b95c7d21dcd
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/ops_sse.h
M target/i386/ops_sse_header.h
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: provide 3-operand versions of unary scalar helpers
Compared to Paul's implementation, the new decoder will use a different approach
to implement AVX's merging of dst with src1 on scalar operations. Adjust the
old SSE decoder to be compatible with new-style helpers.
The affected instructions are CVTSx2Sx, ROUNDSx, RSQRTSx, SQRTSx, RCPSx.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 6e0cac782ab121ab5a330644c4c38011c53de30f
https://github.com/qemu/qemu/commit/6e0cac782ab121ab5a330644c4c38011c53de30f
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/ops_sse.h
M target/i386/ops_sse_header.h
Log Message:
-----------
target/i386: implement additional AVX comparison operators
The new implementation of SSE will cover AVX from the get go, so include
the 24 extra comparison operators that are only available with the VEX
prefix.
Based on a patch by Paul Brook <paul@nowt.org>.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: b98f886c8f8661773047197d132efec97810b37a
https://github.com/qemu/qemu/commit/b98f886c8f8661773047197d132efec97810b37a
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/helper.h
M target/i386/ops_sse.h
M target/i386/ops_sse_header.h
M target/i386/tcg/fpu_helper.c
Log Message:
-----------
target/i386: Introduce 256-bit vector helpers
The new implementation of SSE will cover AVX from the get go, because
all the work for the helper functions is already done. We just need to
build them.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 92ec056a6b2fc5d5a5593121c5d9475d2a2461d6
https://github.com/qemu/qemu/commit/92ec056a6b2fc5d5a5593121c5d9475d2a2461d6
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: reimplement 0x0f 0x60-0x6f, add AVX
These are both MMX and SSE/AVX instructions, except for vmovdqu. In both
cases the inputs and output is in s->ptr{0,1,2}, so the only difference
between MMX, SSE, and AVX is which helper to call.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 1d0efbdb35f619db9178e862742335d7c472c1a4
https://github.com/qemu/qemu/commit/1d0efbdb35f619db9178e862742335d7c472c1a4
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, add AVX
These are more simple integer instructions present in both MMX and SSE/AVX,
with no holes that were later occupied by newer instructions.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 03b4588070b647398acd4d6a654836bba554c800
https://github.com/qemu/qemu/commit/03b4588070b647398acd4d6a654836bba554c800
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: reimplement 0x0f 0x50-0x5f, add AVX
These are mostly floating-point SSE operations. The odd ones out
are MOVMSK and CVTxx2yy, the others are straightforward.
Unary operations are a bit special in AVX because they have 2 operands
for PD/PS operands (VEX.vvvv must be 1111b), and 3 operands for SD/SS.
They are handled using X86_OP_GROUP3 for compactness.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: d1c1a4222cdcab0e3de1635dbc71dc646975507b
https://github.com/qemu/qemu/commit/d1c1a4222cdcab0e3de1635dbc71dc646975507b
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: reimplement 0x0f 0x78-0x7f, add AVX
These are a mixed batch, including the first two horizontal
(66 and F2 only) operations, more moves, and SSE4a extract/insert.
Because SSE4a is pretty rare, I chose to leave the helper as they are,
but it is possible to unify them by loading index and length from the
source XMM register and generating deposit or extract TCG ops.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: ce4fcb94785f7326682e1c72400ddd299481db6e
https://github.com/qemu/qemu/commit/ce4fcb94785f7326682e1c72400ddd299481db6e
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: reimplement 0x0f 0x70-0x77, add AVX
This includes shifts by immediate, which use bits 3-5 of the ModRM byte
as an opcode extension. With the exception of 128-bit shifts, they are
implemented using gvec.
This also covers VZEROALL and VZEROUPPER, which use the same opcode
as EMMS. If we were wanting to optimize out gen_clear_ymmh then this
would be one of the starting points. The implementation of the VZEROALL
and VZEROUPPER helpers is by Paul Brook.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 6bbeb98d10f9d93e723a0fa3d35457750f5e69ac
https://github.com/qemu/qemu/commit/6bbeb98d10f9d93e723a0fa3d35457750f5e69ac
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/decode-new.h
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVX
The more complicated ones here are d6-d7, e6-e7, f7. The others
are trivial.
For LDDQU, using gen_load_sse directly might corrupt the register if
the second part of the load fails. Therefore, add a custom X86_TYPE_WM
value; like X86_TYPE_W it does call gen_load(), but it also rejects a
value of 11 in the ModRM field like X86_TYPE_M.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: a64eee3ab402469b536db9aeb259097b84d31d0f
https://github.com/qemu/qemu/commit/a64eee3ab402469b536db9aeb259097b84d31d0f
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/ops_sse.h
M target/i386/ops_sse_header.h
Log Message:
-----------
target/i386: clarify (un)signedness of immediates from 0F3Ah opcodes
Three-byte opcodes from the 0F3Ah area all have an immediate byte which
is usually unsigned. Clarify in the helper code that it is unsigned;
the new decoder treats immediates as signed by default, and seeing
an intN_t in the prototype might give the wrong impression that one
can use decode->immediate directly.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 7906847768613ea6b6e737f3295c77cdb4ff67f4
https://github.com/qemu/qemu/commit/7906847768613ea6b6e737f3295c77cdb4ff67f4
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/ops_sse.h
M target/i386/ops_sse_header.h
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: reimplement 0x0f 0x3a, add AVX
The more complicated operations here are insertions and extractions.
Otherwise, there are just more entries than usual because the PS/PD/SS/SD
variations are encoded in the opcode rater than in the prefixes.
These three-byte opcodes also include AVX new instructions, whose
implementation in the helpers was originally done by Paul Brook
<paul@nowt.org>.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: d4af67a27a817c2e96b7de176045fd95e2e9420b
https://github.com/qemu/qemu/commit/d4af67a27a817c2e96b7de176045fd95e2e9420b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/emit.c.inc
Log Message:
-----------
target/i386: Use tcg gvec ops for pmovmskb
As pmovmskb is used by strlen et al, this is the third
highest overhead sse operation at %0.8.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
[Reorganize to generate code for any vector size. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 16fc5726a6e296b3f63acec537c299c1dc49d6c4
https://github.com/qemu/qemu/commit/16fc5726a6e296b3f63acec537c299c1dc49d6c4
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/ops_sse.h
M target/i386/ops_sse_header.h
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/decode-new.h
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: reimplement 0x0f 0x38, add AVX
There are several special cases here:
1) extending moves have different widths for the helpers vs. for the
memory loads, and the width for memory loads depends on VEX.L too.
This is represented by X86_SPECIAL_AVXExtMov.
2) some instructions, such as variable-width shifts, select the vector element
size via REX.W.
3) VSIB instructions (VGATHERxPy, VPGATHERxy) are also part of this group,
and they have (among other things) two output operands.
3) the macros for 4-operand blends (which are under 0x0f 0x3a) have to be
extended to support 2-operand blends. The 2-operand variant actually
came a few years earlier, but it is clearer to implement them in the
opposite order.
X86_TYPE_WM, introduced earlier for unaligned loads, is reused for helpers
that accept a Reg* but have a M argument.
These three-byte opcodes also include AVX new instructions, for which
the helpers were originally implemented by Paul Brook <paul@nowt.org>.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: aba2b8ecb90552cb347ac2e33557a3d475830ed4
https://github.com/qemu/qemu/commit/aba2b8ecb90552cb347ac2e33557a3d475830ed4
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, add AVX
Nothing special going on here, for once.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 7170a17ec3f29320dc66075cfea671013d4e2511
https://github.com/qemu/qemu/commit/7170a17ec3f29320dc66075cfea671013d4e2511
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/ops_sse.h
M target/i386/ops_sse_header.h
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: reimplement 0x0f 0x10-0x17, add AVX
These are mostly moves, and yet are a total pain. The main issue
is that:
1) some instructions are selected by mod==11 (register operand)
vs. mod=00/01/10 (memory operand)
2) stores to memory are two-operand operations, while the 3-register
and load-from-memory versions operate on the entire contents of the
destination; this makes it easier to separate the gen_* function for
the store case
3) it's inefficient to load into xmm_T0 only to move the value out
again, so the gen_* function for the load case is separated too
The manual also has various mistakes in the operands here, for example
the store case of MOVHPS operates on a 128-bit source (albeit discarding
the bottom 64 bits) and therefore should be Mq,Vdq rather than Mq,Vq.
Likewise for the destination and source of MOVHLPS.
VUNPCK?PS and VUNPCK?PD are the same as VUNPCK?DQ and VUNPCK?QDQ,
but encoded as prefixes rather than separate operands. The helpers
can be reused however.
For MOVSLDUP, MOVSHDUP and MOVDDUP I chose to reimplement them as
helpers. I named the helper for MOVDDUP "movdldup" in preparation
for possible future introduction of MOVDHDUP and to clarify the
similarity with MOVSLDUP.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: f8d19eec0d53db298fc8269c2414fc2d214f22a4
https://github.com/qemu/qemu/commit/f8d19eec0d53db298fc8269c2414fc2d214f22a4
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: reimplement 0x0f 0x28-0x2f, add AVX
Here the code is a bit uglier due to the truncation and extension
of registers to and from 32-bit. There is also a mistake in the
manual with respect to the size of the memory operand of CVTPS2PI
and CVTTPS2PI, reported by Ricky Zhou.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 892544317fe1f6a181e47c44307a38ba42fcdd18
https://github.com/qemu/qemu/commit/892544317fe1f6a181e47c44307a38ba42fcdd18
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/fpu_helper.c
Log Message:
-----------
target/i386: implement XSAVE and XRSTOR of AVX registers
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 57f6bba023d8ed60ee1ab9e91aef34f28a173447
https://github.com/qemu/qemu/commit/57f6bba023d8ed60ee1ab9e91aef34f28a173447
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/emit.c.inc
Log Message:
-----------
target/i386: implement VLDMXCSR/VSTMXCSR
These are exactly the same as the non-VEX version, but one has to be careful
that only VEX.L=0 is allowed.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 2f8a21d8ff3af484a37edc8ea61d127ec1529ab5
https://github.com/qemu/qemu/commit/2f8a21d8ff3af484a37edc8ea61d127ec1529ab5
Author: Paul Brook <paul@nowt.org>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: Enable AVX cpuid bits when using TCG
Include AVX, AVX2 and VAES in the guest cpuid features supported by TCG.
Signed-off-by: Paul Brook <paul@nowt.org>
Message-Id: <20220424220204.2493824-40-paul@nowt.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 0339ddfa7562d835cca1dd468c2ad08b84a7abb5
https://github.com/qemu/qemu/commit/0339ddfa7562d835cca1dd468c2ad08b84a7abb5
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M tests/tcg/i386/Makefile.target
M tests/tcg/i386/test-avx.c
M tests/tcg/i386/test-avx.py
Log Message:
-----------
tests/tcg: extend SSE tests to AVX
Extracted from a patch by Paul Brook <paul@nowt.org>.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 71a0891d611189b651887414f56f8bb10c796d6f
https://github.com/qemu/qemu/commit/71a0891d611189b651887414f56f8bb10c796d6f
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/helper.h
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/decode-new.h
M target/i386/tcg/emit.c.inc
M target/i386/tcg/fpu_helper.c
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: move 3DNow to the new decoder
This adds another kind of weirdness when you thought you had seen it all:
an opcode byte that comes _after_ the address, not before. It's not
worth adding a new X86_SPECIAL_* constant for it, but it's actually
not unlike VCMP; so, forgive me for exploiting the similarity and just
deciding to dispatch to the right gen_helper_* call in a single code
generation function.
In fact, the old decoder had a bug where s->rip_offset should have
been set to 1 for 3DNow! instructions, and it's fixed now.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 653fad2497bed71d938827299cb9ac38ac333f9b
https://github.com/qemu/qemu/commit/653fad2497bed71d938827299cb9ac38ac333f9b
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M target/i386/ops_sse.h
M target/i386/ops_sse_header.h
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/emit.c.inc
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: remove old SSE decoder
With all SSE (and AVX!) instructions now implemented in disas_insn_new,
it's possible to remove gen_sse, as well as the helpers for instructions
that now use gvec.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 2c65091fd9d387b8dca8115dbdd9c3c61f658a9e
https://github.com/qemu/qemu/commit/2c65091fd9d387b8dca8115dbdd9c3c61f658a9e
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M MAINTAINERS
M configs/devices/ppc-softmmu/default.mak
M docs/system/ppc/ppce500.rst
M hmp-commands.hx
M hw/gpio/Kconfig
M hw/gpio/meson.build
M hw/nios2/boot.c
M hw/nios2/meson.build
M hw/ppc/Kconfig
M hw/ppc/e500.c
M hw/ppc/e500.h
M hw/ppc/e500plat.c
M hw/ppc/meson.build
M hw/ppc/mpc8544ds.c
M hw/ppc/pegasos2.c
M hw/ppc/pnv.c
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
M hw/ppc/ppc440.h
M hw/ppc/ppc440_bamboo.c
M hw/ppc/ppc440_uc.c
M hw/ppc/ppc4xx_devs.c
M hw/ppc/sam460ex.c
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_pci.c
M hw/ppc/virtex_ml507.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M include/hw/ppc/ppc4xx.h
M include/sysemu/device_tree.h
M monitor/misc.c
M qapi/machine.json
M softmmu/device_tree.c
M target/ppc/excp_helper.c
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
Merge tag 'pull-ppc-20221017' of https://gitlab.com/danielhb/qemu into staging
ppc patch queue for 2022-10-18:
This queue contains improvements in the e500 and ppc4xx boards, changes
in the maintainership of the project, a new QMP/HMP command and bug
fixes:
- Cedric is stepping back from qemu-ppc maintainership;
- ppc4xx_sdram: QOMification and clean ups;
- e500: add new types of flash and clean ups;
- QMP/HMP: introduce dumpdtb command;
- spapr_pci, booke doorbell interrupt and xvcmp* bit fixes;
The 'dumpdtb' implementation is also making changes to RISC-V files that
were acked by Alistair Francis and are being included in this queue.
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# ZIadAQCYY9f+NFrSJBm3z4JjUaP+GmbgEjibjZW05diyKwbqzQEAjE1KXFCcd40D
# 3Brs2Dm4YruaJCwb68vswVQAYteXaQ8=
# =hl94
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 17 Oct 2022 15:16:34 EDT
# gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>"
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164
* tag 'pull-ppc-20221017' of https://gitlab.com/danielhb/qemu: (38 commits)
hw/riscv: set machine->fdt in spike_board_init()
hw/riscv: set machine->fdt in sifive_u_machine_init()
hw/ppc: set machine->fdt in spapr machine
hw/ppc: set machine->fdt in pnv_reset()
hw/ppc: set machine->fdt in pegasos2_machine_reset()
hw/ppc: set machine->fdt in xilinx_load_device_tree()
hw/ppc: set machine->fdt in sam460ex_load_device_tree()
hw/ppc: set machine->fdt in bamboo_load_device_tree()
hw/nios2: set machine->fdt in nios2_load_dtb()
qmp/hmp, device_tree.c: introduce dumpdtb
hw/ppc/spapr_pci.c: Use device_cold_reset() rather than device_legacy_reset()
target/ppc: Fix xvcmp* clearing FI bit
hw/ppc/e500: Remove if statement which is now always true
hw/ppc/mpc8544ds: Add platform bus
hw/ppc/mpc8544ds: Rename wrongly named method
hw/ppc/e500: Reduce usage of sysbus API
docs/system/ppc/ppce500: Add heading for networking chapter
hw/gpio/meson: Introduce dedicated config switch for hw/gpio/mpc8xxx
hw/ppc/meson: Allow e500 boards to be enabled separately
ppc440_uc.c: Remove unneeded parenthesis
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 214a8da23651f2472b296b3293e619fd58d9e212
https://github.com/qemu/qemu/commit/214a8da23651f2472b296b3293e619fd58d9e212
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-10-18 (Tue, 18 Oct 2022)
Changed paths:
M configure
M hw/i386/microvm.c
M hw/i386/pc.c
M hw/scsi/esp.c
M hw/scsi/lsi53c895a.c
M hw/scsi/megasas.c
M hw/scsi/mptsas.c
M hw/scsi/scsi-bus.c
M hw/scsi/spapr_vscsi.c
M hw/scsi/virtio-scsi.c
M hw/scsi/vmw_pvscsi.c
M include/hw/scsi/scsi.h
M target/i386/cpu-param.h
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/helper.c
M target/i386/helper.h
M target/i386/kvm/hyperv.c
M target/i386/kvm/kvm.c
M target/i386/kvm/kvm_i386.h
M target/i386/ops_sse.h
M target/i386/ops_sse_header.h
A target/i386/tcg/decode-new.c.inc
A target/i386/tcg/decode-new.h
A target/i386/tcg/emit.c.inc
M target/i386/tcg/fpu_helper.c
M target/i386/tcg/sysemu/excp_helper.c
M target/i386/tcg/sysemu/svm_helper.c
M target/i386/tcg/translate.c
M tests/tcg/i386/Makefile.target
M tests/tcg/i386/test-avx.c
M tests/tcg/i386/test-avx.py
Log Message:
-----------
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* configure: don't enable firmware for targets that are not built
* configure: don't use strings(1)
* scsi, target/i386: switch from device_legacy_reset() to device_cold_reset()
* target/i386: AVX support for TCG
* target/i386: fix SynIC SINT assertion failure on guest reset
* target/i386: Use atomic operations for pte updates and other cleanups
* tests/tcg: extend SSE tests to AVX
* virtio-scsi: send "REPORTED LUNS CHANGED" sense data upon disk hotplug events
# -----BEGIN PGP SIGNATURE-----
#
# iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmNOlOcUHHBib256aW5p
# QHJlZGhhdC5jb20ACgkQv/vSX3jHroNuvwgAj/Z5pI9KU33XiWKFR3bZf2lHh21P
# xmTzNtPmnP1WHDY1DNug/UB+BLg3c+carpTf5n3B8aKI4X3FfxGSJvYlXy4BONFD
# XqYMH3OZB5GaR8Wza9trNYjDs/9hOZus/0R6Hqdl/T38PlMjf8mmayULJIGdcFcJ
# WJvITVntbcCwwbpyJbRC5BNigG8ZXTNRoKBgtFVGz6Ox+n0YydwKX5qU5J7xRfCU
# lW41LjZ0Fk5lonH16+xuS4WD5EyrNt8cMKCGsxnyxhI7nehe/OGnYr9l+xZJclrh
# inQlSwJv0IpUJcrGCI4Xugwux4Z7ZXv3JQ37FzsdZcv/ZXpGonXMeXNJ9A==
# =o6x7
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 18 Oct 2022 07:58:31 EDT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (53 commits)
target/i386: remove old SSE decoder
target/i386: move 3DNow to the new decoder
tests/tcg: extend SSE tests to AVX
target/i386: Enable AVX cpuid bits when using TCG
target/i386: implement VLDMXCSR/VSTMXCSR
target/i386: implement XSAVE and XRSTOR of AVX registers
target/i386: reimplement 0x0f 0x28-0x2f, add AVX
target/i386: reimplement 0x0f 0x10-0x17, add AVX
target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, add AVX
target/i386: reimplement 0x0f 0x38, add AVX
target/i386: Use tcg gvec ops for pmovmskb
target/i386: reimplement 0x0f 0x3a, add AVX
target/i386: clarify (un)signedness of immediates from 0F3Ah opcodes
target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVX
target/i386: reimplement 0x0f 0x70-0x77, add AVX
target/i386: reimplement 0x0f 0x78-0x7f, add AVX
target/i386: reimplement 0x0f 0x50-0x5f, add AVX
target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, add AVX
target/i386: reimplement 0x0f 0x60-0x6f, add AVX
target/i386: Introduce 256-bit vector helpers
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/8823ef1336d6...214a8da23651