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[Qemu-commits] [qemu/qemu] a50d08: m68k: rework BI_VIRT_RNG_SEED as BI_R

From: Paolo Bonzini
Subject: [Qemu-commits] [qemu/qemu] a50d08: m68k: rework BI_VIRT_RNG_SEED as BI_RNG_SEED
Date: Sun, 16 Oct 2022 08:41:14 -0700 
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: a50d0868f25b42cde2d3ffe5170747c48f96c5a3
      
https://github.com/qemu/qemu/commit/a50d0868f25b42cde2d3ffe5170747c48f96c5a3
  Author: Jason A. Donenfeld <Jason@zx2c4.com>
  Date:   2022-10-11 (Tue, 11 Oct 2022)

  Changed paths:
    M hw/m68k/q800.c
    M hw/m68k/virt.c
    M include/standard-headers/asm-m68k/bootinfo-virt.h
    M include/standard-headers/asm-m68k/bootinfo.h

  Log Message:
  -----------
  m68k: rework BI_VIRT_RNG_SEED as BI_RNG_SEED

Following a change on the kernel side (see link), pass BI_RNG_SEED
instead of BI_VIRT_RNG_SEED. This should have no impact on
compatibility, as there will simply be no effect if it's an old kernel,
which is how things have always been. We then use this as an opportunity
to add this to q800, since now we can, which is a nice improvement.

Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Laurent Vivier <laurent@vivier.eu>
Link: https://lore.kernel.org/lkml/20220923170340.4099226-3-Jason@zx2c4.com/
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Message-Id: <20220926113900.1256630-1-Jason@zx2c4.com>
[lv: s/^I/         /g]
Signed-off-by: Laurent Vivier <laurent@vivier.eu>


  Commit: fa327be58280f76d2565ff0bdb9b0010ac97c3b0
      
https://github.com/qemu/qemu/commit/fa327be58280f76d2565ff0bdb9b0010ac97c3b0
  Author: Jason A. Donenfeld <Jason@zx2c4.com>
  Date:   2022-10-11 (Tue, 11 Oct 2022)

  Changed paths:
    M hw/m68k/bootinfo.h
    M hw/m68k/q800.c
    M hw/m68k/virt.c

  Log Message:
  -----------
  m68k: write bootinfo as rom section and re-randomize on reboot

Rather than poking directly into RAM, add the bootinfo block as a proper
ROM, so that it's restored when rebooting the system. This way, if the
guest corrupts any of the bootinfo items, but then tries to reboot,
it'll still be restored back to normal as expected.

Then, since the RNG seed needs to be fresh on each boot, regenerate the
RNG seed in the ROM when reseting the CPU.

Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Message-Id: <20221003110221.971024-1-Jason@zx2c4.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>


  Commit: 838f717b22fb942f488f2bf5d1cd943736c8eae5
      
https://github.com/qemu/qemu/commit/838f717b22fb942f488f2bf5d1cd943736c8eae5
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2022-10-14 (Fri, 14 Oct 2022)

  Changed paths:
    M hw/riscv/boot.c

  Log Message:
  -----------
  hw/riscv: Update comment for qtest check in riscv_find_firmware()

Since commit 4211fc553234 ("roms/opensbi: Remove ELF images"), the
comment for qtest check in riscv_find_firmware() is out of date.
Update it to reflect the latest status.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: 
<BN7PR08MB435525C92550BAC5467BE672BF219@BN7PR08MB4355.namprd08.prod.outlook.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ff3809ef34d39a2b42f0ced5f5f90c36bd550cc9
      
https://github.com/qemu/qemu/commit/ff3809ef34d39a2b42f0ced5f5f90c36bd550cc9
  Author: Wilfred Mallawa <wilfred.mallawa@wdc.com>
  Date:   2022-10-14 (Fri, 14 Oct 2022)

  Changed paths:
    M hw/ssi/ibex_spi_host.c

  Log Message:
  -----------
  hw/ssi: ibex_spi: fixup coverity issue

This patch addresses the coverity issues specified in [1],
as suggested, `FIELD_DP32()`/`FIELD_EX32()` macros have been
implemented to clean up the code.

[1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg887713.html

Fixes: Coverity CID 1488107

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-Id: <20220930033241.206581-2-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6c1876958bbb53396655777401ab34207d0e1afa
      
https://github.com/qemu/qemu/commit/6c1876958bbb53396655777401ab34207d0e1afa
  Author: Wilfred Mallawa <wilfred.mallawa@wdc.com>
  Date:   2022-10-14 (Fri, 14 Oct 2022)

  Changed paths:
    M hw/ssi/ibex_spi_host.c
    M include/hw/ssi/ibex_spi_host.h

  Log Message:
  -----------
  hw/ssi: ibex_spi: fixup/add rw1c functionality

This patch adds the `rw1c` functionality to the respective
registers. The status fields are cleared when the respective
field is set.

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220930033241.206581-3-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 785a7383dd4832cc772a2c5483bd6fa40ee51302
      
https://github.com/qemu/qemu/commit/785a7383dd4832cc772a2c5483bd6fa40ee51302
  Author: Sunil V L <sunilvl@ventanamicro.com>
  Date:   2022-10-14 (Fri, 14 Oct 2022)

  Changed paths:
    M hw/arm/boot.c
    M hw/loongarch/virt.c
    M hw/nvram/fw_cfg.c
    M include/hw/nvram/fw_cfg.h

  Log Message:
  -----------
  hw/arm, loongarch: Move load_image_to_fw_cfg() to common location

load_image_to_fw_cfg() is duplicated by both arm and loongarch. The same
function will be required by riscv too. So, it's time to refactor and
move this function to a common path.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20221004092351.18209-2-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 90e26984eede1f4303572a39ee328f4c23b276a0
      
https://github.com/qemu/qemu/commit/90e26984eede1f4303572a39ee328f4c23b276a0
  Author: Sunil V L <sunilvl@ventanamicro.com>
  Date:   2022-10-14 (Fri, 14 Oct 2022)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: virt: Move create_fw_cfg() prior to loading kernel

To enable both -kernel and -pflash options, the fw_cfg needs to be
created prior to loading the kernel.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221004092351.18209-3-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a5b0249dfef6d39d345ed7c9620a04bdb1c2ffb0
      
https://github.com/qemu/qemu/commit/a5b0249dfef6d39d345ed7c9620a04bdb1c2ffb0
  Author: Sunil V L <sunilvl@ventanamicro.com>
  Date:   2022-10-14 (Fri, 14 Oct 2022)

  Changed paths:
    M hw/riscv/boot.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  hw/riscv: virt: Enable booting S-mode firmware from pflash

To boot S-mode firmware payload like EDK2 from persistent
flash storage, qemu needs to pass the flash address as the
next_addr in fw_dynamic_info to the opensbi.

When both -kernel and -pflash options are provided in command line,
the kernel (and initrd if -initrd) will be copied to fw_cfg table.
The S-mode FW will load the kernel/initrd from fw_cfg table.

If only pflash is given but not -kernel, then it is the job of
of the S-mode firmware to locate and load the kernel.

In either case, update the kernel_entry with the flash address
so that the opensbi can jump to the entry point of the S-mode
firmware.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221004092351.18209-4-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 07f4964d1785e9c230282074a5aef1eb7368d378
      
https://github.com/qemu/qemu/commit/07f4964d1785e9c230282074a5aef1eb7368d378
  Author: Yang Liu <liuyang22@iscas.ac.cn>
  Date:   2022-10-14 (Fri, 14 Oct 2022)

  Changed paths:
    M disas/riscv.c

  Log Message:
  -----------
  disas/riscv.c: rvv: Add disas support for vector instructions

Tested with https://github.com/ksco/rvv-decoder-tests

Expected checkpatch errors for consistency and brevity reasons:

ERROR: line over 90 characters
ERROR: trailing statements should be on next line
ERROR: braces {} are necessary for all arms of this statement

Signed-off-by: Yang Liu <liuyang22@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220928051842.16207-1-liuyang22@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 55144a1fd0d1f37b49ea051291decbbe427b7714
      
https://github.com/qemu/qemu/commit/55144a1fd0d1f37b49ea051291decbbe427b7714
  Author: Jim Shu <jim.shu@sifive.com>
  Date:   2022-10-14 (Fri, 14 Oct 2022)

  Changed paths:
    M hw/intc/sifive_plic.c

  Log Message:
  -----------
  hw/intc: sifive_plic: fix hard-coded max priority level

The maximum priority level is hard-coded when writing to interrupt
priority register. However, when writing to priority threshold register,
the maximum priority level is from num_priorities Property which is
configured by platform.

Also change interrupt priority register to use num_priorities Property
in maximum priority level.

Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221003041440.2320-2-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1aae4a12dab4bf1adc249c2ac6178d15e4b5a77d
      
https://github.com/qemu/qemu/commit/1aae4a12dab4bf1adc249c2ac6178d15e4b5a77d
  Author: Jim Shu <jim.shu@sifive.com>
  Date:   2022-10-14 (Fri, 14 Oct 2022)

  Changed paths:
    M hw/intc/sifive_plic.c

  Log Message:
  -----------
  hw/intc: sifive_plic: change interrupt priority register to WARL field

PLIC spec [1] requires interrupt source priority registers are WARL
field and the number of supported priority is power-of-2 to simplify SW
discovery.

Existing QEMU RISC-V machine (e.g. shakti_c) don't strictly follow PLIC
spec, whose number of supported priority is not power-of-2. Just change
each bit of interrupt priority register to WARL field when the number of
supported priority is power-of-2.

[1] 
https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-priorities

Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Clément Chigot <chigot@adacore.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221003041440.2320-3-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 47566421f029b0a489b63f8195b3ff944e017056
      
https://github.com/qemu/qemu/commit/47566421f029b0a489b63f8195b3ff944e017056
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2022-10-14 (Fri, 14 Oct 2022)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  target/riscv: pmp: Fixup TLB size calculation

Since commit 4047368938f6 "accel/tcg: Introduce tlb_set_page_full" we
have been seeing this assert

    ../accel/tcg/cputlb.c:1294: tlb_set_page_with_attrs: Assertion 
`is_power_of_2(size)' failed.

When running Tock on the OpenTitan machine.

The issue is that pmp_get_tlb_size() would return a TLB size that wasn't
a power of 2. The size was also smaller then TARGET_PAGE_SIZE.

This patch ensures that any TLB size less then TARGET_PAGE_SIZE is
rounded down to 1 to ensure it's a valid size.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei<zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221012011449.506928-1-alistair.francis@opensource.wdc.com
Message-Id: <20221012011449.506928-1-alistair.francis@opensource.wdc.com>


  Commit: e4a6ba3b3f7e65842508dd591e120fe5a6d92782
      
https://github.com/qemu/qemu/commit/e4a6ba3b3f7e65842508dd591e120fe5a6d92782
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2022-10-16 (Sun, 16 Oct 2022)

  Changed paths:
    M hw/m68k/bootinfo.h
    M hw/m68k/q800.c
    M hw/m68k/virt.c
    M include/standard-headers/asm-m68k/bootinfo-virt.h
    M include/standard-headers/asm-m68k/bootinfo.h

  Log Message:
  -----------
  Merge tag 'm68k-for-7.2-pull-request' of https://github.com/vivier/qemu-m68k 
into staging

Pull request m68k branch 20221014

Update rng seed boot parameter

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# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 14 Oct 2022 03:23:46 EDT
# gpg:                using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg:                issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" 
[full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* tag 'm68k-for-7.2-pull-request' of https://github.com/vivier/qemu-m68k:
  m68k: write bootinfo as rom section and re-randomize on reboot
  m68k: rework BI_VIRT_RNG_SEED as BI_RNG_SEED

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


  Commit: c7829015c8d6c6d45dcf10330fbdf6b9f1208149
      
https://github.com/qemu/qemu/commit/c7829015c8d6c6d45dcf10330fbdf6b9f1208149
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2022-10-16 (Sun, 16 Oct 2022)

  Changed paths:
    M disas/riscv.c
    M hw/arm/boot.c
    M hw/intc/sifive_plic.c
    M hw/loongarch/virt.c
    M hw/nvram/fw_cfg.c
    M hw/riscv/boot.c
    M hw/riscv/virt.c
    M hw/ssi/ibex_spi_host.c
    M include/hw/nvram/fw_cfg.h
    M include/hw/riscv/boot.h
    M include/hw/ssi/ibex_spi_host.h
    M target/riscv/pmp.c

  Log Message:
  -----------
  Merge tag 'pull-riscv-to-apply-20221014' of 
https://github.com/alistair23/qemu into staging

Third RISC-V PR for QEMU 7.2

* Update qtest comment
* Fix coverity issue with Ibex SPI
* Move load_image_to_fw_cfg() to common location
* Enable booting S-mode firmware from pflash on virt machine
* Add disas support for vector instructions
* Priority level fixes for PLIC
* Fixup TLB size calculation when using PMP

# -----BEGIN PGP SIGNATURE-----
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# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 14 Oct 2022 03:51:59 EDT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20221014' of https://github.com/alistair23/qemu:
  target/riscv: pmp: Fixup TLB size calculation
  hw/intc: sifive_plic: change interrupt priority register to WARL field
  hw/intc: sifive_plic: fix hard-coded max priority level
  disas/riscv.c: rvv: Add disas support for vector instructions
  hw/riscv: virt: Enable booting S-mode firmware from pflash
  hw/riscv: virt: Move create_fw_cfg() prior to loading kernel
  hw/arm, loongarch: Move load_image_to_fw_cfg() to common location
  hw/ssi: ibex_spi: fixup/add rw1c functionality
  hw/ssi: ibex_spi: fixup coverity issue
  hw/riscv: Update comment for qtest check in riscv_find_firmware()

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


Compare: https://github.com/qemu/qemu/compare/2ba341b3694c...c7829015c8d6
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