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[Qemu-commits] [qemu/qemu] b77252: Hexagon (target/hexagon) add instruct
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From: |
Paolo Bonzini |
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Subject: |
[Qemu-commits] [qemu/qemu] b77252: Hexagon (target/hexagon) add instruction attribute... |
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Date: |
Wed, 05 Oct 2022 10:55:37 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: b772528acbd4669a56c8bbc16d78f8f4335c1aa3
https://github.com/qemu/qemu/commit/b772528acbd4669a56c8bbc16d78f8f4335c1aa3
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2022-09-30 (Fri, 30 Sep 2022)
Changed paths:
M target/hexagon/attribs_def.h.inc
M target/hexagon/imported/ldst.idef
M target/hexagon/imported/subinsns.idef
Log Message:
-----------
Hexagon (target/hexagon) add instruction attributes from archlib
The imported files from the architecture library have added some
instruction attributes. Some of these will be used in a subsequent
patch for determing the size of a store.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220920080746.26791-2-tsimpson@quicinc.com>
Commit: e2be9a5c5f65a2cbde4915e29a112439177656d7
https://github.com/qemu/qemu/commit/e2be9a5c5f65a2cbde4915e29a112439177656d7
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2022-09-30 (Fri, 30 Sep 2022)
Changed paths:
M target/hexagon/attribs_def.h.inc
M target/hexagon/decode.c
M target/hexagon/hex_common.py
M target/hexagon/translate.c
Log Message:
-----------
Hexagon (target/hexagon) Change decision to set pkt_has_store_s[01]
We have found cases where pkt_has_store_s[01] is set incorrectly.
This leads to generating an unnecessary store that is left over
from a previous packet.
Add an attribute to determine if an instruction is a scalar store
The attribute is attached to the fSTORE macro (hex_common.py)
Update the logic in decode.c that sets pkt_has_store_s[01]
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220920080746.26791-4-tsimpson@quicinc.com>
Commit: 661ad999c554d1cc99ff96b3baf3ff4acbe2ecee
https://github.com/qemu/qemu/commit/661ad999c554d1cc99ff96b3baf3ff4acbe2ecee
Author: Taylor Simpson <tsimpson@quicinc.com>
Date: 2022-09-30 (Fri, 30 Sep 2022)
Changed paths:
M target/hexagon/genptr.c
M target/hexagon/macros.h
M target/hexagon/translate.c
Log Message:
-----------
Hexagon (target/hexagon) move store size tracking to translation
The store width is needed for packet commit, so it is stored in
ctx->store_width. Currently, it is set when a store has a TCG
override instead of a QEMU helper. In the QEMU helper case, the
ctx->store_width is not set, we invoke a helper during packet commit
that uses the runtime store width.
This patch ensures ctx->store_width is set for all store instructions,
so performance is improved because packet commit can generate the proper
TCG store rather than the generic helper.
We do this by
- Use the attributes from the instructions during translation to
set ctx->store_width
- Remove setting of ctx->store_width from genptr.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220920080746.26791-3-tsimpson@quicinc.com>
Commit: 772b3eb4b4fe15f0595bd95923778a5a0f3558cc
https://github.com/qemu/qemu/commit/772b3eb4b4fe15f0595bd95923778a5a0f3558cc
Author: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Date: 2022-10-03 (Mon, 03 Oct 2022)
Changed paths:
M target/hexagon/gen_tcg_funcs.py
Log Message:
-----------
Hexagon (gen_tcg_funcs.py): avoid duplicated tcg code on A_CVI_NEW
Hexagon instructions with the A_CVI_NEW attribute produce a vector value
that can be used in the same packet. The python function responsible for
generating code for such instructions has a typo ("if" instead of
"elif"), which makes genptr_dst_write_ext() be executed twice, thus also
generating the same tcg code twice. Fortunately, this doesn't cause any
problems for correctness, but it is less efficient than it could be. Fix
it by using an "elif" and avoiding the unnecessary extra code gen.
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id:
<fa706b192b2a3a0ffbd399fa8dbf0d5b2c5b82d9.1664568492.git.quic_mathbern@quicinc.com>
Commit: 6fbdff870620705042a5b2d87491659487b3f4e2
https://github.com/qemu/qemu/commit/6fbdff870620705042a5b2d87491659487b3f4e2
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-10-03 (Mon, 03 Oct 2022)
Changed paths:
M cpu.c
M include/hw/core/cpu.h
Log Message:
-----------
cpu: cache CPUClass in CPUState for hot code paths
The class cast checkers are quite expensive and always on (unlike the
dynamic case who's checks are gated by CONFIG_QOM_CAST_DEBUG). To
avoid the overhead of repeatedly checking something which should never
change we cache the CPUClass reference for use in the hot code paths.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220811151413.3350684-3-alex.bennee@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220923084803.498337-3-clg@kaod.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b404ca370e4ee60e98effec5cdf942d15b61c507
https://github.com/qemu/qemu/commit/b404ca370e4ee60e98effec5cdf942d15b61c507
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-10-03 (Mon, 03 Oct 2022)
Changed paths:
M hw/core/cpu-sysemu.c
Log Message:
-----------
hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs
This is a heavily used function so lets avoid the cost of
CPU_GET_CLASS. On the romulus-bmc run it has a modest effect:
Before: 36.812 s ± 0.506 s
After: 35.912 s ± 0.168 s
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220811151413.3350684-4-alex.bennee@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220923084803.498337-4-clg@kaod.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 8810ee2ac0899356013f56db6ea5f3e5023fbef6
https://github.com/qemu/qemu/commit/8810ee2ac0899356013f56db6ea5f3e5023fbef6
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-10-03 (Mon, 03 Oct 2022)
Changed paths:
M accel/tcg/cputlb.c
Log Message:
-----------
cputlb: used cached CPUClass in our hot-paths
Before: 35.912 s ± 0.168 s
After: 35.565 s ± 0.087 s
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220811151413.3350684-5-alex.bennee@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220923084803.498337-5-clg@kaod.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 25d3ec5831e08ed3e72a5db654d7c281feb559c7
https://github.com/qemu/qemu/commit/25d3ec5831e08ed3e72a5db654d7c281feb559c7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-03 (Mon, 03 Oct 2022)
Changed paths:
M accel/tcg/cputlb.c
M include/exec/cpu-defs.h
M target/arm/mte_helper.c
M target/arm/sve_helper.c
M target/arm/translate-a64.c
Log Message:
-----------
accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull
This structure will shortly contain more than just
data for accessing MMIO. Rename the 'addr' member
to 'xlat_section' to more clearly indicate its purpose.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 37523ff734721a699d338f918e95b1697cb0880c
https://github.com/qemu/qemu/commit/37523ff734721a699d338f918e95b1697cb0880c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-03 (Mon, 03 Oct 2022)
Changed paths:
M accel/tcg/cputlb.c
M include/hw/core/cpu.h
Log Message:
-----------
accel/tcg: Drop addr member from SavedIOTLB
This field is only written, not read; remove it.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c3c8bf579b431b6b305dce12d67ff6fe86bc79e8
https://github.com/qemu/qemu/commit/c3c8bf579b431b6b305dce12d67ff6fe86bc79e8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-03 (Mon, 03 Oct 2022)
Changed paths:
M accel/tcg/cputlb.c
M target/s390x/tcg/mem_helper.c
Log Message:
-----------
accel/tcg: Suppress auto-invalidate in probe_access_internal
When PAGE_WRITE_INV is set when calling tlb_set_page,
we immediately set TLB_INVALID_MASK in order to force
tlb_fill to be called on the next lookup. Here in
probe_access_internal, we have just called tlb_fill
and eliminated true misses, thus the lookup must be valid.
This allows us to remove a warning comment from s390x.
There doesn't seem to be a reason to change the code though.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: af803a4fcb1c707a6a885b5736335baf794f7676
https://github.com/qemu/qemu/commit/af803a4fcb1c707a6a885b5736335baf794f7676
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-03 (Mon, 03 Oct 2022)
Changed paths:
M accel/tcg/cputlb.c
M include/exec/exec-all.h
M include/qemu/typedefs.h
Log Message:
-----------
accel/tcg: Introduce probe_access_full
Add an interface to return the CPUTLBEntryFull struct
that goes with the lookup. The result is not intended
to be valid across multiple lookups, so the user must
use the results immediately.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4047368938f64e2b79103c6e6358b06570b237e5
https://github.com/qemu/qemu/commit/4047368938f64e2b79103c6e6358b06570b237e5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-03 (Mon, 03 Oct 2022)
Changed paths:
M accel/tcg/cputlb.c
M include/exec/cpu-defs.h
M include/exec/exec-all.h
Log Message:
-----------
accel/tcg: Introduce tlb_set_page_full
Now that we have collected all of the page data into
CPUTLBEntryFull, provide an interface to record that
all in one go, instead of using 4 arguments. This interface
allows CPUTLBEntryFull to be extended without having to
change the number of arguments.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 8c6953cf034cec0998815961e5ec70c9de15da6e
https://github.com/qemu/qemu/commit/8c6953cf034cec0998815961e5ec70c9de15da6e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-03 (Mon, 03 Oct 2022)
Changed paths:
M include/exec/cpu-defs.h
Log Message:
-----------
include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA
Allow the target to cache items from the guest page tables.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6981f7026af3507f0bac6a16ae3b098fae12beb2
https://github.com/qemu/qemu/commit/6981f7026af3507f0bac6a16ae3b098fae12beb2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-03 (Mon, 03 Oct 2022)
Changed paths:
M accel/tcg/translate-all.c
Log Message:
-----------
accel/tcg: Remove PageDesc code_bitmap
This bitmap is created and discarded immediately.
We gain nothing by its existence.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822232338.1727934-2-richard.henderson@linaro.org>
Commit: f79542afa798e1a6f7056b82c9a7e933242dd81b
https://github.com/qemu/qemu/commit/f79542afa798e1a6f7056b82c9a7e933242dd81b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-03 (Mon, 03 Oct 2022)
Changed paths:
M accel/tcg/translate-all.c
Log Message:
-----------
accel/tcg: Use bool for page_find_alloc
Bool is more appropriate type for the alloc parameter.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b21af662c15522b83a973bc2ffd51d0117c0e039
https://github.com/qemu/qemu/commit/b21af662c15522b83a973bc2ffd51d0117c0e039
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-03 (Mon, 03 Oct 2022)
Changed paths:
M accel/tcg/plugin-gen.c
M accel/tcg/translator.c
M include/exec/plugin-gen.h
Log Message:
-----------
accel/tcg: Use DisasContextBase in plugin_gen_tb_start
Use the pc coming from db->pc_first rather than the TB.
Use the cached host_addr rather than re-computing for the
first page. We still need a separate lookup for the second
page because it won't be computed for DisasContextBase until
the translator actually performs a read from the page.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 93b996161b54860ded173f54ed96257717bb9728
https://github.com/qemu/qemu/commit/93b996161b54860ded173f54ed96257717bb9728
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-04 (Tue, 04 Oct 2022)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/cputlb.c
M accel/tcg/translate-all.c
Log Message:
-----------
accel/tcg: Do not align tb->page_addr[0]
Let tb->page_addr[0] contain the address of the first byte of the
translated block, rather than the address of the page containing the
start of the translated block. We need to recover this value anyway
at various points, and it is easier to discard a page offset when it
is not needed, which happens naturally via the existing find_page shift.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 1d41a79b3c7573c941723455149cfadfe7c2ab37
https://github.com/qemu/qemu/commit/1d41a79b3c7573c941723455149cfadfe7c2ab37
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-04 (Tue, 04 Oct 2022)
Changed paths:
M accel/tcg/cputlb.c
Log Message:
-----------
accel/tcg: Inline tb_flush_jmp_cache
This function has two users, who use it incompatibly.
In tlb_flush_page_by_mmuidx_async_0, when flushing a
single page, we need to flush exactly two pages.
In tlb_flush_range_by_mmuidx_async_0, when flushing a
range of pages, we need to flush N+1 pages.
This avoids double-flushing of jmp cache pages in a range.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a976a99a29755e8c7a275ac269db8a0a20d79e95
https://github.com/qemu/qemu/commit/a976a99a29755e8c7a275ac269db8a0a20d79e95
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-04 (Tue, 04 Oct 2022)
Changed paths:
M accel/stubs/tcg-stub.c
M accel/tcg/cpu-exec.c
M accel/tcg/cputlb.c
M accel/tcg/tb-hash.h
A accel/tcg/tb-jmp-cache.h
M accel/tcg/translate-all.c
M hw/core/cpu-common.c
M include/exec/cpu-common.h
M include/hw/core/cpu.h
M include/qemu/typedefs.h
M plugins/core.c
M trace/control-target.c
Log Message:
-----------
include/hw/core: Create struct CPUJumpCache
Wrap the bare TranslationBlock pointer into a structure.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e4fdf9df5b1c2aa427de796bea973520027ddd15
https://github.com/qemu/qemu/commit/e4fdf9df5b1c2aa427de796bea973520027ddd15
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-04 (Tue, 04 Oct 2022)
Changed paths:
M include/hw/core/cpu.h
M target/alpha/cpu.c
M target/arm/cpu.c
M target/avr/cpu.c
M target/cris/cpu.c
M target/hexagon/cpu.c
M target/hppa/cpu.c
M target/i386/cpu.c
M target/loongarch/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/nios2/cpu.c
M target/openrisc/cpu.c
M target/ppc/cpu_init.c
M target/riscv/cpu.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/sh4/cpu.c
M target/sparc/cpu.c
M target/tricore/cpu.c
M target/xtensa/cpu.c
Log Message:
-----------
hw/core: Add CPUClass.get_pc
Populate this new method for all targets. Always match
the result that would be given by cpu_get_tb_cpu_state,
as we will want these values to correspond in the logs.
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (target/sparc)
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: Eduardo Habkost <eduardo@habkost.net> (supporter:Machine core)
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> (supporter:Machine core)
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org> (reviewer:Machine core)
Cc: Yanan Wang <wangyanan55@huawei.com> (reviewer:Machine core)
Cc: Michael Rolnik <mrolnik@gmail.com> (maintainer:AVR TCG CPUs)
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> (maintainer:CRIS TCG CPUs)
Cc: Taylor Simpson <tsimpson@quicinc.com> (supporter:Hexagon TCG CPUs)
Cc: Song Gao <gaosong@loongson.cn> (maintainer:LoongArch TCG CPUs)
Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn> (maintainer:LoongArch TCG CPUs)
Cc: Laurent Vivier <laurent@vivier.eu> (maintainer:M68K TCG CPUs)
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> (reviewer:MIPS TCG CPUs)
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> (reviewer:MIPS TCG CPUs)
Cc: Chris Wulff <crwulff@gmail.com> (maintainer:NiosII TCG CPUs)
Cc: Marek Vasut <marex@denx.de> (maintainer:NiosII TCG CPUs)
Cc: Stafford Horne <shorne@gmail.com> (odd fixer:OpenRISC TCG CPUs)
Cc: Yoshinori Sato <ysato@users.sourceforge.jp> (reviewer:RENESAS RX CPUs)
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (maintainer:SPARC TCG CPUs)
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (maintainer:TriCore TCG
CPUs)
Cc: Max Filippov <jcmvbkbc@gmail.com> (maintainer:Xtensa TCG CPUs)
Cc: qemu-arm@nongnu.org (open list:ARM TCG CPUs)
Cc: qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs)
Cc: qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs)
Cc: qemu-s390x@nongnu.org (open list:S390 TCG CPUs)
Commit: fbf59aad178d98afe193fa872a2d880266a75269
https://github.com/qemu/qemu/commit/fbf59aad178d98afe193fa872a2d880266a75269
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-04 (Tue, 04 Oct 2022)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/internal.h
M accel/tcg/translate-all.c
M include/exec/exec-all.h
M include/tcg/tcg.h
M target/arm/cpu.c
M target/avr/cpu.c
M target/hexagon/cpu.c
M target/hppa/cpu.c
M target/i386/tcg/tcg-cpu.c
M target/loongarch/cpu.c
M target/microblaze/cpu.c
M target/mips/tcg/exception.c
M target/mips/tcg/sysemu/special_helper.c
M target/openrisc/cpu.c
M target/riscv/cpu.c
M target/rx/cpu.c
M target/sh4/cpu.c
M target/sparc/cpu.c
M target/tricore/cpu.c
M tcg/tcg.c
Log Message:
-----------
accel/tcg: Introduce tb_pc and log_pc
The availability of tb->pc will shortly be conditional.
Introduce accessor functions to minimize ifdefs.
Pass around a known pc to places like tcg_gen_code,
where the caller must already have the value.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 8ed558ec0cbcc29ecf490e93c54dd65d276e8e69
https://github.com/qemu/qemu/commit/8ed558ec0cbcc29ecf490e93c54dd65d276e8e69
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-04 (Tue, 04 Oct 2022)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/internal.h
M accel/tcg/tb-jmp-cache.h
M accel/tcg/translate-all.c
M include/exec/cpu-defs.h
M include/exec/exec-all.h
Log Message:
-----------
accel/tcg: Introduce TARGET_TB_PCREL
Prepare for targets to be able to produce TBs that can
run in more than one virtual context.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 20add588296a8a24374004e9dbf6219f28665d34
https://github.com/qemu/qemu/commit/20add588296a8a24374004e9dbf6219f28665d34
Author: Leandro Lupori <leandro.lupori@eldorado.org.br>
Date: 2022-10-04 (Tue, 04 Oct 2022)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Optimize 26-bit jumps
PowerPC64 processors handle direct branches better than indirect
ones, resulting in less stalled cycles and branch misses.
However, PPC's tb_target_set_jmp_target() was only using direct
branches for 16-bit jumps, while PowerPC64's unconditional branch
instructions are able to handle displacements of up to 26 bits.
To take advantage of this, now jumps whose displacements fit in
between 17 and 26 bits are also converted to direct branches.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
[rth: Expanded some commentary.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ab419fd8a035a65942de4e63effcd55ccbf1a9fe
https://github.com/qemu/qemu/commit/ab419fd8a035a65942de4e63effcd55ccbf1a9fe
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-10-04 (Tue, 04 Oct 2022)
Changed paths:
M linux-user/sh4/signal.c
M target/sh4/cpu.c
M target/sh4/cpu.h
M target/sh4/helper.c
M target/sh4/translate.c
Log Message:
-----------
target/sh4: Fix TB_FLAG_UNALIGN
The value previously chosen overlaps GUSA_MASK.
Rename all DELAY_SLOT_* and GUSA_* defines to emphasize
that they are included in TB_FLAGs. Add aliases for the
FPSCR and SR bits that are included in TB_FLAGS, so that
we don't accidentally reassign those bits.
Fixes: 4da06fb3062 ("target/sh4: Implement prctl_unalign_sigbus")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/856
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4a9c04672a875ed00ea807ea4d552c01f6440bc7
https://github.com/qemu/qemu/commit/4a9c04672a875ed00ea807ea4d552c01f6440bc7
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-10-05 (Wed, 05 Oct 2022)
Changed paths:
M accel/stubs/tcg-stub.c
M accel/tcg/cpu-exec.c
M accel/tcg/cputlb.c
M accel/tcg/internal.h
M accel/tcg/plugin-gen.c
M accel/tcg/tb-hash.h
A accel/tcg/tb-jmp-cache.h
M accel/tcg/translate-all.c
M accel/tcg/translator.c
M cpu.c
M hw/core/cpu-common.c
M hw/core/cpu-sysemu.c
M include/exec/cpu-common.h
M include/exec/cpu-defs.h
M include/exec/exec-all.h
M include/exec/plugin-gen.h
M include/hw/core/cpu.h
M include/qemu/typedefs.h
M include/tcg/tcg.h
M linux-user/sh4/signal.c
M plugins/core.c
M target/alpha/cpu.c
M target/arm/cpu.c
M target/arm/mte_helper.c
M target/arm/sve_helper.c
M target/arm/translate-a64.c
M target/avr/cpu.c
M target/cris/cpu.c
M target/hexagon/cpu.c
M target/hppa/cpu.c
M target/i386/cpu.c
M target/i386/tcg/tcg-cpu.c
M target/loongarch/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/mips/tcg/exception.c
M target/mips/tcg/sysemu/special_helper.c
M target/nios2/cpu.c
M target/openrisc/cpu.c
M target/ppc/cpu_init.c
M target/riscv/cpu.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/s390x/tcg/mem_helper.c
M target/sh4/cpu.c
M target/sh4/cpu.h
M target/sh4/helper.c
M target/sh4/translate.c
M target/sparc/cpu.c
M target/tricore/cpu.c
M target/xtensa/cpu.c
M tcg/ppc/tcg-target.c.inc
M tcg/tcg.c
M trace/control-target.c
Log Message:
-----------
Merge tag 'pull-tcg-20221004' of https://gitlab.com/rth7680/qemu into staging
Cache CPUClass for use in hot code paths.
Add CPUTLBEntryFull, probe_access_full, tlb_set_page_full.
Add generic support for TARGET_TB_PCREL.
tcg/ppc: Optimize 26-bit jumps using STQ for POWER 2.07
target/sh4: Fix TB_FLAG_UNALIGN
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# gpg: Signature made Tue 04 Oct 2022 15:45:53 EDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20221004' of https://gitlab.com/rth7680/qemu:
target/sh4: Fix TB_FLAG_UNALIGN
tcg/ppc: Optimize 26-bit jumps
accel/tcg: Introduce TARGET_TB_PCREL
accel/tcg: Introduce tb_pc and log_pc
hw/core: Add CPUClass.get_pc
include/hw/core: Create struct CPUJumpCache
accel/tcg: Inline tb_flush_jmp_cache
accel/tcg: Do not align tb->page_addr[0]
accel/tcg: Use DisasContextBase in plugin_gen_tb_start
accel/tcg: Use bool for page_find_alloc
accel/tcg: Remove PageDesc code_bitmap
include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA
accel/tcg: Introduce tlb_set_page_full
accel/tcg: Introduce probe_access_full
accel/tcg: Suppress auto-invalidate in probe_access_internal
accel/tcg: Drop addr member from SavedIOTLB
accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull
cputlb: used cached CPUClass in our hot-paths
hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs
cpu: cache CPUClass in CPUState for hot code paths
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 1dcdc92c72af5311666df64f5f04d6600af262ed
https://github.com/qemu/qemu/commit/1dcdc92c72af5311666df64f5f04d6600af262ed
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-10-05 (Wed, 05 Oct 2022)
Changed paths:
M target/hexagon/attribs_def.h.inc
M target/hexagon/decode.c
M target/hexagon/gen_tcg_funcs.py
M target/hexagon/genptr.c
M target/hexagon/hex_common.py
M target/hexagon/imported/ldst.idef
M target/hexagon/imported/subinsns.idef
M target/hexagon/macros.h
M target/hexagon/translate.c
Log Message:
-----------
Merge tag 'pull-hex-20221003' of https://github.com/quic/qemu into staging
Make store handling faster and more robust
Bug fix in gen_tcg_funcs.py
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# gpg: Signature made Mon 03 Oct 2022 14:08:46 EDT
# gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422
# gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>"
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422
* tag 'pull-hex-20221003' of https://github.com/quic/qemu:
Hexagon (gen_tcg_funcs.py): avoid duplicated tcg code on A_CVI_NEW
Hexagon (target/hexagon) move store size tracking to translation
Hexagon (target/hexagon) Change decision to set pkt_has_store_s[01]
Hexagon (target/hexagon) add instruction attributes from archlib
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/fafd35a6dab8...1dcdc92c72af