[Qemu-commits] [qemu/qemu] d1e23c: target/nios2: Use semihosting/syscalls.h

[Paolo Bonzini]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: d1e23cbaa403b2d816e1cb2acd61105d00c38b9b
      
https://github.com/qemu/qemu/commit/d1e23cbaa403b2d816e1cb2acd61105d00c38b9b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-09-13 (Tue, 13 Sep 2022)

  Changed paths:
    M target/nios2/nios2-semi.c

  Log Message:
  -----------
  target/nios2: Use semihosting/syscalls.h

This separates guest file descriptors from host file descriptors,
and utilizes shared infrastructure for integration with gdbstub.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 78c2c68ddac7b1a73615d89363fffd8c01561123
      
https://github.com/qemu/qemu/commit/78c2c68ddac7b1a73615d89363fffd8c01561123
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-09-13 (Tue, 13 Sep 2022)

  Changed paths:
    M target/nios2/nios2-semi.c

  Log Message:
  -----------
  target/nios2: Convert semihosting errno to gdb remote errno

The semihosting abi used by nios2 uses the gdb remote
protocol filesys errnos.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 950272506dbd8dcf8c74b63e9949d18397e6a0ec
      
https://github.com/qemu/qemu/commit/950272506dbd8dcf8c74b63e9949d18397e6a0ec
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-09-13 (Tue, 13 Sep 2022)

  Changed paths:
    M target/m68k/m68k-semi.c

  Log Message:
  -----------
  target/m68k: Use semihosting/syscalls.h

This separates guest file descriptors from host file descriptors,
and utilizes shared infrastructure for integration with gdbstub.

Acked-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 7327e60237c36e9aa089141de547ca224ec5f3be
      
https://github.com/qemu/qemu/commit/7327e60237c36e9aa089141de547ca224ec5f3be
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-09-13 (Tue, 13 Sep 2022)

  Changed paths:
    M target/m68k/m68k-semi.c

  Log Message:
  -----------
  target/m68k: Convert semihosting errno to gdb remote errno

The semihosting abi used by m68k uses the gdb remote
protocol filesys errnos.

Acked-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 5202861b20d77b1d638da5f10af0f51ebcfc61bf
      
https://github.com/qemu/qemu/commit/5202861b20d77b1d638da5f10af0f51ebcfc61bf
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-13 (Tue, 13 Sep 2022)

  Changed paths:
    M include/semihosting/semihost.h
    M qemu-options.hx
    M semihosting/config.c
    M softmmu/vl.c
    M stubs/semihost.c
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/m68k/op_helper.c
    M target/nios2/translate.c
    M target/xtensa/translate.c

  Log Message:
  -----------
  semihosting: Allow optional use of semihosting from userspace

Currently our semihosting implementations generally prohibit use of
semihosting calls in system emulation from the guest userspace.  This
is a very long standing behaviour justified originally "to provide
some semblance of security" (since code with access to the
semihosting ABI can do things like read and write arbitrary files on
the host system).  However, it is sometimes useful to be able to run
trusted guest code which performs semihosting calls from guest
userspace, notably for test code.  Add a command line suboption to
the existing semihosting-config option group so that you can
explicitly opt in to semihosting from guest userspace with
 -semihosting-config userspace=on

(There is no equivalent option for the user-mode emulator, because
there by definition all code runs in userspace and has access to
semihosting already.)

This commit adds the infrastructure for the command line option and
adds a bool 'is_user' parameter to the function
semihosting_userspace_enabled() that target code can use to check
whether it should be permitting the semihosting call for userspace.
It mechanically makes all the callsites pass 'false', so they
continue checking "is semihosting enabled in general".  Subsequent
commits will make each target that implements semihosting honour the
userspace=on option by passing the correct value and removing
whatever "don't do this for userspace" checking they were doing by
hand.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822141230.3658237-2-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 19b26317e9eb0c4dfd42e341ba7c4474c6d53ff9
      
https://github.com/qemu/qemu/commit/19b26317e9eb0c4dfd42e341ba7c4474c6d53ff9
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-13 (Tue, 13 Sep 2022)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Honour -semihosting-config userspace=on

Honour the commandline -semihosting-config userspace=on option,
instead of never permitting userspace semihosting calls in system
emulation mode, by passing the correct value to the is_userspace
argument of semihosting_enabled(), instead of manually checking and
always forbidding semihosting if the guest is in userspace and this
isn't the linux-user build.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822141230.3658237-3-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a52417e1eeb4501993e29145d16faac59e8465ca
      
https://github.com/qemu/qemu/commit/a52417e1eeb4501993e29145d16faac59e8465ca
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-13 (Tue, 13 Sep 2022)

  Changed paths:
    M target/m68k/op_helper.c

  Log Message:
  -----------
  target/m68k: Honour -semihosting-config userspace=on

Honour the commandline -semihosting-config userspace=on option,
instead of never permitting userspace semihosting calls in system
emulation mode, by passing the correct value to the is_userspace
argument of semihosting_enabled(), instead of manually checking and
always forbidding semihosting if the guest is in userspace.

(Note that target/m68k doesn't support semihosting at all
in the linux-user build.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822141230.3658237-4-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b35d74015b0262260b7dbb75c80ea85aeebab89b
      
https://github.com/qemu/qemu/commit/b35d74015b0262260b7dbb75c80ea85aeebab89b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-13 (Tue, 13 Sep 2022)

  Changed paths:
    M target/mips/tcg/micromips_translate.c.inc
    M target/mips/tcg/mips16e_translate.c.inc
    M target/mips/tcg/nanomips_translate.c.inc
    M target/mips/tcg/translate.c

  Log Message:
  -----------
  target/mips: Honour -semihosting-config userspace=on

Honour the commandline -semihosting-config userspace=on option,
instead of always permitting userspace semihosting calls in system
emulation mode, by passing the correct value to the is_userspace
argument of semihosting_enabled().

Note that this is a behaviour change: if the user wants to
do semihosting calls from userspace they must now specifically
enable them on the command line.

MIPS semihosting is not implemented for linux-user builds.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822141230.3658237-5-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: cab9f19370b5e26afbc7f62e08293507bf2a5f6b
      
https://github.com/qemu/qemu/commit/cab9f19370b5e26afbc7f62e08293507bf2a5f6b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-13 (Tue, 13 Sep 2022)

  Changed paths:
    M target/nios2/translate.c

  Log Message:
  -----------
  target/nios2: Honour -semihosting-config userspace=on

Honour the commandline -semihosting-config userspace=on option,
instead of always permitting userspace semihosting calls in system
emulation mode, by passing the correct value to the is_userspace
argument of semihosting_enabled().

Note that this is a behaviour change: if the user wants to
do semihosting calls from userspace they must now specifically
enable them on the command line.

nios2 semihosting is not implemented for linux-user builds.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822141230.3658237-6-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 870ab98bee4312caf0ced42999e295f741aba853
      
https://github.com/qemu/qemu/commit/870ab98bee4312caf0ced42999e295f741aba853
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-13 (Tue, 13 Sep 2022)

  Changed paths:
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: Honour -semihosting-config userspace=on

Honour the commandline -semihosting-config userspace=on option,
instead of always permitting userspace semihosting calls in system
emulation mode, by passing the correct value to the is_userspace
argument of semihosting_enabled().

Note that this is a behaviour change: if the user wants to
do semihosting calls from userspace they must now specifically
enable them on the command line.

xtensa semihosting is not implemented for linux-user builds.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822141230.3658237-7-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 7d7fb11615809839ff858328134c6a0abad27ea4
      
https://github.com/qemu/qemu/commit/7d7fb11615809839ff858328134c6a0abad27ea4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-13 (Tue, 13 Sep 2022)

  Changed paths:
    M target/riscv/cpu_helper.c
    M target/riscv/insn_trans/trans_privileged.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Honour -semihosting-config userspace=on and enable=on

The riscv target incorrectly enabled semihosting always, whether the
user asked for it or not.  Call semihosting_enabled() passing the
correct value to the is_userspace argument, which fixes this and also
handles the userspace=on argument.  Because we do this at translate
time, we no longer need to check the privilege level in
riscv_cpu_do_interrupt().

Note that this is a behaviour change: we used to default to
semihosting being enabled, and now the user must pass
"-semihosting-config enable=on" if they want it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220822141230.3658237-8-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3b16766b5ae7f61079e3ae674e140219c4cdbe85
      
https://github.com/qemu/qemu/commit/3b16766b5ae7f61079e3ae674e140219c4cdbe85
  Author: Hao Wu <wuhaotsh@google.com>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M docs/system/arm/virt.rst
    M hw/arm/virt.c
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Add cortex-a35

Add cortex A35 core and enable it for virt board.

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220819002015.1663247-1-wuhaotsh@google.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3b9a030e846dd42a53f9f5bdcdd0228bb898e01b
      
https://github.com/qemu/qemu/commit/3b9a030e846dd42a53f9f5bdcdd0228bb898e01b
  Author: Enrik Berkhan <Enrik.Berkhan@inka.de>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M hw/misc/bcm2835_property.c

  Log Message:
  -----------
  hw/arm/bcm2835_property: Add support for 
RPI_FIRMWARE_FRAMEBUFFER_GET_NUM_DISPLAYS

In more recent Raspbian OS Linux kernels, the fb driver gives up
immediately if RPI_FIRMWARE_FRAMEBUFFER_GET_NUM_DISPLAYS fails or no
displays are reported.

This change simply always reports one display. It makes bcm2835_fb work
again with these more recent kernels.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Enrik Berkhan <Enrik.Berkhan@inka.de>
Message-Id: <20220812143519.59134-1-Enrik.Berkhan@inka.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: dde4d028dc829cb70d285bb943ebdc049692fa27
      
https://github.com/qemu/qemu/commit/dde4d028dc829cb70d285bb943ebdc049692fa27
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Make cpregs 0, c0, c{3-15}, {0-7} correctly RAZ in v8

In the AArch32 ID register scheme, coprocessor registers with
encoding cp15, 0, c0, c{0-7}, {0-7} are all in the space covered by
what in v6 and v7 was called the "CPUID scheme", and are supposed to
RAZ if they're not allocated to a specific ID register.  For our
pre-v8 CPUs we get this right, because the regdefs in
id_pre_v8_midr_cp_reginfo[] cover these RAZ requirements.  However
for v8 we failed to put in the necessary patterns to cover this, so
we end up UNDEFing on everything we didn't have an ID register for.
This is a problem because in Armv8 some encodings in 0, c0, c3, {0-7}
are now being used for new ID registers, and guests might thus start
trying to read them.  (We already have one of these: ID_PFR2.)

For v8 CPUs, we already have regdefs for 0, c0, c{0-2}, {0-7} (that
is, the space is completely allocated with no reserved spaces).  Add
entries to v8_idregs[] covering 0, c0, c3, {0-7}:
 * c3, {0-2} is the reserved AArch32 space corresponding to the
   AArch64 MVFR[012]_EL1
 * c3, {3,5,6,7} are reserved RAZ for both AArch32 and AArch64
   (in fact some of these are given defined meanings in Armv8.6,
   but we don't implement them yet)
 * c3, 4 is ID_PFR2 (already defined)

We then programmatically add RAZ patterns for AArch32 for
0, c0, c{4..15}, {0-7}:
 * c4-c7 are unused, and not shared with AArch64 (these
   are the encodings corresponding to where the AArch64
   specific ID registers live in the system register space)
 * c8-c15 weren't required to RAZ in v6/v7, but v8 extends
   the AArch32 reserved-should-RAZ space to cover these;
   the equivalent area of the AArch64 sysreg space is not
   defined as must-RAZ

Note that the architecture allows some registers in this space
to return an UNKNOWN value; we always return 0.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220819110052.2942289-2-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 62b6f5e2f0a029810791dde6e02f86ad8575a02c
      
https://github.com/qemu/qemu/commit/62b6f5e2f0a029810791dde6e02f86ad8575a02c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M target/arm/kvm64.c

  Log Message:
  -----------
  target/arm: Sort KVM reads of AArch32 ID registers into encoding order

The code that reads the AArch32 ID registers from KVM in
kvm_arm_get_host_cpu_features() does so almost but not quite in
encoding order.  Move the read of ID_PFR2 down so it's really in
encoding order.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220819110052.2942289-3-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 32957aad8ce3cd4f923b464efb80645963479ff8
      
https://github.com/qemu/qemu/commit/32957aad8ce3cd4f923b464efb80645963479ff8
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/kvm64.c

  Log Message:
  -----------
  target/arm: Implement ID_MMFR5

In Armv8.6 a new AArch32 ID register ID_MMFR5 is defined.
Implement this; we want to be able to use it to report to
the guest that we implement FEAT_ETS.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220819110052.2942289-4-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d22c564958ffa6bd40be34c6ea3333ee7ef73b68
      
https://github.com/qemu/qemu/commit/d22c564958ffa6bd40be34c6ea3333ee7ef73b68
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/kvm64.c

  Log Message:
  -----------
  target/arm: Implement ID_DFR1

In Armv8.6, a new AArch32 ID register ID_DFR1 is defined; implement
it. We don't have any CPUs with features that they need to advertise
here yet, but plumbing in the ID register gives it the right name
when debugging and will help in future when we do add a CPU that
has non-zero ID_DFR1 fields.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220819110052.2942289-5-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3fe72e213eae33daaea88685878a571bd5ef3e08
      
https://github.com/qemu/qemu/commit/3fe72e213eae33daaea88685878a571bd5ef3e08
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M docs/system/arm/emulation.rst
    M target/arm/cpu64.c
    M target/arm/cpu_tcg.c

  Log Message:
  -----------
  target/arm: Advertise FEAT_ETS for '-cpu max'

The architectural feature FEAT_ETS (Enhanced Translation
Synchronization) is a set of tightened guarantees about memory
ordering involving translation table walks:

 * if memory access RW1 is ordered-before memory access RW2 then it
   is also ordered-before any translation table walk generated by RW2
   that generates a translation fault, address size fault or access
   fault

 * TLB maintenance on non-exec-permission translations is guaranteed
   complete after a DSB (ie it does not need the context
   synchronization event that you have to have if you don’t have
   FEAT_ETS)

For QEMU’s implementation we don’t reorder translation table walk
accesses, and we guarantee to finish the TLB maintenance as soon as
the TLB op is done (the tlb_flush functions will complete at the end
of the TLB, and TLB ops always end the TB because they’re sysreg
writes).

So we’re already compliant and all we need to do is say so in the ID
registers for the 'max' CPU.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220819110052.2942289-6-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: bb7d902154f7f17c9127631c42a21fbbc805cb40
      
https://github.com/qemu/qemu/commit/bb7d902154f7f17c9127631c42a21fbbc805cb40
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M target/arm/cpu_tcg.c

  Log Message:
  -----------
  target/arm: Add missing space in comment

Fix a missing space before a comment terminator.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220819110052.2942289-7-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 76e25d41d44c49eb0fe399064a719702a3023102
      
https://github.com/qemu/qemu/commit/76e25d41d44c49eb0fe399064a719702a3023102
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Don't corrupt high half of PMOVSR when cycle counter overflows

When the cycle counter overflows, we are intended to set bit 31 in PMOVSR
to indicate this. However a missing ULL suffix means that we end up
setting all of bits 63-31. Fix the bug.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822132358.3524971-2-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c117c0649ce4022f518a7f0bc14bf7b036c89de3
      
https://github.com/qemu/qemu/commit/c117c0649ce4022f518a7f0bc14bf7b036c89de3
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Correct value returned by pmu_counter_mask()

pmu_counter_mask() accidentally returns a value with bits [63:32]
set, because the expression it returns is evaluated as a signed value
that gets sign-extended to 64 bits.  Force the whole expression to be
evaluated with 64-bit arithmetic with ULL suffixes.

The main effect of this bug was that a guest could write to the bits
in the high half of registers like PMCNTENSET_EL0 that are supposed
to be RES0.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822132358.3524971-3-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 01765386a88868ae993bcbb39f111501fe690035
      
https://github.com/qemu/qemu/commit/01765386a88868ae993bcbb39f111501fe690035
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Don't mishandle count when enabling or disabling PMU counters

The PMU cycle and event counter infrastructure design requires that
operations on the PMU register fields are wrapped in pmu_op_start()
and pmu_op_finish() calls (or their more specific pmmcntr and
pmevcntr equivalents).  This includes any changes to registers which
affect whether the counter should be enabled or disabled, but we
forgot to do this.

The effect of this bug is that in sequences like:
 * disable the cycle counter (PMCCNTR) using the PMCNTEN register
 * write a value such as 0xfffff000 to the PMCCNTR
 * restart the counter by writing to PMCNTEN
the value written to the cycle counter is corrupted, and it starts
counting from the wrong place. (Essentially, we fail to record that
the QEMU_CLOCK_VIRTUAL timestamp when the counter should be considered
to have started counting is the point when PMCNTEN is written to enable
the counter.)

Add the necessary bracketing calls, so that updates to the various
registers which affect whether the PMU is counting are handled
correctly.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822132358.3524971-4-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b57aa7bdc3b4f16b216bd854e86431146729a640
      
https://github.com/qemu/qemu/commit/b57aa7bdc3b4f16b216bd854e86431146729a640
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Ignore PMCR.D when PMCR.LC is set

The architecture requires that if PMCR.LC is set (for a 64-bit cycle
counter) then PMCR.D (which enables the clock divider so the counter
ticks every 64 cycles rather than every cycle) should be ignored.  We
were always honouring PMCR.D; fix the bug so we correctly ignore it
in this situation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822132358.3524971-5-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 872d20343de4f1af45a31270f47cc54cc474bf55
      
https://github.com/qemu/qemu/commit/872d20343de4f1af45a31270f47cc54cc474bf55
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Honour MDCR_EL2.HPMD in Secure EL2

The logic in pmu_counter_enabled() for handling the 'prohibit event
counting' bits MDCR_EL2.HPMD and MDCR_EL3.SPME is written in a way
that assumes that EL2 is never Secure.  This used to be true, but the
architecture now permits Secure EL2, and QEMU can emulate this.

Refactor the prohibit logic so that we effectively OR together
the various prohibit bits when they apply, rather than trying to
construct an if-else ladder where any particular state of the CPU
ends up in exactly one branch of the ladder.

This fixes the Secure EL2 case and also is a better structure for
adding the PMUv8.5 bits MDCR_EL2.HCCD and MDCR_EL3.SCCD.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822132358.3524971-6-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f1dd2506ee75b21a604e5a8b6e1c0fd00a435f7e
      
https://github.com/qemu/qemu/commit/f1dd2506ee75b21a604e5a8b6e1c0fd00a435f7e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Detect overflow when calculating next PMU interrupt

In pmccntr_op_finish() and pmevcntr_op_finish() we calculate the next
point at which we will get an overflow and need to fire the PMU
interrupt or set the overflow flag.  We do this by calculating the
number of nanoseconds to the overflow event and then adding it to
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL).  However, we don't check
whether that signed addition overflows, which can happen if the next
PMU interrupt would happen massively far in the future (250 years or
more).

Since QEMU assumes that "when the QEMU_CLOCK_VIRTUAL rolls over" is
"never", the sensible behaviour in this situation is simply to not
try to set the timer if it would be beyond that point.  Detect the
overflow, and skip setting the timer in that case.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822132358.3524971-7-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a793bcd0272d9d25c942184ee18c7ed4dc75dc0d
      
https://github.com/qemu/qemu/commit/a793bcd0272d9d25c942184ee18c7ed4dc75dc0d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Rename pmu_8_n feature test functions

Our feature test functions that check the PMU version are named
isar_feature_{aa32,aa64,any}_pmu_8_{1,4}.  This doesn't match the
current Arm ARM official feature names, which are FEAT_PMUv3p1 and
FEAT_PMUv3p4.  Rename these functions to _pmuv3p1 and _pmuv3p4.

This commit was created with:
  sed -i -e 's/pmu_8_/pmuv3p/g' target/arm/*.[ch]

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822132358.3524971-8-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0b42f4fab9d3e994efa44e17cb76c15b269bcbda
      
https://github.com/qemu/qemu/commit/0b42f4fab9d3e994efa44e17cb76c15b269bcbda
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits

FEAT_PMUv3p5 introduces new bits which disable the cycle
counter from counting:
 * MDCR_EL2.HCCD disables the counter when in EL2
 * MDCR_EL3.SCCD disables the counter when Secure

Add the code to support these bits.

(Note that there is a third documented counter-disable
bit, MDCR_EL3.MCCD, which disables the counter when in
EL3. This is not present until FEAT_PMUv3p7, so is
out of scope for now.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822132358.3524971-9-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 47b385dae8e95e833114285625f4db796c52e8a3
      
https://github.com/qemu/qemu/commit/47b385dae8e95e833114285625f4db796c52e8a3
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Support 64-bit event counters for FEAT_PMUv3p5

With FEAT_PMUv3p5, the event counters are now 64 bit, rather than 32
bit.  (Previously, only the cycle counter could be 64 bit, and other
event counters were always 32 bits).  For any given event counter,
whether the overflow event is noted for overflow from bit 31 or from
bit 63 is controlled by a combination of PMCR.LP, MDCR_EL2.HLP and
MDCR_EL2.HPMN.

Implement the 64-bit event counter handling.  We choose to make our
counters always 64 bits, and mask out the top 32 bits on read or
write of PMXEVCNTR for CPUs which don't have FEAT_PMUv3p5.

(Note that the changes to pmenvcntr_op_start() and
pmenvcntr_op_finish() bring their logic closer into line with that of
pmccntr_op_start() and pmccntr_op_finish(), which already had to cope
with the overflow being either at 32 or 64 bits.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822132358.3524971-10-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e31e0f56616ae88cda22da8d5a257c2fcee4de2a
      
https://github.com/qemu/qemu/commit/e31e0f56616ae88cda22da8d5a257c2fcee4de2a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M docs/system/arm/emulation.rst
    M target/arm/cpu64.c
    M target/arm/cpu_tcg.c

  Log Message:
  -----------
  target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max'

Update the ID registers for TCG's '-cpu max' to report a FEAT_PMUv3p5
compliant PMU.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822132358.3524971-11-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f92bd43480bf2da36354e148d139ef2aac12d3f2
      
https://github.com/qemu/qemu/commit/f92bd43480bf2da36354e148d139ef2aac12d3f2
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M hw/arm/armv7m.c

  Log Message:
  -----------
  target/arm: Remove useless TARGET_BIG_ENDIAN check in armv7m_load_kernel()

Arm system emulation targets always have TARGET_BIG_ENDIAN clear, so
there is no need to have handling in armv7m_load_kernel() for the
case when it is defined.  Remove the unnecessary code.

Side notes:
 * our M-profile implementation is always little-endian (that is, it
   makes the IMPDEF choice that the read-only AIRCR.ENDIANNESS is 0)
 * if we did want to handle big-endian ELF files here we should do it
   the way that hw/arm/boot.c:arm_load_elf() does, by looking at the
   ELF header to see what endianness the file itself is

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220823160417.3858216-2-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 761c532ab1ebe9d345c9afe4fb9c2c4b26c58582
      
https://github.com/qemu/qemu/commit/761c532ab1ebe9d345c9afe4fb9c2c4b26c58582
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M hw/arm/armv7m.c
    M hw/arm/aspeed.c
    M hw/arm/microbit.c
    M hw/arm/mps2-tz.c
    M hw/arm/mps2.c
    M hw/arm/msf2-som.c
    M hw/arm/musca.c
    M hw/arm/netduino2.c
    M hw/arm/netduinoplus2.c
    M hw/arm/stellaris.c
    M hw/arm/stm32vldiscovery.c
    M include/hw/arm/boot.h

  Log Message:
  -----------
  target/arm: Make boards pass base address to armv7m_load_kernel()

Currently armv7m_load_kernel() takes the size of the block of memory
where it should load the initial guest image, but assumes that it
should always load it at address 0.  This happens to be true of all
our M-profile boards at the moment, but it isn't guaranteed to always
be so: M-profile CPUs can be configured (via init-svtor and
init-nsvtor, which match equivalent hardware configuration signals)
to have the initial vector table at any address, not just zero.  (For
instance the Teeny board has the boot ROM at address 0x0200_0000.)

Add a base address argument to armv7m_load_kernel(), so that
callers now pass in both base address and size. All the current
callers pass 0, so this is not a behaviour change.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220823160417.3858216-3-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 00d60cfcbda54b86ad9e09b20c7b71250dd6b19b
      
https://github.com/qemu/qemu/commit/00d60cfcbda54b86ad9e09b20c7b71250dd6b19b
  Author: zhenwei pi <pizhenwei@bytedance.com>
  Date:   2022-09-15 (Thu, 15 Sep 2022)

  Changed paths:
    M hmp-commands-info.hx
    M monitor/misc.c

  Log Message:
  -----------
  monitor: Support specified vCPU registers

Originally we have to get all the vCPU registers and parse the
specified one. To improve the performance of this usage, allow user
specified vCPU id to query registers.

Run a VM with 16 vCPU, use bcc tool to track the latency of
'hmp_info_registers':
'info registers -a' uses about 3ms;
'info registers 12' uses about 150us.

Cc: Darren Kenny <darren.kenny@oracle.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: zhenwei pi <pizhenwei@bytedance.com>
Reviewed-by: Darren Kenny <darren.kenny@oracle.com>
Message-Id: <20220802073720.1236988-2-pizhenwei@bytedance.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>


  Commit: 3183bb3f441ba5b9da570f7f5f9abdc3313ba311
      
https://github.com/qemu/qemu/commit/3183bb3f441ba5b9da570f7f5f9abdc3313ba311
  Author: Dongli Zhang <dongli.zhang@oracle.com>
  Date:   2022-09-15 (Thu, 15 Sep 2022)

  Changed paths:
    M monitor/hmp.c

  Log Message:
  -----------
  monitor/hmp: print trace as option in help for log command

The below is printed when printing help information in qemu-system-x86_64
command line, and when CONFIG_TRACE_LOG is enabled:

----------------------------
$ qemu-system-x86_64 -d help
... ...
trace:PATTERN   enable trace events

Use "-d trace:help" to get a list of trace events.
----------------------------

However, the options of "trace:PATTERN" are only printed by
"qemu-system-x86_64 -d help", but missing in hmp "help log" command.

Fixes: c84ea00dc2 ("log: add "-d trace:PATTERN"")
Cc: Joe Jin <joe.jin@oracle.com>
Signed-off-by: Dongli Zhang <dongli.zhang@oracle.com>
Message-Id: <20220831213943.8155-1-dongli.zhang@oracle.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>


  Commit: 22269b0436cc8e4aaac975b4c8cb01b343d09661
      
https://github.com/qemu/qemu/commit/22269b0436cc8e4aaac975b4c8cb01b343d09661
  Author: Dr. David Alan Gilbert <dgilbert@redhat.com>
  Date:   2022-09-15 (Thu, 15 Sep 2022)

  Changed paths:
    M hmp-commands.hx

  Log Message:
  -----------
  hmp: Fix ordering of text

Fix the ordering of the help text so it's always after the commands
being defined.  A few had got out of order.  Keep 'info' at the end.

Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>


  Commit: 50eac424c74bddd2d73cee47080be94c1d04893e
      
https://github.com/qemu/qemu/commit/50eac424c74bddd2d73cee47080be94c1d04893e
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2022-09-17 (Sat, 17 Sep 2022)

  Changed paths:
    M docs/system/arm/emulation.rst
    M docs/system/arm/virt.rst
    M hw/arm/armv7m.c
    M hw/arm/aspeed.c
    M hw/arm/microbit.c
    M hw/arm/mps2-tz.c
    M hw/arm/mps2.c
    M hw/arm/msf2-som.c
    M hw/arm/musca.c
    M hw/arm/netduino2.c
    M hw/arm/netduinoplus2.c
    M hw/arm/stellaris.c
    M hw/arm/stm32vldiscovery.c
    M hw/arm/virt.c
    M hw/misc/bcm2835_property.c
    M include/hw/arm/boot.h
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/cpu_tcg.c
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/kvm64.c

  Log Message:
  -----------
  Merge tag 'pull-arm-20220914' of https://gitlab.com/rth7680/qemu into staging

Add cortex-a35.
Fix bcm2835 framebuffer for rpi firmware.
Add FEAT_ETS.
Add FEAT_PMUv3p5.
Cleanups to armv7m_load_kernel.

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmMhwAsdHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/7Xgf9Ezg+etwsEzY0EWtH
# yoQ7ymJHM1VKqtLkbk9U+Ju18YHEi3fwbYbfLgzkAMFHKDUteKJivKm2w41tsw5g
# lE+5PojQT3k8PffaqeFzKG/JsDPoqKtTa23WjkafbIQAbjRT8JtmF/JmSLaaxyqW
# DozPXJ9jXMS+Q2BxHnoCBuy/Kb3zsqekCr8DOgUIXY5gcAB6q1I8SMX2BrhsIyvV
# vZxNm+hFDCOJtXvkAekMrwGkiIBYoBNpswnv40ldeSvRtD8tnty73JUt+AnWoCwi
# zH4k+CvWICIuZT7oxVecRhlOojtaP5cUTXs0+zhk6GxEx/X6wmXd42heO9ZJL0y1
# 6FH0xw==
# =ohPU
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 14 Sep 2022 07:50:35 EDT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* tag 'pull-arm-20220914' of https://gitlab.com/rth7680/qemu:
  target/arm: Make boards pass base address to armv7m_load_kernel()
  target/arm: Remove useless TARGET_BIG_ENDIAN check in armv7m_load_kernel()
  target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max'
  target/arm: Support 64-bit event counters for FEAT_PMUv3p5
  target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits
  target/arm: Rename pmu_8_n feature test functions
  target/arm: Detect overflow when calculating next PMU interrupt
  target/arm: Honour MDCR_EL2.HPMD in Secure EL2
  target/arm: Ignore PMCR.D when PMCR.LC is set
  target/arm: Don't mishandle count when enabling or disabling PMU counters
  target/arm: Correct value returned by pmu_counter_mask()
  target/arm: Don't corrupt high half of PMOVSR when cycle counter overflows
  target/arm: Add missing space in comment
  target/arm: Advertise FEAT_ETS for '-cpu max'
  target/arm: Implement ID_DFR1
  target/arm: Implement ID_MMFR5
  target/arm: Sort KVM reads of AArch32 ID registers into encoding order
  target/arm: Make cpregs 0, c0, c{3-15}, {0-7} correctly RAZ in v8
  hw/arm/bcm2835_property: Add support for 
RPI_FIRMWARE_FRAMEBUFFER_GET_NUM_DISPLAYS
  target/arm: Add cortex-a35

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


  Commit: 123a32f9b38c3bd22d47688d0bf0ab955d4152bc
      
https://github.com/qemu/qemu/commit/123a32f9b38c3bd22d47688d0bf0ab955d4152bc
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2022-09-17 (Sat, 17 Sep 2022)

  Changed paths:
    M include/semihosting/semihost.h
    M qemu-options.hx
    M semihosting/config.c
    M softmmu/vl.c
    M stubs/semihost.c
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/m68k/m68k-semi.c
    M target/m68k/op_helper.c
    M target/mips/tcg/micromips_translate.c.inc
    M target/mips/tcg/mips16e_translate.c.inc
    M target/mips/tcg/nanomips_translate.c.inc
    M target/mips/tcg/translate.c
    M target/nios2/nios2-semi.c
    M target/nios2/translate.c
    M target/riscv/cpu_helper.c
    M target/riscv/insn_trans/trans_privileged.c.inc
    M target/riscv/translate.c
    M target/xtensa/translate.c

  Log Message:
  -----------
  Merge tag 'pull-semi-20220914' of https://gitlab.com/rth7680/qemu into staging

Convert m68k to semihosting/syscalls.h.
Convert nios2 to semihosting/syscalls.h.
Allow optional use of semihosting from userspace.

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmMh1W8dHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8ptggAimuNN6IiD19Huu5F
# PMjzDqFPvWFOf82O16WTBM1xN0lwVH8+02PYRL3AhOIw9ZTgxezOo9/KXZpr8a8Z
# gocr4Ge/J7zHzHahYuqcyOqqkur2dM4lFiK9rfDD6vdNBMbi0kQZVuaNlQK6rV6Z
# 2LHEwKKh64MXJVfwGzK7OLMv4pu0wpWcuCTH2/6U4E1325SOKmEos1VzIePxY1bw
# +AMNnairGEdBX1b3JlzZfrLSaOapJcgl0HZdrg6Mflm6ttTuuykGGtjkWBfcu3Nw
# utNI1zmUYfD/iJbnbsCNpZSLv6LVOQ2l5S6dOWV+JJ1HukVTZu3DoyfTr8t95kwK
# UuUoqA==
# =W7Yh
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 14 Sep 2022 09:21:51 EDT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* tag 'pull-semi-20220914' of https://gitlab.com/rth7680/qemu:
  target/riscv: Honour -semihosting-config userspace=on and enable=on
  target/xtensa: Honour -semihosting-config userspace=on
  target/nios2: Honour -semihosting-config userspace=on
  target/mips: Honour -semihosting-config userspace=on
  target/m68k: Honour -semihosting-config userspace=on
  target/arm: Honour -semihosting-config userspace=on
  semihosting: Allow optional use of semihosting from userspace
  target/m68k: Convert semihosting errno to gdb remote errno
  target/m68k: Use semihosting/syscalls.h
  target/nios2: Convert semihosting errno to gdb remote errno
  target/nios2: Use semihosting/syscalls.h

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


  Commit: d29201ff34a135cdfc197f4413c1c5047e4f58bb
      
https://github.com/qemu/qemu/commit/d29201ff34a135cdfc197f4413c1c5047e4f58bb
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2022-09-17 (Sat, 17 Sep 2022)

  Changed paths:
    M hmp-commands-info.hx
    M hmp-commands.hx
    M monitor/hmp.c
    M monitor/misc.c

  Log Message:
  -----------
  Merge tag 'pull-hmp-20220915a' of https://gitlab.com/dagrh/qemu into staging

HMP pull 2022-09-15

A set of 3 small additions/fixes.

Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEERfXHG0oMt/uXep+pBRYzHrxb/ecFAmMjNG4ACgkQBRYzHrxb
# /edRhhAAibHXFdK1EHtcABInxMVg50wZ7oD2QiYqKb1m0t9rQDSmZ/cX22qdYF7D
# hBvjsMiniy6isGYyiPhpi+7ZMnid12E6EpZ49tFKbDz+DPfpT3mk/MOKvNQu150I
# K8NuqD40HImpUzo7/OVVIzo26TsKMFUo7WzuzqP4PEguSCqVAlzuoVxId8oZ3DbT
# c/VQTZjwLbi+i7DuuFc1pqfzC3euNEApM7DRAYNios+oGxd2kd+DC7JLqMKK4Uk1
# 5t5YmCz3Q+aFZ1kOvpxUW+3xT0LI4wzR0XA0ImA3jADaqt5G3dNOzosY2E7eaQen
# AXpqu6dH5wbSl2y5LWSscgN8ObAs5N6n0+ncXtIYwMENBBkZpWtaDbTYp6ezcrww
# 2st2qQ0MlUj8oiH3jMr5TtkZxcx9wXdEfrCDZ0MQt3275Bp6JuSW6DjqXjjpKimY
# 2HsAPDKYFNVJl/9SX5PxW6cGPZyb/YMa+14YdIdMbWc8+q+4yMSQnTJbGvxLFakt
# S/agxGu3hpEGrYUjCdl6JzIyOxdUVFp+Lp4NwhU+DI/1UaL1/QbiK+NxDXvkk+Wp
# wcI7VbIXb6YMWf9Gmv4NQ1b4uTf8qoA7J0SNONrw9ywU4lhsm9UKoIoakKaSK9F8
# kI+vBt/mmZTCqNw8h4w/KNvrRFF5nP/vw117xdOGGbtCS7G8438=
# =Isyw
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 15 Sep 2022 10:19:26 EDT
# gpg:                using RSA key 45F5C71B4A0CB7FB977A9FA90516331EBC5BFDE7
# gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" 
[full]
# Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A  9FA9 0516 331E BC5B FDE7

* tag 'pull-hmp-20220915a' of https://gitlab.com/dagrh/qemu:
  hmp: Fix ordering of text
  monitor/hmp: print trace as option in help for log command
  monitor: Support specified vCPU registers

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


Compare: https://github.com/qemu/qemu/compare/2e4dd7aa8da2...d29201ff34a1