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[Qemu-commits] [qemu/qemu] 8809ba: target/mips: Handle lock_user() failu


From: Richard Henderson
Subject: [Qemu-commits] [qemu/qemu] 8809ba: target/mips: Handle lock_user() failure in UHI_plo...
Date: Mon, 08 Aug 2022 19:41:33 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 8809baf4e40633ba01b47cd2257bbbbba14fc861
      
https://github.com/qemu/qemu/commit/8809baf4e40633ba01b47cd2257bbbbba14fc861
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-08-08 (Mon, 08 Aug 2022)

  Changed paths:
    M target/mips/tcg/sysemu/mips-semi.c

  Log Message:
  -----------
  target/mips: Handle lock_user() failure in UHI_plog semihosting call

Coverity notes that we forgot to check the error return from
lock_user() in one place in the handling of the UHI_plog semihosting
call.  Add the missing error handling.

report_fault() is rather brutal in that it will call abort(), but
this is the same error-handling used in the rest of this file.

Resolves: Coverity CID 1490684
Fixes: ea4210600db3c5 ("target/mips: Avoid qemu_semihosting_log_out for 
UHI_plog")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220719191737.384744-1-peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: bd64c210ce2bebba993ee49d34327706ec47f685
      
https://github.com/qemu/qemu/commit/bd64c210ce2bebba993ee49d34327706ec47f685
  Author: Igor Mammedov <imammedo@redhat.com>
  Date:   2022-08-08 (Mon, 08 Aug 2022)

  Changed paths:
    M hw/mips/malta.c

  Log Message:
  -----------
  hw/mips/malta: turn off x86 specific features of PIIX4_PM

QEMU crashes trying to save VMSTATE when only MIPS target are compiled in
  $ qemu-system-mips -monitor stdio
  (qemu) migrate "exec:gzip -c > STATEFILE.gz"
  Segmentation fault (core dumped)

It happens due to PIIX4_PM trying to parse hotplug vmstate structures
which are valid only for x86 and not for MIPS (as it requires ACPI
tables support which is not existent for ithe later)

Issue was probably exposed by trying to cleanup/compile out unused
ACPI bits from MIPS target (but forgetting about migration bits).

Disable compiled out features using compat properties as the least
risky way to deal with issue.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/995
Reviewed-by: Ani Sinha <ani@anisinha.ca>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20220728115034.1327988-1-imammedo@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 09d12c81ec5d8dc9208e5739d17a56c34be96247
      
https://github.com/qemu/qemu/commit/09d12c81ec5d8dc9208e5739d17a56c34be96247
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-08-08 (Mon, 08 Aug 2022)

  Changed paths:
    M hw/misc/grlib_ahb_apb_pnp.c
    M hw/misc/trace-events

  Log Message:
  -----------
  hw/misc/grlib_ahb_apb_pnp: Support 8 and 16 bit accesses

In real hardware, the APB and AHB PNP data tables can be accessed
with byte and halfword reads as well as word reads.  Our
implementation currently only handles word reads.  Add support for
the 8 and 16 bit accesses.  Note that we only need to handle aligned
accesses -- unaligned accesses should continue to trap, as happens on
hardware.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1132
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Frederic Konrad <fkonrad@amd.com>
Message-Id: <20220802131925.3380923-1-peter.maydell@linaro.org>
Tested-by: Tomasz Martyniak <gitlab.com/tom4r>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 7b06148df8a22d984e77e796322aeb5901dc653c
      
https://github.com/qemu/qemu/commit/7b06148df8a22d984e77e796322aeb5901dc653c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-08-08 (Mon, 08 Aug 2022)

  Changed paths:
    M hw/mips/malta.c
    M hw/misc/grlib_ahb_apb_pnp.c
    M hw/misc/trace-events
    M target/mips/tcg/sysemu/mips-semi.c

  Log Message:
  -----------
  Merge tag 'mips-20220809' of https://github.com/philmd/qemu into staging

MIPS/SPARC patches queue

- target/mips: Handle lock_user failure in UHI_plog semihosting (Peter Maydell)
- hw/mips/malta: Turn off x86 specific features of PIIX4 PM (Igor Mammedov)
- hw/misc/grlib_ahb_apb_pnp: Support 8 and 16 bit accesses (Peter Maydell)

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# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" 
[full]

* tag 'mips-20220809' of https://github.com/philmd/qemu:
  hw/misc/grlib_ahb_apb_pnp: Support 8 and 16 bit accesses
  hw/mips/malta: turn off x86 specific features of PIIX4_PM
  target/mips: Handle lock_user() failure in UHI_plog semihosting call

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/8a1337e60400...7b06148df8a2



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