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[Qemu-commits] [qemu/qemu] 54ee56: aspeed: sbc: Allow per-machine settin


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 54ee56: aspeed: sbc: Allow per-machine settings
Date: Fri, 15 Jul 2022 07:37:32 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 54ee564132bdbd1346a241dde5d51f0a1d1a1c7b
      
https://github.com/qemu/qemu/commit/54ee564132bdbd1346a241dde5d51f0a1d1a1c7b
  Author: Joel Stanley <joel@jms.id.au>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M hw/misc/aspeed_sbc.c
    M include/hw/misc/aspeed_sbc.h

  Log Message:
  -----------
  aspeed: sbc: Allow per-machine settings

In order to correctly report secure boot running firmware the values
of certain registers must be set.

We don't yet have documentation from ASPEED on what they mean. The
meaning is inferred from u-boot's use of them.

Introduce properties so the settings can be configured per-machine.

Reviewed-by: Peter Delevoryas <pdel@fb.com>
Tested-by: Peter Delevoryas <pdel@fb.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20220628154740.1117349-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: d272d1410c91f399af15ef9ae4b561bc621de115
      
https://github.com/qemu/qemu/commit/d272d1410c91f399af15ef9ae4b561bc621de115
  Author: Peter Delevoryas <pdel@fb.com>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M hw/i2c/pmbus_device.c
    M include/hw/i2c/pmbus_device.h

  Log Message:
  -----------
  hw/i2c/pmbus: Add idle state to return 0xff's

Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
Message-Id: <20220701000626.77395-2-me@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: e51ae82571746e40f36aa9bfc5d0924dcf2b0a5d
      
https://github.com/qemu/qemu/commit/e51ae82571746e40f36aa9bfc5d0924dcf2b0a5d
  Author: Peter Delevoryas <pdel@fb.com>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M hw/sensor/isl_pmbus_vr.c
    M include/hw/sensor/isl_pmbus_vr.h

  Log Message:
  -----------
  hw/sensor: Add IC_DEVICE_ID to ISL voltage regulators

This commit adds a passthrough for PMBUS_IC_DEVICE_ID to allow Renesas
voltage regulators to return the integrated circuit device ID if they
would like to.

The behavior is very device specific, so it hasn't been added to the
general PMBUS model. Additionally, if the device ID hasn't been set,
then the voltage regulator will respond with the error byte value.  The
guest error message will change slightly for IC_DEVICE_ID with this
commit.

Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
Message-Id: <20220701000626.77395-3-me@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: b347dd5ef324f964ca77582802822ad117690df0
      
https://github.com/qemu/qemu/commit/b347dd5ef324f964ca77582802822ad117690df0
  Author: Peter Delevoryas <pdel@fb.com>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M hw/sensor/isl_pmbus_vr.c

  Log Message:
  -----------
  hw/sensor: Add Renesas ISL69259 device model

This adds the ISL69259, using all the same functionality as the existing
ISL69260 but overriding the IC_DEVICE_ID.

Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
Message-Id: <20220701000626.77395-4-me@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 72a7c47393b41e406492e257a85589a75476b385
      
https://github.com/qemu/qemu/commit/72a7c47393b41e406492e257a85589a75476b385
  Author: Peter Delevoryas <peter@pjd.dev>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M hw/arm/aspeed_ast10x0.c
    M hw/arm/aspeed_ast2600.c
    M hw/arm/aspeed_soc.c

  Log Message:
  -----------
  aspeed: Create SRAM name from first CPU index

To support multiple SoC's running simultaneously, we need a unique name for
each RAM region. DRAM is created by the machine, but SRAM is created by the
SoC, since in hardware it is part of the SoC's internals.

We need a way to uniquely identify each SRAM region though, for VM
migration. Since each of the SoC's CPU's has an index which identifies it
uniquely from other CPU's in the machine, we can use the index of any of the
CPU's in the SoC to uniquely identify differentiate the SRAM name from other
SoC SRAM's. In this change, I just elected to use the index of the first CPU
in each SoC.

Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220705191400.41632-3-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: d2b3eaefb4d7ae274ff85001f03d8b1a87ea3a7f
      
https://github.com/qemu/qemu/commit/d2b3eaefb4d7ae274ff85001f03d8b1a87ea3a7f
  Author: Peter Delevoryas <peter@pjd.dev>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M hw/arm/aspeed.c
    M hw/arm/aspeed_ast10x0.c
    M hw/arm/aspeed_ast2600.c
    M hw/arm/aspeed_soc.c
    M include/hw/arm/aspeed_soc.h

  Log Message:
  -----------
  aspeed: Refactor UART init for multi-SoC machines

This change moves the code that connects the SoC UART's to serial_hd's
to the machine.

It makes each UART a proper child member of the SoC, and then allows the
machine to selectively initialize the chardev for each UART with a
serial_hd.

This should preserve backwards compatibility, but also allow multi-SoC
boards to completely change the wiring of serial devices from the
command line to specific SoC UART's.

This also removes the uart-default property from the SoC, since the SoC
doesn't need to know what UART is the "default" on the machine anymore.

I tested this using the images and commands from the previous
refactoring, and another test image for the ast1030:

    wget 
https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
    wget 
https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
    wget 
https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf

Fuji uses UART1:

    qemu-system-arm -machine fuji-bmc \
        -drive file=fuji.mtd,format=raw,if=mtd \
        -nographic

ast2600-evb uses uart-default=UART5:

    qemu-system-arm -machine ast2600-evb \
        -drive file=fuji.mtd,format=raw,if=mtd \
        -serial null -serial mon:stdio -display none

Wedge100 uses UART3:

    qemu-system-arm -machine palmetto-bmc \
        -drive file=wedge100.mtd,format=raw,if=mtd \
        -serial null -serial null -serial null \
        -serial mon:stdio -display none

AST1030 EVB uses UART5:

    qemu-system-arm -machine ast1030-evb \
        -kernel Y35BCL.elf -nographic

Fixes: 6827ff20b2975 ("hw: aspeed: Init all UART's with serial devices")
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220705191400.41632-4-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 1099ad10b0ec66406d419765428eef0738267035
      
https://github.com/qemu/qemu/commit/1099ad10b0ec66406d419765428eef0738267035
  Author: Peter Delevoryas <peter@pjd.dev>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M hw/arm/aspeed.c
    M include/hw/arm/aspeed_soc.h

  Log Message:
  -----------
  aspeed: Make aspeed_board_init_flashes public

Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220705191400.41632-5-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: c2f58c2fa2f2a0e65de3235ca78d084a8dc1b344
      
https://github.com/qemu/qemu/commit/c2f58c2fa2f2a0e65de3235ca78d084a8dc1b344
  Author: Peter Delevoryas <peter@pjd.dev>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M MAINTAINERS
    A hw/arm/fby35.c
    M hw/arm/meson.build

  Log Message:
  -----------
  aspeed: Add fby35 skeleton

Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220705191400.41632-6-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 778e14cc5cd589d45b5f8884b029d463c20226bc
      
https://github.com/qemu/qemu/commit/778e14cc5cd589d45b5f8884b029d463c20226bc
  Author: Peter Delevoryas <peter@pjd.dev>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M hw/arm/fby35.c

  Log Message:
  -----------
  aspeed: Add AST2600 (BMC) to fby35

You can test booting the BMC with both '-device loader' and '-drive
file'. This is necessary because of how the fb-openbmc boot sequence
works (jump to 0x20000000 after U-Boot SPL).

    wget 
https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd
    qemu-system-arm -machine fby35 -nographic \
        -device loader,file=fby35.mtd,addr=0,cpu-num=0 -drive 
file=fby35.mtd,format=raw,if=mtd

Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220705191400.41632-7-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 9cd8c41d7a41b12f36e921ba03057cb9a688d396
      
https://github.com/qemu/qemu/commit/9cd8c41d7a41b12f36e921ba03057cb9a688d396
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M hw/arm/fby35.c

  Log Message:
  -----------
  aspeed: fby35: Add a bootrom for the BMC

The BMC boots from the first flash device by fetching instructions
from the flash contents. Add an alias region on 0x0 for this
purpose. There are currently performance issues with this method (TBs
being flushed too often), so as a faster alternative, install the
flash contents as a ROM in the BMC memory space.

See commit 1a15311a12fa ("hw/arm/aspeed: add a 'execute-in-place'
property to boot directly from CE0")

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
[ clg: blk_pread() fixes ]
Message-Id: <20220705191400.41632-8-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: d5829a29207b29a7b5d64e449e58db2e40544b74
      
https://github.com/qemu/qemu/commit/d5829a29207b29a7b5d64e449e58db2e40544b74
  Author: Peter Delevoryas <peter@pjd.dev>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M hw/arm/fby35.c

  Log Message:
  -----------
  aspeed: Add AST1030 (BIC) to fby35

With the BIC, the easiest way to run everything is to create two pty's
for each SoC and reserve stdin/stdout for the monitor:

    wget 
https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd
    wget 
https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf
    qemu-system-arm -machine fby35 \
        -drive file=fby35.mtd,format=raw,if=mtd \
        -device loader,file=fby35.mtd,addr=0,cpu-num=0 \
        -serial pty -serial pty -serial mon:stdio -display none -S

    screen /dev/ttys0
    screen /dev/ttys1
    (qemu) c

This commit only adds the the first server board's Bridge IC, but in the
future we'll try to include the other three server board Bridge IC's
too.

Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220705191400.41632-9-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 19d7c0d460fe81a179ff41a7d52b580aeb115685
      
https://github.com/qemu/qemu/commit/19d7c0d460fe81a179ff41a7d52b580aeb115685
  Author: Peter Delevoryas <peter@pjd.dev>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M docs/system/arm/aspeed.rst

  Log Message:
  -----------
  docs: aspeed: Add fby35 multi-SoC machine section

Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: - fixed URL links
       - Moved Facebook Yosemite section at the end of the file ]
Message-Id: <20220705191400.41632-10-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 1d6fb3d05888578fdb09600fef4e9e90e652010d
      
https://github.com/qemu/qemu/commit/1d6fb3d05888578fdb09600fef4e9e90e652010d
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M docs/system/arm/aspeed.rst

  Log Message:
  -----------
  docs: aspeed: Minor updates

Some more controllers have been modeled recently. Reflect that in the
list of supported devices. New machines were also added.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20220706172131.809255-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: bceb4d994d0fc9c5cccb7fc177938f132d3d4a30
      
https://github.com/qemu/qemu/commit/bceb4d994d0fc9c5cccb7fc177938f132d3d4a30
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M tests/avocado/machine_aspeed.py

  Log Message:
  -----------
  test/avocado/machine_aspeed.py: Add SDK tests

The Aspeed SDK kernel usually includes support for the lastest HW
features. This is interesting to exercise QEMU and discover the gaps
in the models.

Add extra I2C tests for the AST2600 EVB machine to check the new
register interface.

Message-Id: <20220707091239.1029561-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 2113a128976f973bb5d2e655ac6353939df993da
      
https://github.com/qemu/qemu/commit/2113a128976f973bb5d2e655ac6353939df993da
  Author: Iris Chen <irischenlj@fb.com>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  hw: m25p80: Add Block Protect and Top Bottom bits for write protect

Signed-off-by: Iris Chen <irischenlj@fb.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220708164552.3462620-1-irischenlj@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 8abf9ba472a204ee9a9b01dbad9fb6615bbd9cae
      
https://github.com/qemu/qemu/commit/8abf9ba472a204ee9a9b01dbad9fb6615bbd9cae
  Author: Iris Chen <irischenlj@fb.com>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M tests/qtest/aspeed_smc-test.c

  Log Message:
  -----------
  hw: m25p80: add tests for BP and TB bit write protect

Signed-off-by: Iris Chen <irischenlj@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220627185234.1911337-3-irischenlj@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 35c86423d34460b24b4f0b35b32571da166a78fe
      
https://github.com/qemu/qemu/commit/35c86423d34460b24b4f0b35b32571da166a78fe
  Author: Peter Delevoryas <peter@pjd.dev>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M tests/qtest/aspeed_gpio-test.c

  Log Message:
  -----------
  qtest/aspeed_gpio: Add input pin modification test

Verify the current behavior, which is that input pins can be modified by
guest OS register writes.

Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220712023219.41065-2-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 1f30db922c72ca8c9de31f58a996bc21ee668304
      
https://github.com/qemu/qemu/commit/1f30db922c72ca8c9de31f58a996bc21ee668304
  Author: Peter Delevoryas <peter@pjd.dev>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M hw/gpio/aspeed_gpio.c
    M tests/qtest/aspeed_gpio-test.c

  Log Message:
  -----------
  hw/gpio/aspeed: Don't let guests modify input pins

Up until now, guests could modify input pins by overwriting the data
value register. The guest OS should only be allowed to modify output pin
values, and the QOM property setter should only be permitted to modify
input pins.

This change also updates the gpio input pin test to match this
expectation.

Andrew suggested this particularly refactoring here:

    
https://lore.kernel.org/qemu-devel/23523aa1-ba81-412b-92cc-8174faba3612@www.fastmail.com/

Suggested-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Fixes: 4b7f956862dc ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and 
AST2500")
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220712023219.41065-3-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: f0418558302ef9e140681e04250fc1ca265f3140
      
https://github.com/qemu/qemu/commit/f0418558302ef9e140681e04250fc1ca265f3140
  Author: Peter Delevoryas <peter@pjd.dev>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: Add fby35-bmc slot GPIO's

Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220712023219.41065-4-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 44bfcf628b1531f11ecc21ae96d025a238e1083f
      
https://github.com/qemu/qemu/commit/44bfcf628b1531f11ecc21ae96d025a238e1083f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-07-15 (Fri, 15 Jul 2022)

  Changed paths:
    M MAINTAINERS
    M docs/system/arm/aspeed.rst
    M hw/arm/aspeed.c
    M hw/arm/aspeed_ast10x0.c
    M hw/arm/aspeed_ast2600.c
    M hw/arm/aspeed_soc.c
    A hw/arm/fby35.c
    M hw/arm/meson.build
    M hw/block/m25p80.c
    M hw/gpio/aspeed_gpio.c
    M hw/i2c/pmbus_device.c
    M hw/misc/aspeed_sbc.c
    M hw/sensor/isl_pmbus_vr.c
    M include/hw/arm/aspeed_soc.h
    M include/hw/i2c/pmbus_device.h
    M include/hw/misc/aspeed_sbc.h
    M include/hw/sensor/isl_pmbus_vr.h
    M tests/avocado/machine_aspeed.py
    M tests/qtest/aspeed_gpio-test.c
    M tests/qtest/aspeed_smc-test.c

  Log Message:
  -----------
  Merge tag 'pull-aspeed-20220714' of https://github.com/legoater/qemu into 
staging

aspeed queue:

* New ISL69259 device model
* New fby35 multi-SoC machine (AST1030 BIC + AST2600 BMC)
* Aspeed GPIO fixes
* Extension of m25p80 with write protect bits
* More avocado tests using the Aspeed SDK

# gpg: Signature made Thu 14 Jul 2022 15:28:09 BST
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-aspeed-20220714' of https://github.com/legoater/qemu:
  aspeed: Add fby35-bmc slot GPIO's
  hw/gpio/aspeed: Don't let guests modify input pins
  qtest/aspeed_gpio: Add input pin modification test
  hw: m25p80: add tests for BP and TB bit write protect
  hw: m25p80: Add Block Protect and Top Bottom bits for write protect
  test/avocado/machine_aspeed.py: Add SDK tests
  docs: aspeed: Minor updates
  docs: aspeed: Add fby35 multi-SoC machine section
  aspeed: Add AST1030 (BIC) to fby35
  aspeed: fby35: Add a bootrom for the BMC
  aspeed: Add AST2600 (BMC) to fby35
  aspeed: Add fby35 skeleton
  aspeed: Make aspeed_board_init_flashes public
  aspeed: Refactor UART init for multi-SoC machines
  aspeed: Create SRAM name from first CPU index
  hw/sensor: Add Renesas ISL69259 device model
  hw/sensor: Add IC_DEVICE_ID to ISL voltage regulators
  hw/i2c/pmbus: Add idle state to return 0xff's
  aspeed: sbc: Allow per-machine settings

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/285f64fcbf86...44bfcf628b15



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