[Qemu-commits] [qemu/qemu] 4e245a: target/riscv: Remove condition guarding register z...

[Richard Henderson]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 4e245a9e263e6272c5a47a46c770f3c3965cdf21
      
https://github.com/qemu/qemu/commit/4e245a9e263e6272c5a47a46c770f3c3965cdf21
  Author: Víctor Colombo <victor.colombo@eldorado.org.br>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M target/riscv/insn_trans/trans_rvi.c.inc

  Log Message:
  -----------
  target/riscv: Remove condition guarding register zero for auipc and lui

Commit 57c108b8646 introduced gen_set_gpri(), which already contains
a check for if the destination register is 'zero'. The check in auipc
and lui are then redundant. This patch removes those checks.

Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220610165517.47517-1-victor.colombo@eldorado.org.br>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: b97028b8c5a2865bec784bc9b8c4c31ad23a9351
      
https://github.com/qemu/qemu/commit/b97028b8c5a2865bec784bc9b8c4c31ad23a9351
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M target/riscv/translate.c
    A tests/tcg/riscv64/Makefile.softmmu-target
    A tests/tcg/riscv64/issue1060.S
    A tests/tcg/riscv64/semihost.ld

  Log Message:
  -----------
  target/riscv: Set env->bins in gen_exception_illegal

While we set env->bins when unwinding for ILLEGAL_INST,
from e.g. csrrw, we weren't setting it for immediately
illegal instructions.

Add a testcase for mtval via both exception paths.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1060
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220604231004.49990-2-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 5dacdbaeaf7874d361dc95d07e30c86b72c9693d
      
https://github.com/qemu/qemu/commit/5dacdbaeaf7874d361dc95d07e30c86b72c9693d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Remove generate_exception_mtval

The function doesn't set mtval, it sets badaddr. Move the set
of badaddr directly into gen_exception_inst_addr_mis and use
generate_exception.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220604231004.49990-3-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a9814e3e08d2aacbd9018c36c77c2fb652537848
      
https://github.com/qemu/qemu/commit/a9814e3e08d2aacbd9018c36c77c2fb652537848
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M target/riscv/insn_trans/trans_privileged.c.inc
    M target/riscv/insn_trans/trans_rvh.c.inc
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Minimize the calls to decode_save_opc

The set of instructions that require decode_save_opc for
unwinding is really fairly small -- only insns that can
raise ILLEGAL_INSN at runtime.  This includes CSR, anything
that uses a *new* fp rounding mode, and many privileged insns.

Since unwind info is stored as the difference from the
previous insn, storing a 0 for most insns minimizes the
size of the unwind info.

Booting a debian kernel image to the missing rootfs panic yields

- gen code size       22226819/1026886656
+ gen code size       21601907/1026886656

on 41k TranslationBlocks, a savings of 610kB or a bit less than 3%.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220604231004.49990-4-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2e983399186b9ff85521dd35082779a133cd9b2b
      
https://github.com/qemu/qemu/commit/2e983399186b9ff85521dd35082779a133cd9b2b
  Author: Nicolas Pitre <nico@fluxnic.net>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  target/riscv/pmp: guard against PMP ranges with a negative size

For a TOR entry to match, the stard address must be lower than the end
address. Normally this is always the case, but correct code might still
run into the following scenario:

Initial state:

        pmpaddr3 = 0x2000       pmp3cfg = OFF
        pmpaddr4 = 0x3000       pmp4cfg = TOR

Execution:

        1. write 0x40ff to pmpaddr3
        2. write 0x32ff to pmpaddr4
        3. set pmp3cfg to NAPOT with a read-modify-write on pmpcfg0
        4. set pmp4cfg to NAPOT with a read-modify-write on pmpcfg1

When (2) is emulated, a call to pmp_update_rule() creates a negative
range for pmp4 as pmp4cfg is still set to TOR. And when (3) is emulated,
a call to tlb_flush() is performed, causing pmp_get_tlb_size() to return
a very creatively large TLB size for pmp4. This, in turn, may result in
accesses to non-existent/unitialized memory regions and a fault, so that
(4) ends up never being executed.

This is in m-mode with MPRV unset, meaning that unlocked PMP entries
should have no effect. Therefore such a behavior based on PMP content
is very unexpected.

Make sure no negative PMP range can be created, whether explicitly by
the emulated code or implicitly like the above.

Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <3oq0sqs1-67o0-145-5n1s-453o118804q@syhkavp.arg>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 562009e47c622298f82ee7557be9e15d5e50cee5
      
https://github.com/qemu/qemu/commit/562009e47c622298f82ee7557be9e15d5e50cee5
  Author: Atish Patra <atish.patra@wdc.com>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Fix PMU CSR predicate function

The predicate function calculates the counter index incorrectly for
hpmcounterx. Fix the counter index to reflect correct CSR number.

Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-2-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a5a92fd6ef038170231933c60cc2780f52b3a2e1
      
https://github.com/qemu/qemu/commit/a5a92fd6ef038170231933c60cc2780f52b3a2e1
  Author: Atish Patra <atish.patra@wdc.com>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Implement PMU CSR predicate function for S-mode

Currently, the predicate function for PMU related CSRs only works if
virtualization is enabled. It also does not check mcounteren bits before
before cycle/minstret/hpmcounterx access.

Support supervisor mode access in the predicate function as well.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-3-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d3be1299fb37e50535438a675a5b02f5bc068c14
      
https://github.com/qemu/qemu/commit/d3be1299fb37e50535438a675a5b02f5bc068c14
  Author: Atish Patra <atish.patra@wdc.com>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: pmu: Rename the counters extension to pmu

The PMU counters are supported via cpu config "Counters" which doesn't
indicate the correct purpose of those counters.

Rename the config property to pmu to indicate that these counters
are performance monitoring counters. This aligns with cpu options for
ARM architecture as well.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-4-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 18d6d89efc60f1c030c4a8a22816d2d911ece105
      
https://github.com/qemu/qemu/commit/18d6d89efc60f1c030c4a8a22816d2d911ece105
  Author: Atish Patra <atishp@rivosinc.com>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: pmu: Make number of counters configurable

The RISC-V privilege specification provides flexibility to implement
any number of counters from 29 programmable counters. However, the QEMU
implements all the counters.

Make it configurable through pmu config parameter which now will indicate
how many programmable counters should be implemented by the cpu.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-5-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: b1675eeb3e6e38b042a23a9647559c9c548c733d
      
https://github.com/qemu/qemu/commit/b1675eeb3e6e38b042a23a9647559c9c548c733d
  Author: Atish Patra <atish.patra@wdc.com>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c
    M target/riscv/machine.c

  Log Message:
  -----------
  target/riscv: Implement mcountinhibit CSR

As per the privilege specification v1.11, mcountinhibit allows to start/stop
a pmu counter selectively.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-6-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 621f35bb2fa8babb9ab2a65033fe8d47ea5cd8ba
      
https://github.com/qemu/qemu/commit/621f35bb2fa8babb9ab2a65033fe8d47ea5cd8ba
  Author: Atish Patra <atish.patra@wdc.com>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/csr.c
    M target/riscv/machine.c

  Log Message:
  -----------
  target/riscv: Add support for hpmcounters/hpmevents

With SBI PMU extension, user can use any of the available hpmcounters to
track any perf events based on the value written to mhpmevent csr.
Add read/write functionality for these csrs.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-7-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3780e33732f88a88b444fa42d56c5938ecd33e21
      
https://github.com/qemu/qemu/commit/3780e33732f88a88b444fa42d56c5938ecd33e21
  Author: Atish Patra <atish.patra@wdc.com>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/csr.c
    M target/riscv/machine.c
    M target/riscv/meson.build
    A target/riscv/pmu.c
    A target/riscv/pmu.h

  Log Message:
  -----------
  target/riscv: Support mcycle/minstret write operation

mcycle/minstret are actually WARL registers and can be written with any
given value. With SBI PMU extension, it will be used to store a initial
value provided from supervisor OS. The Qemu also need prohibit the counter
increment if mcountinhibit is set.

Support mcycle/minstret through generic counter infrastructure.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-8-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: b509caceaa6dcb694015390a202002a0f3088ad0
      
https://github.com/qemu/qemu/commit/b509caceaa6dcb694015390a202002a0f3088ad0
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Fixup MSECCFG minimum priv check

There is nothing in the RISC-V spec that mandates version 1.12 is
required for ePMP and there is currently hardware [1] that implements
ePMP (a draft version though) with the 1.11 priv spec.

1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html

Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the 
CSR ops.")
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220629233102.275181-2-alistair.francis@opensource.wdc.com>


  Commit: be2265c776a67287cea03908495cf1e785271c6f
      
https://github.com/qemu/qemu/commit/be2265c776a67287cea03908495cf1e785271c6f
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Ibex: Support priv version 1.11

The Ibex CPU supports version 1.11 of the priv spec [1], so let's
correct that in QEMU as well.

1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220629233102.275181-3-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 188000952ca002402e41efe0a0d333097024dd90
      
https://github.com/qemu/qemu/commit/188000952ca002402e41efe0a0d333097024dd90
  Author: Anup Patel <apatel@ventanamicro.com>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Don't force update priv spec version to latest

The riscv_cpu_realize() sets priv spec version to v1.12 when it is
when "env->priv_ver == 0" (i.e. default v1.10) because the enum
value of priv spec v1.10 is zero.

Due to above issue, the sifive_u machine will see priv spec v1.12
instead of priv spec v1.10.

To fix this issue, we set latest priv spec version (i.e. v1.12)
for base rv64/rv32 cpu and riscv_cpu_realize() will override priv
spec version only when "cpu->cfg.priv_spec != NULL".

Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220611080107.391981-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ec2c62dacc186893a6ce63089f96b1906dd68804
      
https://github.com/qemu/qemu/commit/ec2c62dacc186893a6ce63089f96b1906dd68804
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M hw/riscv/boot.c

  Log Message:
  -----------
  hw/riscv: boot: Reduce FDT address alignment constraints

We previously stored the device tree at a 16MB alignment from the end of
memory (or 3GB). This means we need at least 16MB of memory to be able
to do this. We don't actually need the FDT to be 16MB aligned, so let's
drop it down to 2MB so that we can support systems with less memory,
while also allowing FDT size expansion.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/992
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20220608062015.317894-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 598ca8370634febb3438e7125278fd86b971a4a1
      
https://github.com/qemu/qemu/commit/598ca8370634febb3438e7125278fd86b971a4a1
  Author: Anup Patel <apatel@ventanamicro.com>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Set minumum priv spec version for mcountinhibit

The minimum priv spec versino for mcountinhibit to v1.11 so that it
is not available for v1.10 (or lower).

Fixes: eab4776b2bad ("target/riscv: Add support for hpmcounters/hpmevents")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220628101737.786681-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: df01af337f0cd48137ec67e207e3de5956acc379
      
https://github.com/qemu/qemu/commit/df01af337f0cd48137ec67e207e3de5956acc379
  Author: Anup Patel <apatel@ventanamicro.com>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits

Based on architecture review committee feedback, the [m|s|vs]seteienum,
[m|s|vs]clreienum, [m|s|vs]seteipnum, and [m|s|vs]clreipnum CSRs are
removed in the latest AIA draft v0.3.0 specification.
(Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31)

These CSRs were mostly for software convenience and software can always
use [m|s|vs]iselect and [m|s|vs]ireg CSRs to update the IMSIC interrupt
file bits.

We update the IMSIC CSR emulation as-per above to match the latest AIA
draft specification.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220616031543.953776-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 435774992e82d2d16f025afbb20b4f7be9b242b0
      
https://github.com/qemu/qemu/commit/435774992e82d2d16f025afbb20b4f7be9b242b0
  Author: Anup Patel <apatel@ventanamicro.com>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Update default priority table for local interrupts

The latest AIA draft v0.3.0 defines a relatively simpler scheme for
default priority assignments where:
1) local interrupts 24 to 31 and 48 to 63 are reserved for custom use
   and have implementation specific default priority.
2) remaining local interrupts 0 to 23 and 32 to 47 have a recommended
   (not mandatory) priority assignments.

We update the default priority table and hviprio mapping as-per above.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220616031543.953776-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e8e86b484eac70cd86e15fa10a2f0038a536cbba
      
https://github.com/qemu/qemu/commit/e8e86b484eac70cd86e15fa10a2f0038a536cbba
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M hw/riscv/boot.c
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/insn_trans/trans_privileged.c.inc
    M target/riscv/insn_trans/trans_rvh.c.inc
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/machine.c
    M target/riscv/meson.build
    M target/riscv/pmp.c
    A target/riscv/pmu.c
    A target/riscv/pmu.h
    M target/riscv/translate.c
    A tests/tcg/riscv64/Makefile.softmmu-target
    A tests/tcg/riscv64/issue1060.S
    A tests/tcg/riscv64/semihost.ld

  Log Message:
  -----------
  Merge tag 'pull-riscv-to-apply-20220703-1' of github.com:alistair23/qemu into 
staging

Fifth RISC-V PR for QEMU 7.1

* Fix register zero guarding for auipc and lui
* Ensure bins (mtval) is set correctly
* Minimize the calls to decode_save_opc
* Guard against PMP ranges with a negative size
* Implement mcountinhibit CSR
* Add support for hpmcounters/hpmevents
* Improve PMU implenentation
* Support mcycle/minstret write operation
* Fixup MSECCFG minimum priv check
* Ibex (OpenTitan) fixup priv version
* Fix bug resulting in always using latest priv spec
* Reduce FDT address alignment constraints
* Set minumum priv spec version for mcountinhibit
* AIA update to v0.3 of the spec

# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmLA3r8ACgkQIeENKd+X
# cFQdFQf6A63mocJxSc0vqMTBNULwgcUKbRbnkazbFS4vtbo/YXioCGaHA8c8trKj
# HbZfJv64phOThj7Y8ifLozENjnHX7dHbspPOcWIK9yalvKLA4EB4+OI7LisoL1vg
# H4E+9nXSzskaCmJgwSM6WlS0Vf89VxL0CoBb3XqJocSaajstg1XpqrR9anTZlUhl
# N712cLze+bOxBHTdjtC5Kxuxj+zmNvcMmuhldIJRdPCW8P5v2yccNVc6+hrE3WUX
# 9jHGMthS4qC5oVhok14/tPoyL0QTZpU2DXrJPFGUigOvUHoMBfQ3Qhulx3/rGLZv
# 4SdTD9ASrNWJfa+eyHAPNw//5NxTYA==
# =N7VN
# -----END PGP SIGNATURE-----
# gpg: Signature made Sun 03 Jul 2022 05:41:43 AM +0530
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" 
[undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20220703-1' of github.com:alistair23/qemu:
  target/riscv: Update default priority table for local interrupts
  target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits
  target/riscv: Set minumum priv spec version for mcountinhibit
  hw/riscv: boot: Reduce FDT address alignment constraints
  target/riscv: Don't force update priv spec version to latest
  target/riscv: Ibex: Support priv version 1.11
  target/riscv: Fixup MSECCFG minimum priv check
  target/riscv: Support mcycle/minstret write operation
  target/riscv: Add support for hpmcounters/hpmevents
  target/riscv: Implement mcountinhibit CSR
  target/riscv: pmu: Make number of counters configurable
  target/riscv: pmu: Rename the counters extension to pmu
  target/riscv: Implement PMU CSR predicate function for S-mode
  target/riscv: Fix PMU CSR predicate function
  target/riscv/pmp: guard against PMP ranges with a negative size
  target/riscv: Minimize the calls to decode_save_opc
  target/riscv: Remove generate_exception_mtval
  target/riscv: Set env->bins in gen_exception_illegal
  target/riscv: Remove condition guarding register zero for auipc and lui

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/ba45b82518bd...e8e86b484eac