[Qemu-commits] [qemu/qemu] ba1a67: sphinx: change default language to 'e

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[Qemu-commits] [qemu/qemu] ba1a67: sphinx: change default language to 'e

From:	Richard Henderson
Subject:	[Qemu-commits] [qemu/qemu] ba1a67: sphinx: change default language to 'en'
Date:	Mon, 27 Jun 2022 04:18:52 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: ba1a6723f58640ba281bc952abc255e97c70bad5
      
https://github.com/qemu/qemu/commit/ba1a6723f58640ba281bc952abc255e97c70bad5
  Author: Martin Liška <mliska@suse.cz>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M docs/conf.py

  Log Message:
  -----------
  sphinx: change default language to 'en'

Fixes the following Sphinx warning (treated as error) starting
with 5.0 release:

Warning, treated as error:
Invalid configuration value found: 'language = None'. Update your configuration 
to a valid langauge code. Falling back to 'en' (English).

Signed-off-by: Martin Liska <mliska@suse.cz>
Message-id: e91e51ee-48ac-437e-6467-98b56ee40042@suse.cz
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 55bd445c4195966675236936c0a8642f1965dddb
      
https://github.com/qemu/qemu/commit/55bd445c4195966675236936c0a8642f1965dddb
  Author: Alexander Graf <agraf@csgraf.de>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M accel/accel-common.c
    M include/qemu/accel.h
    M softmmu/vl.c

  Log Message:
  -----------
  accel: Introduce current_accel_name()

We need to fetch the name of the current accelerator in flexible error
messages more going forward. Let's create a helper that gives it to us
without casting in the target code.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620192242.70573-1-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 045e50641fd17655b02c4af485835bca38577bf3
      
https://github.com/qemu/qemu/commit/045e50641fd17655b02c4af485835bca38577bf3
  Author: Alexander Graf <agraf@csgraf.de>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Catch invalid kvm state also for hvf

Some features such as running in EL3 or running M profile code are
incompatible with virtualization as QEMU implements it today. To prevent
users from picking invalid configurations on other virt solutions like
Hvf, let's run the same checks there too.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1073
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620192242.70573-2-agraf@csgraf.de
[PMM: Allow qtest accelerator too; tweak comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9e5ec745e33ad6ace7a01653262dcedf1a5676d3
      
https://github.com/qemu/qemu/commit/9e5ec745e33ad6ace7a01653262dcedf1a5676d3
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement TPIDR2_EL0

This register is part of SME, but isn't closely related to the
rest of the extension.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6b2ca83e4c7953e6652e897bb4d4fb5280555dbf
      
https://github.com/qemu/qemu/commit/6b2ca83e4c7953e6652e897bb4d4fb5280555dbf
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Add SMEEXC_EL to TB flags

This is CheckSMEAccess, which is the basis for a set of
related tests for various SME cpregs and instructions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 58b2908ee1011c33cc01d7d9341673f8af6d14b7
      
https://github.com/qemu/qemu/commit/58b2908ee1011c33cc01d7d9341673f8af6d14b7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/syndrome.h

  Log Message:
  -----------
  target/arm: Add syn_smetrap

This will be used for raising various traps for SME.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: bca063d579cbd6075d0bab78cc702131df199d6e
      
https://github.com/qemu/qemu/commit/bca063d579cbd6075d0bab78cc702131df199d6e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/cpregs.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Add ARM_CP_SME

This will be used for controlling access to SME cpregs.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c37e6ac9eb94667d803d0cc1c4cc39ab351a6921
      
https://github.com/qemu/qemu/commit/c37e6ac9eb94667d803d0cc1c4cc39ab351a6921
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add SVCR

This cpreg is used to access two new bits of PSTATE
that are not visible via any other mechanism.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: de5619887cbc7549bfc63bec4993de94626ccf09
      
https://github.com/qemu/qemu/commit/de5619887cbc7549bfc63bec4993de94626ccf09
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add SMCR_ELx

These cpregs control the streaming vector length and whether the
full a64 instruction set is allowed while in streaming mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d5b1223ac1ddf8f706f5e6feaaa526df8287f8b1
      
https://github.com/qemu/qemu/commit/d5b1223ac1ddf8f706f5e6feaaa526df8287f8b1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add SMIDR_EL1, SMPRI_EL1, SMPRIMAP_EL2

Implement the streaming mode identification register, and the
two streaming priority registers.  For QEMU, they are all RES0.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a3637e8882f9dbb00036ff77a88b841bd2580900
      
https://github.com/qemu/qemu/commit/a3637e8882f9dbb00036ff77a88b841bd2580900
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Add PSTATE.{SM,ZA} to TB flags

These are required to determine if various insns
are allowed to issue.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: dc993a01a75295c505ef1ff8764c68f31089fcc7
      
https://github.com/qemu/qemu/commit/dc993a01a75295c505ef1ff8764c68f31089fcc7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/machine.c

  Log Message:
  -----------
  target/arm: Add the SME ZA storage to CPUARMState

Place this late in the resettable section of the structure,
to keep the most common element offsets from being > 64k.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-10-richard.henderson@linaro.org
[PMM: expanded comment on zarray[] format]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f84734b87461fbf3ab349399f7936de832e477ed
      
https://github.com/qemu/qemu/commit/f84734b87461fbf3ab349399f7936de832e477ed
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/cpu.h
    A target/arm/helper-sme.h
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/meson.build
    A target/arm/sme_helper.c
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Implement SMSTART, SMSTOP

These two instructions are aliases of MSR (immediate).
Use the two helpers to properly implement svcr_write.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 531cc510370eb7f672eaca416b0a3927806b3983
      
https://github.com/qemu/qemu/commit/531cc510370eb7f672eaca416b0a3927806b3983
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Move error for sve%d property to arm_cpu_sve_finalize

Keep all of the error messages together.  This does mean that
when setting many sve length properties we'll only generate
one error, but we only really need one.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7f9e25a6e43356d4a0fb2cc201c1a45c5be5bb6c
      
https://github.com/qemu/qemu/commit/7f9e25a6e43356d4a0fb2cc201c1a45c5be5bb6c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c
    M target/arm/kvm64.c

  Log Message:
  -----------
  target/arm: Create ARMVQMap

Pull the three sve_vq_* values into a structure.
This will be reused for SME.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0f40784eac0e429e48c26e85f5821120cf35ed79
      
https://github.com/qemu/qemu/commit/0f40784eac0e429e48c26e85f5821120cf35ed79
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Generalize cpu_arm_{get,set}_vq

Rename from cpu_arm_{get,set}_sve_vq, and take the
ARMVQMap as the opaque parameter.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 515816a82c11bbcc48272e1d8d3d61267cb2fd84
      
https://github.com/qemu/qemu/commit/515816a82c11bbcc48272e1d8d3d61267cb2fd84
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Generalize cpu_arm_{get, set}_default_vec_len

Rename from cpu_arm_{get,set}_sve_default_vec_len,
and take the pointer to default_vq from opaque.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 073011612b44771190bc091e459d0642d46c69b5
      
https://github.com/qemu/qemu/commit/073011612b44771190bc091e459d0642d46c69b5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Move arm_cpu_*_finalize to internals.h

Drop the aa32-only inline fallbacks,
and just use a couple of ifdefs.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 70cc9ee19e53bc8bc597c5134e294a2ab377c4da
      
https://github.com/qemu/qemu/commit/70cc9ee19e53bc8bc597c5134e294a2ab377c4da
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Unexport aarch64_add_*_properties

These functions are not used outside cpu64.c,
so make them static.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e74c097638d38b46d9c68f11565432034afc0ad0
      
https://github.com/qemu/qemu/commit/e74c097638d38b46d9c68f11565432034afc0ad0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M docs/system/arm/cpu-features.rst
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Add cpu properties for SME

Mirror the properties for SVE.  The main difference is
that any arbitrary set of powers of 2 may be supported,
and not the stricter constraints that apply to SVE.

Include a property to control FEAT_SME_FA64, as failing
to restrict the runtime to the proper subset of insns
could be a major point for bugs.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220620175235.60881-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6ca54aa9a882ece5a6bcf5879f25bdcd7a95331f
      
https://github.com/qemu/qemu/commit/6ca54aa9a882ece5a6bcf5879f25bdcd7a95331f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Introduce sve_vqm1_for_el_sm

When Streaming SVE mode is enabled, the size is taken from
SMCR_ELx instead of ZCR_ELx.  The format is shared, but the
set of vector lengths is not.  Further, Streaming SVE does
not require any particular length to be supported.

Adjust sve_vqm1_for_el to pass the current value of PSTATE.SM
to the new function.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5d7953adcfb30196ba684d3af69271528630367f
      
https://github.com/qemu/qemu/commit/5d7953adcfb30196ba684d3af69271528630367f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Add SVL to TB flags

We need SVL separate from VL for RDSVL et al, as well as
ZA storage loads and stores, which do not require PSTATE.SM.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d61d1b8600caea833c377b31aef61484ccf9e414
      
https://github.com/qemu/qemu/commit/d61d1b8600caea833c377b31aef61484ccf9e414
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/translate-a64.h
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Move pred_{full, gvec}_reg_{offset, size} to translate-a64.h

We will need these functions in translate-sme.c.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 22536b13247cf041b6dcabf0d708f486058989a9
      
https://github.com/qemu/qemu/commit/22536b13247cf041b6dcabf0d708f486058989a9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M hw/arm/virt.c
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Extend arm_pamax to more than aarch64

Move the code from hw/arm/virt.c that is supposed
to handle v7 into the one function.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reported-by: He Zhe <zhe.he@windriver.com>
Message-id: 20220619001541.131672-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 59e1b8a22ea9f947d038ccac784de1020f266e14
      
https://github.com/qemu/qemu/commit/59e1b8a22ea9f947d038ccac784de1020f266e14
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Check V7VE as well as LPAE in arm_pamax

In machvirt_init we create a cpu but do not fully initialize it.
Thus the propagation of V7VE to LPAE has not been done, and we
compute the wrong value for some v7 cpus, e.g. cortex-a15.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1078
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reported-by: He Zhe <zhe.he@windriver.com>
Message-id: 20220619001541.131672-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 29f6db75667f44f3f01ba5037dacaf9ebd9328da
      
https://github.com/qemu/qemu/commit/29f6db75667f44f3f01ba5037dacaf9ebd9328da
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M accel/accel-common.c
    M docs/conf.py
    M docs/system/arm/cpu-features.rst
    M hw/arm/virt.c
    M include/qemu/accel.h
    M softmmu/vl.c
    M target/arm/cpregs.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    A target/arm/helper-sme.h
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/internals.h
    M target/arm/kvm64.c
    M target/arm/machine.c
    M target/arm/meson.build
    M target/arm/ptw.c
    A target/arm/sme_helper.c
    M target/arm/syndrome.h
    M target/arm/translate-a64.c
    M target/arm/translate-a64.h
    M target/arm/translate-sve.c
    M target/arm/translate.h

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20220627' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * sphinx: change default language to 'en'
 * Diagnose attempts to emulate EL3 in hvf as well as kvm
 * More SME groundwork patches
 * virt: Fix calculation of physical address space size
   for v7VE CPUs (eg cortex-a15)

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# gpg: Signature made Mon 27 Jun 2022 03:51:21 PM +0530
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[full]

* tag 'pull-target-arm-20220627' of 
https://git.linaro.org/people/pmaydell/qemu-arm: (25 commits)
  target/arm: Check V7VE as well as LPAE in arm_pamax
  target/arm: Extend arm_pamax to more than aarch64
  target/arm: Move pred_{full, gvec}_reg_{offset, size} to translate-a64.h
  target/arm: Add SVL to TB flags
  target/arm: Introduce sve_vqm1_for_el_sm
  target/arm: Add cpu properties for SME
  target/arm: Unexport aarch64_add_*_properties
  target/arm: Move arm_cpu_*_finalize to internals.h
  target/arm: Generalize cpu_arm_{get, set}_default_vec_len
  target/arm: Generalize cpu_arm_{get,set}_vq
  target/arm: Create ARMVQMap
  target/arm: Move error for sve%d property to arm_cpu_sve_finalize
  target/arm: Implement SMSTART, SMSTOP
  target/arm: Add the SME ZA storage to CPUARMState
  target/arm: Add PSTATE.{SM,ZA} to TB flags
  target/arm: Add SMIDR_EL1, SMPRI_EL1, SMPRIMAP_EL2
  target/arm: Add SMCR_ELx
  target/arm: Add SVCR
  target/arm: Add ARM_CP_SME
  target/arm: Add syn_smetrap
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/097ccbbbaf26...29f6db75667f
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