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[Qemu-commits] [qemu/qemu] 44c2c0: hw/nvme: Add support for SR-IOV


From: Richard Henderson
Subject: [Qemu-commits] [qemu/qemu] 44c2c0: hw/nvme: Add support for SR-IOV
Date: Thu, 23 Jun 2022 14:53:00 -0700

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 44c2c09488db83b76cab8dd91f7319be82b2bd91
      
https://github.com/qemu/qemu/commit/44c2c09488db83b76cab8dd91f7319be82b2bd91
  Author: Lukasz Maniak <lukasz.maniak@linux.intel.com>
  Date:   2022-06-23 (Thu, 23 Jun 2022)

  Changed paths:
    M hw/nvme/ctrl.c
    M hw/nvme/nvme.h
    M include/hw/pci/pci_ids.h

  Log Message:
  -----------
  hw/nvme: Add support for SR-IOV

This patch implements initial support for Single Root I/O Virtualization
on an NVMe device.

Essentially, it allows to define the maximum number of virtual functions
supported by the NVMe controller via sriov_max_vfs parameter.

Passing a non-zero value to sriov_max_vfs triggers reporting of SR-IOV
capability by a physical controller and ARI capability by both the
physical and virtual function devices.

NVMe controllers created via virtual functions mirror functionally
the physical controller, which may not entirely be the case, thus
consideration would be needed on the way to limit the capabilities of
the VF.

NVMe subsystem is required for the use of SR-IOV.

Signed-off-by: Lukasz Maniak <lukasz.maniak@linux.intel.com>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>


  Commit: 5e6f963f018f2ebb16c0f9586f17811163d62b4a
      
https://github.com/qemu/qemu/commit/5e6f963f018f2ebb16c0f9586f17811163d62b4a
  Author: Lukasz Maniak <lukasz.maniak@linux.intel.com>
  Date:   2022-06-23 (Thu, 23 Jun 2022)

  Changed paths:
    M hw/nvme/ctrl.c
    M hw/nvme/nvme.h
    M hw/nvme/trace-events
    M include/block/nvme.h

  Log Message:
  -----------
  hw/nvme: Add support for Primary Controller Capabilities

Implementation of Primary Controller Capabilities data
structure (Identify command with CNS value of 14h).

Currently, the command returns only ID of a primary controller.
Handling of remaining fields are added in subsequent patches
implementing virtualization enhancements.

Signed-off-by: Lukasz Maniak <lukasz.maniak@linux.intel.com>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>


  Commit: 99f48ae7aea70fb080f04bf1cc846cd6450bd11a
      
https://github.com/qemu/qemu/commit/99f48ae7aea70fb080f04bf1cc846cd6450bd11a
  Author: Lukasz Maniak <lukasz.maniak@linux.intel.com>
  Date:   2022-06-23 (Thu, 23 Jun 2022)

  Changed paths:
    M hw/nvme/ctrl.c
    M hw/nvme/ns.c
    M hw/nvme/nvme.h
    M hw/nvme/subsys.c
    M hw/nvme/trace-events
    M include/block/nvme.h

  Log Message:
  -----------
  hw/nvme: Add support for Secondary Controller List

Introduce handling for Secondary Controller List (Identify command with
CNS value of 15h).

Secondary controller ids are unique in the subsystem, hence they are
reserved by it upon initialization of the primary controller to the
number of sriov_max_vfs.

ID reservation requires the addition of an intermediate controller slot
state, so the reserved controller has the address 0xFFFF.
A secondary controller is in the reserved state when it has no virtual
function assigned, but its primary controller is realized.
Secondary controller reservations are released to NULL when its primary
controller is unregistered.

Signed-off-by: Lukasz Maniak <lukasz.maniak@linux.intel.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>


  Commit: 1e9c685ec76e3b10de29c4ac7ad02d86cb5aeff1
      
https://github.com/qemu/qemu/commit/1e9c685ec76e3b10de29c4ac7ad02d86cb5aeff1
  Author: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
  Date:   2022-06-23 (Thu, 23 Jun 2022)

  Changed paths:
    M hw/nvme/ctrl.c
    M hw/nvme/nvme.h
    M hw/nvme/trace-events

  Log Message:
  -----------
  hw/nvme: Implement the Function Level Reset

This patch implements the Function Level Reset, a feature currently not
implemented for the Nvme device, while listed as a mandatory ("shall")
in the 1.4 spec.

The implementation reuses FLR-related building blocks defined for the
pci-bridge module, and follows the same logic:
    - FLR capability is advertised in the PCIE config,
    - custom pci_write_config callback detects a write to the trigger
      register and performs the PCI reset,
    - which, eventually, calls the custom dc->reset handler.

Depending on reset type, parts of the state should (or should not) be
cleared. To distinguish the type of reset, an additional parameter is
passed to the reset function.

This patch also enables advertisement of the Power Management PCI
capability. The main reason behind it is to announce the no_soft_reset=1
bit, to signal SR-IOV support where each VF can be reset individually.

The implementation purposedly ignores writes to the PMCS.PS register,
as even such naïve behavior is enough to correctly handle the D3->D0
transition.

It’s worth to note, that the power state transition back to to D3, with
all the corresponding side effects, wasn't and stil isn't handled
properly.

Signed-off-by: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>


  Commit: decc02614f90ff5583807d89888fec47dfec23e1
      
https://github.com/qemu/qemu/commit/decc02614f90ff5583807d89888fec47dfec23e1
  Author: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
  Date:   2022-06-23 (Thu, 23 Jun 2022)

  Changed paths:
    M hw/nvme/ctrl.c
    M hw/nvme/nvme.h

  Log Message:
  -----------
  hw/nvme: Make max_ioqpairs and msix_qsize configurable in runtime

The NVMe device defines two properties: max_ioqpairs, msix_qsize. Having
them as constants is problematic for SR-IOV support.

SR-IOV introduces virtual resources (queues, interrupts) that can be
assigned to PF and its dependent VFs. Each device, following a reset,
should work with the configured number of queues. A single constant is
no longer sufficient to hold the whole state.

This patch tries to solve the problem by introducing additional
variables in NvmeCtrl’s state. The variables for, e.g., managing queues
are therefore organized as:
 - n->params.max_ioqpairs – no changes, constant set by the user
 - n->(mutable_state) – (not a part of this patch) user-configurable,
                        specifies number of queues available _after_
                        reset
 - n->conf_ioqpairs - (new) used in all the places instead of the ‘old’
                      n->params.max_ioqpairs; initialized in realize()
                      and updated during reset() to reflect user’s
                      changes to the mutable state

Since the number of available i/o queues and interrupts can change in
runtime, buffers for sq/cqs and the MSIX-related structures are
allocated big enough to handle the limits, to completely avoid the
complicated reallocation. A helper function (nvme_update_msixcap_ts)
updates the corresponding capability register, to signal configuration
changes.

Signed-off-by: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>


  Commit: 3bfcc51737a939d909e42fb7a93c11b68549a613
      
https://github.com/qemu/qemu/commit/3bfcc51737a939d909e42fb7a93c11b68549a613
  Author: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
  Date:   2022-06-23 (Thu, 23 Jun 2022)

  Changed paths:
    M hw/nvme/ctrl.c
    M hw/nvme/nvme.h

  Log Message:
  -----------
  hw/nvme: Remove reg_size variable and update BAR0 size calculation

The n->reg_size parameter unnecessarily splits the BAR0 size calculation
in two phases; removed to simplify the code.

With all the calculations done in one place, it seems the pow2ceil,
applied originally to reg_size, is unnecessary. The rounding should
happen as the last step, when BAR size includes Nvme registers, queue
registers, and MSIX-related space.

Finally, the size of the mmio memory region is extended to cover the 1st
4KiB padding (see the map below). Access to this range is handled as
interaction with a non-existing queue and generates an error trace, so
actually nothing changes, while the reg_size variable is no longer needed.

    --------------------
    |      BAR0        |
    --------------------
    [Nvme Registers    ]
    [Queues            ]
    [power-of-2 padding] - removed in this patch
    [4KiB padding (1)  ]
    [MSIX TABLE        ]
    [4KiB padding (2)  ]
    [MSIX PBA          ]
    [power-of-2 padding]

Signed-off-by: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>


  Commit: aa817713376195cc5cd861183fc7f953a7b60d5d
      
https://github.com/qemu/qemu/commit/aa817713376195cc5cd861183fc7f953a7b60d5d
  Author: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
  Date:   2022-06-23 (Thu, 23 Jun 2022)

  Changed paths:
    M hw/nvme/ctrl.c

  Log Message:
  -----------
  hw/nvme: Calculate BAR attributes in a function

An NVMe device with SR-IOV capability calculates the BAR size
differently for PF and VF, so it makes sense to extract the common code
to a separate function.

Signed-off-by: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>


  Commit: 746d42b13368e18856dccf16bd39e04d02feec09
      
https://github.com/qemu/qemu/commit/746d42b13368e18856dccf16bd39e04d02feec09
  Author: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
  Date:   2022-06-23 (Thu, 23 Jun 2022)

  Changed paths:
    M hw/nvme/ctrl.c
    M hw/nvme/nvme.h
    M include/block/nvme.h

  Log Message:
  -----------
  hw/nvme: Initialize capability structures for primary/secondary controllers

With four new properties:
 - sriov_v{i,q}_flexible,
 - sriov_max_v{i,q}_per_vf,
one can configure the number of available flexible resources, as well as
the limits. The primary and secondary controller capability structures
are initialized accordingly.

Since the number of available queues (interrupts) now varies between
VF/PF, BAR size calculation is also adjusted.

Signed-off-by: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>


  Commit: 11871f53ef8ef8ff80ded133677230caf6261ac9
      
https://github.com/qemu/qemu/commit/11871f53ef8ef8ff80ded133677230caf6261ac9
  Author: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
  Date:   2022-06-23 (Thu, 23 Jun 2022)

  Changed paths:
    M hw/nvme/ctrl.c
    M hw/nvme/nvme.h
    M hw/nvme/trace-events
    M include/block/nvme.h

  Log Message:
  -----------
  hw/nvme: Add support for the Virtualization Management command

With the new command one can:
 - assign flexible resources (queues, interrupts) to primary and
   secondary controllers,
 - toggle the online/offline state of given controller.

Signed-off-by: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>


  Commit: 751babf5bb7f7e77f2676a9a9e54cc75a947b81b
      
https://github.com/qemu/qemu/commit/751babf5bb7f7e77f2676a9a9e54cc75a947b81b
  Author: Lukasz Maniak <lukasz.maniak@linux.intel.com>
  Date:   2022-06-23 (Thu, 23 Jun 2022)

  Changed paths:
    M docs/system/devices/nvme.rst

  Log Message:
  -----------
  docs: Add documentation for SR-IOV and Virtualization Enhancements

Documentation describes 5 new parameters being added regarding SR-IOV:
sriov_max_vfs
sriov_vq_flexible
sriov_vi_flexible
sriov_max_vi_per_vf
sriov_max_vq_per_vf

The description also includes the simplest possible QEMU invocation
and the series of NVMe commands required to enable SR-IOV support.

Signed-off-by: Lukasz Maniak <lukasz.maniak@linux.intel.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>


  Commit: b7698b917abcbe673cbffc15ee41d95d3daa4af3
      
https://github.com/qemu/qemu/commit/b7698b917abcbe673cbffc15ee41d95d3daa4af3
  Author: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
  Date:   2022-06-23 (Thu, 23 Jun 2022)

  Changed paths:
    M hw/nvme/ctrl.c

  Log Message:
  -----------
  hw/nvme: Update the initalization place for the AER queue

This patch updates the initialization place for the AER queue, so it’s
initialized once, at controller initialization, and not every time
controller is enabled.

While the original version works for a non-SR-IOV device, as it’s hard
to interact with the controller if it’s not enabled, the multiple
reinitialization is not necessarily correct.

With the SR/IOV feature enabled a segfault can happen: a VF can have its
controller disabled, while a namespace can still be attached to the
controller through the parent PF. An event generated in such case ends
up on an uninitialized queue.

While it’s an interesting question whether a VF should support AER in
the first place, I don’t think it must be answered today.

Signed-off-by: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>


  Commit: 58660bfa3694a2d05eacb8dca7c28ffa08917578
      
https://github.com/qemu/qemu/commit/58660bfa3694a2d05eacb8dca7c28ffa08917578
  Author: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
  Date:   2022-06-23 (Thu, 23 Jun 2022)

  Changed paths:
    M hw/acpi/pcihp.c

  Log Message:
  -----------
  hw/acpi: Make the PCI hot-plug aware of SR-IOV

PCI device capable of SR-IOV support is a new, still-experimental
feature with only a single working example of the Nvme device.

This patch in an attempt to fix a double-free problem when a
SR-IOV-capable Nvme device is hot-unplugged in the following scenario:

Qemu CLI:
---------
-device pcie-root-port,slot=0,id=rp0
-device nvme-subsys,id=subsys0
-device 
nvme,id=nvme0,bus=rp0,serial=deadbeef,subsys=subsys0,sriov_max_vfs=1,sriov_vq_flexible=2,sriov_vi_flexible=1

Guest OS:
---------
sudo nvme virt-mgmt /dev/nvme0 -c 0 -r 1 -a 1 -n 0
sudo nvme virt-mgmt /dev/nvme0 -c 0 -r 0 -a 1 -n 0
echo 1 > /sys/bus/pci/devices/0000:01:00.0/reset
sleep 1
echo 1 > /sys/bus/pci/devices/0000:01:00.0/sriov_numvfs
nvme virt-mgmt /dev/nvme0 -c 1 -r 1 -a 8 -n 1
nvme virt-mgmt /dev/nvme0 -c 1 -r 0 -a 8 -n 2
nvme virt-mgmt /dev/nvme0 -c 1 -r 0 -a 9 -n 0
sleep 2
echo 01:00.1 > /sys/bus/pci/drivers/nvme/bind

Qemu monitor:
-------------
device_del nvme0

Explanation of the problem and the proposed solution:

1) The current SR-IOV implementation assumes it’s the PhysicalFunction
   that creates and deletes VirtualFunctions.
2) It’s a design decision (the Nvme device at least) for the VFs to be
   of the same class as PF. Effectively, they share the dc->hotpluggable
   value.
3) When a VF is created, it’s added as a child node to PF’s PCI bus
   slot.
4) Monitor/device_del triggers the ACPI mechanism. The implementation is
   not aware of SR/IOV and ejects PF’s PCI slot, directly unrealizing all
   hot-pluggable (!acpi_pcihp_pc_no_hotplug) children nodes.
5) VFs are unrealized directly, and it doesn’t work well with (1).
   SR/IOV structures are not updated, so when it’s PF’s turn to be
   unrealized, it works on stale pointers to already-deleted VFs.

The proposed fix is to make the PCI ACPI code aware of SR/IOV.

Signed-off-by: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>


  Commit: cc9bcee265a22f6e2391eaa76a0dc2b34469b2a7
      
https://github.com/qemu/qemu/commit/cc9bcee265a22f6e2391eaa76a0dc2b34469b2a7
  Author: Klaus Jensen <k.jensen@samsung.com>
  Date:   2022-06-23 (Thu, 23 Jun 2022)

  Changed paths:
    M hw/nvme/ctrl.c

  Log Message:
  -----------
  hw/nvme: clean up CC register write logic

The SRIOV series exposed an issued with how CC register writes are
handled and how CSTS is set in response to that. Specifically, after
applying the SRIOV series, the controller could end up in a state with
CC.EN set to '1' but with CSTS.RDY cleared to '0', causing drivers to
expect CSTS.RDY to transition to '1' but timing out.

Clean this up.

Reviewed-by: Łukasz Gieryk <lukasz.gieryk@linux.intel.com>
Reviewed-by: Lukasz Maniak <lukasz.maniak@linux.intel.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>


  Commit: b9147a3aa1d4aaab394e32ac1e8ef5d0e05a81fe
      
https://github.com/qemu/qemu/commit/b9147a3aa1d4aaab394e32ac1e8ef5d0e05a81fe
  Author: Klaus Jensen <k.jensen@samsung.com>
  Date:   2022-06-23 (Thu, 23 Jun 2022)

  Changed paths:
    M hw/nvme/ctrl.c

  Log Message:
  -----------
  Revert "hw/block/nvme: add support for sgl bit bucket descriptor"

This reverts commit d97eee64fef35655bd06f5c44a07fdb83a6274ae.

The emulated controller correctly accounts for not including bit buckets
in the controller-to-host data transfer, however it doesn't correctly
account for the holes for the on-disk data offsets.

Reported-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>


  Commit: 98836e8e012a959ec515c041e4fdd7f2ae87ae16
      
https://github.com/qemu/qemu/commit/98836e8e012a959ec515c041e4fdd7f2ae87ae16
  Author: Klaus Jensen <k.jensen@samsung.com>
  Date:   2022-06-23 (Thu, 23 Jun 2022)

  Changed paths:
    M hw/nvme/ctrl.c

  Log Message:
  -----------
  hw/nvme: clear aen mask on reset

The internally maintained AEN mask is not cleared on reset. Fix this.

Reviewed-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>


  Commit: 3a821c52e1a30ecd9a436f2c67cc66b5628c829f
      
https://github.com/qemu/qemu/commit/3a821c52e1a30ecd9a436f2c67cc66b5628c829f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-23 (Thu, 23 Jun 2022)

  Changed paths:
    M docs/system/devices/nvme.rst
    M hw/acpi/pcihp.c
    M hw/nvme/ctrl.c
    M hw/nvme/ns.c
    M hw/nvme/nvme.h
    M hw/nvme/subsys.c
    M hw/nvme/trace-events
    M include/block/nvme.h
    M include/hw/pci/pci_ids.h

  Log Message:
  -----------
  Merge tag 'nvme-next-pull-request' of git://git.infradead.org/qemu-nvme into 
staging

hw/nvme updates

- sriov functionality
- odd fixes

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# gpg: Signature made Thu 23 Jun 2022 02:28:37 PM PDT
# gpg:                using RSA key 522833AA75E2DCE6A24766C04DE1AF316D4F0DE9
# gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [unknown]
# gpg:                 aka "Klaus Jensen <k.jensen@samsung.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468  4272 63D5 6FC5 E55D A838
#      Subkey fingerprint: 5228 33AA 75E2 DCE6 A247  66C0 4DE1 AF31 6D4F 0DE9

* tag 'nvme-next-pull-request' of git://git.infradead.org/qemu-nvme:
  hw/nvme: clear aen mask on reset
  Revert "hw/block/nvme: add support for sgl bit bucket descriptor"
  hw/nvme: clean up CC register write logic
  hw/acpi: Make the PCI hot-plug aware of SR-IOV
  hw/nvme: Update the initalization place for the AER queue
  docs: Add documentation for SR-IOV and Virtualization Enhancements
  hw/nvme: Add support for the Virtualization Management command
  hw/nvme: Initialize capability structures for primary/secondary controllers
  hw/nvme: Calculate BAR attributes in a function
  hw/nvme: Remove reg_size variable and update BAR0 size calculation
  hw/nvme: Make max_ioqpairs and msix_qsize configurable in runtime
  hw/nvme: Implement the Function Level Reset
  hw/nvme: Add support for Secondary Controller List
  hw/nvme: Add support for Primary Controller Capabilities
  hw/nvme: Add support for SR-IOV

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/7db86fe2ed22...3a821c52e1a3



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