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[Qemu-commits] [qemu/qemu] efe159: MAINTAINERS: Cover hw/core/uboot_imag
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] efe159: MAINTAINERS: Cover hw/core/uboot_image.h within Ge... |
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Date: |
Fri, 10 Jun 2022 05:53:43 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: efe1592c43fe9b4053bf2987581a05736062a3cd
https://github.com/qemu/qemu/commit/efe1592c43fe9b4053bf2987581a05736062a3cd
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Cover hw/core/uboot_image.h within Generic Loader section
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220509091339.26016-1-alistair.francis@wdc.com>
Commit: de799beba7f927b2a1ed38128309316511311605
https://github.com/qemu/qemu/commit/de799beba7f927b2a1ed38128309316511311605
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/insn_trans/trans_rvm.c.inc
Log Message:
-----------
target/riscv: add support for zmmul extension v0.1
Add support for the zmmul extension v0.1. This extension includes all
multiplication operations from the M extension but not the divide ops.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220531030732.3850-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f9a461b2d3b8ef4f36b7891eb4040693ee071719
https://github.com/qemu/qemu/commit/f9a461b2d3b8ef4f36b7891eb4040693ee071719
Author: Atish Patra <atishp@rivosinc.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: virt: Generate fw_cfg DT node correctly
fw_cfg DT node is generated after the create_fdt without any check
if the DT is being loaded from the commandline. This results in
FDT_ERR_EXISTS error if dtb is loaded from the commandline.
Generate fw_cfg node only if the DT is not loaded from the commandline.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220526203500.847165-1-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 40244040a7ac00d40db4dea02234d13502c30112
https://github.com/qemu/qemu/commit/40244040a7ac00d40db4dea02234d13502c30112
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M hw/intc/sifive_plic.c
Log Message:
-----------
hw/intc: sifive_plic: Avoid overflowing the addr_config buffer
Since commit ad40be27 "target/riscv: Support start kernel directly by
KVM" we have been overflowing the addr_config on "M,MS..."
configurations, as reported https://gitlab.com/qemu-project/qemu/-/issues/1050.
This commit changes the loop in sifive_plic_create() from iterating over
the number of harts to just iterating over the addr_config. The
addr_config is based on the hart_config, and will contain interrup details
for all harts. This way we can't iterate past the end of addr_config.
Fixes: ad40be27084536 ("target/riscv: Support start kernel directly by KVM")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1050
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220601013631.196854-1-alistair.francis@opensource.wdc.com>
Commit: af9751316e53cdf7e98131afe6928a5f4445fe16
https://github.com/qemu/qemu/commit/af9751316e53cdf7e98131afe6928a5f4445fe16
Author: Jamie Iles <jamie@nuviainc.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M hw/arm/armv7m.c
M hw/arm/boot.c
M hw/core/generic-loader.c
M hw/core/loader.c
M hw/i386/x86.c
M hw/riscv/boot.c
M include/hw/loader.h
Log Message:
-----------
hw/core/loader: return image sizes as ssize_t
Various loader functions return an int which limits images to 2GB which
is fine for things like a BIOS/kernel image, but if we want to be able
to load memory images or large ramdisks then any file over 2GB would
silently fail to load.
Cc: Luc Michel <lmichel@kalray.eu>
Signed-off-by: Jamie Iles <jamie@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Luc Michel <lmichel@kalray.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211111141141.3295094-2-jamie@nuviainc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8f42415fc1d1bb462f2001bf5e2ad3b78f14b2e3
https://github.com/qemu/qemu/commit/8f42415fc1d1bb462f2001bf5e2ad3b78f14b2e3
Author: Andrew Bresticker <abrestic@rivosinc.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Wake on VS-level external interrupts
Whether or not VSEIP is pending isn't reflected in env->mip and must
instead be determined from hstatus.vgein and hgeip. As a result a
CPU in WFI won't wake on a VSEIP, which violates the WFI behavior as
specified in the privileged ISA. Just use riscv_cpu_all_pending()
instead, which already accounts for VSEIP.
Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220531210544.181322-1-abrestic@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d1d8541217ce8a23e9e751cd868c7d618817134a
https://github.com/qemu/qemu/commit/d1d8541217ce8a23e9e751cd868c7d618817134a
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/debug.c
Log Message:
-----------
target/riscv/debug.c: keep experimental rv128 support working
Add an MXL_RV128 case in two switches so that no error is triggered when
using the -cpu x-rv128 option.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220602155246.38837-1-frederic.petrot@univ-grenoble-alpes.fr>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8a085fb2ad812bf06145779bbb6a18a3e7439771
https://github.com/qemu/qemu/commit/8a085fb2ad812bf06145779bbb6a18a3e7439771
Author: eopXD <yueh.ting.chen@gmail.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
No functional change intended in this commit.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-1@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 25eae0486db6e24f86550e3c42af2b17cc43ddbf
https://github.com/qemu/qemu/commit/25eae0486db6e24f86550e3c42af2b17cc43ddbf
Author: eopXD <yueh.ting.chen@gmail.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: rvv: Prune redundant access_type parameter passed
No functional change intended in this commit.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-2@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c7b8a4213b0dba710e31d633e17e661151c3d23a
https://github.com/qemu/qemu/commit/c7b8a4213b0dba710e31d633e17e661151c3d23a
Author: eopXD <yueh.ting.chen@gmail.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: rvv: Rename ambiguous esz
No functional change intended in this commit.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-3@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 41d3d7f76aa7060c0cbc1c8b3a9767a5997b231a
https://github.com/qemu/qemu/commit/41d3d7f76aa7060c0cbc1c8b3a9767a5997b231a
Author: eopXD <yueh.ting.chen@gmail.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Early exit when vstart >= vl
According to v-spec (section 5.4):
When vstart ≥ vl, there are no body elements, and no elements are
updated in any destination vector register group, including that
no tail elements are updated with agnostic values.
vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions themselves
require vstart to be zero. So they don't need the early exit.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-4@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f1eed927fb3a1212af8e324cf242cf6f4bd6fd04
https://github.com/qemu/qemu/commit/f1eed927fb3a1212af8e324cf242cf6f4bd6fd04
Author: eopXD <eop.chen@sifive.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/internals.h
M target/riscv/translate.c
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: rvv: Add tail agnostic for vv instructions
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibility for agnostic elements according to
v-spec. The main intent of this patch-set tries to add option that
can distinguish between tail policies. Setting agnostic elements to
all 1s allows QEMU to express this.
This is the first commit regarding the optional tail agnostic
behavior. Follow-up commits will add this optional behavior
for all rvv instructions.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-5@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 752614cab8e61bb6ba96cee1ec127eba6c35398e
https://github.com/qemu/qemu/commit/752614cab8e61bb6ba96cee1ec127eba6c35398e
Author: eopXD <yueh.ting.chen@gmail.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/translate.c
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: rvv: Add tail agnostic for vector load / store instructions
Destination register of unit-stride mask load and store instructions are
always written with a tail-agnostic policy.
A vector segment load / store instruction may contain fractional lmul
with nf * lmul > 1. The rest of the elements in the last register should
be treated as tail elements.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-6@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5c19fc156e5cea2516085c487eb72cdb331c54b6
https://github.com/qemu/qemu/commit/5c19fc156e5cea2516085c487eb72cdb331c54b6
Author: eopXD <yueh.ting.chen@gmail.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/internals.h
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
`vmadc` and `vmsbc` produces a mask value, they always operate with
a tail agnostic policy.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-7@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7b1bff41c1524e5dc1c2815f68b0454656539993
https://github.com/qemu/qemu/commit/7b1bff41c1524e5dc1c2815f68b0454656539993
Author: eopXD <yueh.ting.chen@gmail.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: rvv: Add tail agnostic for vector integer shift instructions
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-8@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 38581e5c9a99d2ff9244709cb3577b06a1310006
https://github.com/qemu/qemu/commit/38581e5c9a99d2ff9244709cb3577b06a1310006
Author: eopXD <yueh.ting.chen@gmail.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: rvv: Add tail agnostic for vector integer comparison
instructions
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-9@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 89a32de2d57591006d4a5d76e664b0b01c6998dc
https://github.com/qemu/qemu/commit/89a32de2d57591006d4a5d76e664b0b01c6998dc
Author: eopXD <yueh.ting.chen@gmail.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: rvv: Add tail agnostic for vector integer merge and move
instructions
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-10@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 09106eed3041d5eb57dd768332146abe6d86e0e4
https://github.com/qemu/qemu/commit/09106eed3041d5eb57dd768332146abe6d86e0e4
Author: eopXD <yueh.ting.chen@gmail.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic
instructions
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-11@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5eacf7d8a0fb19ea4d87eb678462fdb9a29b9190
https://github.com/qemu/qemu/commit/5eacf7d8a0fb19ea4d87eb678462fdb9a29b9190
Author: eopXD <yueh.ting.chen@gmail.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: rvv: Add tail agnostic for vector floating-point instructions
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-12@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: df4f52a7582c5cd8d2d2f73684996ebc18ac72e3
https://github.com/qemu/qemu/commit/df4f52a7582c5cd8d2d2f73684996ebc18ac72e3
Author: eopXD <yueh.ting.chen@gmail.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: rvv: Add tail agnostic for vector reduction instructions
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-13@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: acc6ffd482f6b0435bea7434eb5b13441c6d4a33
https://github.com/qemu/qemu/commit/acc6ffd482f6b0435bea7434eb5b13441c6d4a33
Author: eopXD <yueh.ting.chen@gmail.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: rvv: Add tail agnostic for vector mask instructions
The tail elements in the destination mask register are updated under
a tail-agnostic policy.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-14@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 803963f7cb7220be0c80d9acd87a0ebea167f35e
https://github.com/qemu/qemu/commit/803963f7cb7220be0c80d9acd87a0ebea167f35e
Author: eopXD <yueh.ting.chen@gmail.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: rvv: Add tail agnostic for vector permutation instructions
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-15@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b8312675d62b878d6647065f01c2c1337a74d4ee
https://github.com/qemu/qemu/commit/b8312675d62b878d6647065f01c2c1337a74d4ee
Author: eopXD <eop.chen@sifive.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail
agnostic behavior
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibility for agnostic elements according to
v-spec. The main intent of this patch-set tries to add option that
can distinguish between tail policies. Setting agnostic elements to
all 1s allows QEMU to express this.
This commit adds option 'rvv_ta_all_1s' is added to enable the
behavior, it is default as disabled.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-16@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 26b2bc58599c02b35e55afbd1bd050faa3d187c2
https://github.com/qemu/qemu/commit/26b2bc58599c02b35e55afbd1bd050faa3d187c2
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Don't expose the CPU properties on names CPUs
There are currently two types of RISC-V CPUs:
- Generic CPUs (base or any) that allow complete custimisation
- "Named" CPUs that match existing hardware
Users can use the base CPUs to custimise the extensions that they want, for
example -cpu rv64,v=true.
We originally exposed these as part of the named CPUs as well, but that was
by accident.
Exposing the CPU properties to named CPUs means that we accidently
enable extensions that don't exist on the CPUs by default. For example
the SiFive E CPU currently support the zba extension, which is a bug.
This patch instead only exposes the CPU extensions to the generic CPUs.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220608061437.314434-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 07314158f6aa4d2589520c194a7531b9364a8d54
https://github.com/qemu/qemu/commit/07314158f6aa4d2589520c194a7531b9364a8d54
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-06-10 (Fri, 10 Jun 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: trans_rvv: Avoid assert for RV32 and e64
When running a 32-bit guest, with a e64 vmv.v.x and vl_eq_vlmax set to
true the `tcg_debug_assert(vece <= MO_32)` will be triggered inside
tcg_gen_gvec_dup_i32().
This patch checks that condition and instead uses tcg_gen_gvec_dup_i64()
is required.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1028
Suggested-by: Robert Bu <robert.bu@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220608234701.369536-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b3cd3b5a66f0dddfe3d5ba2bef13cd4f5b89cde9
https://github.com/qemu/qemu/commit/b3cd3b5a66f0dddfe3d5ba2bef13cd4f5b89cde9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-09 (Thu, 09 Jun 2022)
Changed paths:
M MAINTAINERS
M hw/arm/armv7m.c
M hw/arm/boot.c
M hw/core/generic-loader.c
M hw/core/loader.c
M hw/i386/x86.c
M hw/intc/sifive_plic.c
M hw/riscv/boot.c
M hw/riscv/virt.c
M include/hw/loader.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/debug.c
M target/riscv/insn_trans/trans_rvm.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/internals.h
M target/riscv/translate.c
M target/riscv/vector_helper.c
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20220610' of github.com:alistair23/qemu into
staging
Fourth RISC-V PR for QEMU 7.1
* Update MAINTAINERS
* Add support for Zmmul extension
* Fixup FDT errors when supplying device tree from the command line for virt
machine
* Avoid overflowing the addr_config buffer in the SiFive PLIC
* Support -device loader addresses above 2GB
* Correctly wake from WFI on VS-level external interrupts
* Fixes for RV128 support
* Support Vector extension tail agnostic setting elements' bits to all 1s
* Don't expose the CPU properties on named CPUs
* Fix vector extension assert for RV32
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# gpg: Signature made Thu 09 Jun 2022 09:25:34 PM PDT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>"
[undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* tag 'pull-riscv-to-apply-20220610' of github.com:alistair23/qemu: (25 commits)
target/riscv: trans_rvv: Avoid assert for RV32 and e64
target/riscv: Don't expose the CPU properties on names CPUs
target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail
agnostic behavior
target/riscv: rvv: Add tail agnostic for vector permutation instructions
target/riscv: rvv: Add tail agnostic for vector mask instructions
target/riscv: rvv: Add tail agnostic for vector reduction instructions
target/riscv: rvv: Add tail agnostic for vector floating-point instructions
target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic
instructions
target/riscv: rvv: Add tail agnostic for vector integer merge and move
instructions
target/riscv: rvv: Add tail agnostic for vector integer comparison
instructions
target/riscv: rvv: Add tail agnostic for vector integer shift instructions
target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
target/riscv: rvv: Add tail agnostic for vector load / store instructions
target/riscv: rvv: Add tail agnostic for vv instructions
target/riscv: rvv: Early exit when vstart >= vl
target/riscv: rvv: Rename ambiguous esz
target/riscv: rvv: Prune redundant access_type parameter passed
target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
target/riscv/debug.c: keep experimental rv128 support working
target/riscv: Wake on VS-level external interrupts
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/9cc1bf1ebca5...b3cd3b5a66f0