[Qemu-commits] [qemu/qemu] d507bc: target/arm: Declare support for FEAT

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[Qemu-commits] [qemu/qemu] d507bc: target/arm: Declare support for FEAT_

From:	Richard Henderson
Subject:	[Qemu-commits] [qemu/qemu] d507bc: target/arm: Declare support for FEAT_RASv1p1
Date:	Thu, 09 Jun 2022 08:24:19 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: d507bc3b0541581fc9960f157968e80c02247255
      
https://github.com/qemu/qemu/commit/d507bc3b0541581fc9960f157968e80c02247255
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M docs/system/arm/emulation.rst
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Declare support for FEAT_RASv1p1

The architectural feature RASv1p1 introduces the following new
features:
 * new registers ERXPFGCDN_EL1, ERXPFGCTL_EL1 and ERXPFGF_EL1
 * new bits in the fine-grained trap registers that control traps
   for these new registers
 * new trap bits HCR_EL2.FIEN and SCR_EL3.FIEN that control traps
   for ERXPFGCDN_EL1, ERXPFGCTL_EL1, ERXPFGP_EL1
 * a larger number of the ERXMISC<n>_EL1 registers
 * the format of ERR<n>STATUS registers changes

The architecture permits that if ERRIDR_EL1.NUM is 0 (as it is for
QEMU) then all these new registers may UNDEF, and the HCR_EL2.FIEN
and SCR_EL3.FIEN bits may be RES0.  We don't have any ERR<n>STATUS
registers (again, because ERRIDR_EL1.NUM is 0).  QEMU does not yet
implement the fine-grained-trap extension.  So there is nothing we
need to implement to be compliant with the feature spec.  Make the
'max' CPU report the feature in its ID registers, and document it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220531114258.855804-1-peter.maydell@linaro.org


  Commit: 7ac610206a0049460c392c9559b51246af0afd6d
      
https://github.com/qemu/qemu/commit/7ac610206a0049460c392c9559b51246af0afd6d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M docs/system/arm/emulation.rst
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement FEAT_DoubleFault

The FEAT_DoubleFault extension adds the following:

 * All external aborts on instruction fetches and translation table
   walks for instruction fetches must be synchronous.  For QEMU this
   is already true.

 * SCR_EL3 has a new bit NMEA which disables the masking of SError
   interrupts by PSTATE.A when the SError interrupt is taken to EL3.
   For QEMU we only need to make the bit writable, because we have no
   sources of SError interrupts.

 * SCR_EL3 has a new bit EASE which causes synchronous external
   aborts taken to EL3 to be taken at the same entry point as SError.
   (Note that this does not mean that they are SErrors for purposes
   of PSTATE.A masking or that the syndrome register reports them as
   SErrors: it just means that the vector offset is different.)

 * The existing SCTLR_EL3.IESB has an effective value of 1 when
   SCR_EL3.NMEA is 1.  For QEMU this is a no-op because we don't need
   different behaviour based on IESB (we don't need to do anything to
   ensure that error exceptions are synchronized).

So for QEMU the things we need to change are:
 * Make SCR_EL3.{NMEA,EASE} writable
 * When taking a synchronous external abort at EL3, adjust the
   vector entry point if SCR_EL3.EASE is set
 * Advertise the feature in the ID registers

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220531151431.949322-1-peter.maydell@linaro.org


  Commit: 9323e79f10e5f5d8fffc3b307776173ca11faeae
      
https://github.com/qemu/qemu/commit/9323e79f10e5f5d8fffc3b307776173ca11faeae
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M accel/hvf/hvf-accel-ops.c
    M accel/kvm/kvm-all.c
    M accel/tcg/user-exec.c
    M docs/interop/vhost-user.rst
    M docs/specs/vmgenid.txt
    M hw/acpi/ghes.c
    M hw/intc/arm_gicv3_cpuif.c
    M hw/intc/arm_gicv3_dist.c
    M hw/intc/arm_gicv3_redist.c
    M hw/intc/riscv_aclint.c
    M hw/intc/riscv_aplic.c
    M hw/pci/shpc.c
    M hw/scsi/mfi.h
    M hw/sparc64/sun4u_iommu.c
    M hw/timer/sse-timer.c
    M python/qemu/machine/machine.py
    M target/arm/gdbstub.c
    M target/arm/helper.c
    M target/arm/hvf/hvf.c
    M target/arm/internals.h
    M target/i386/cpu-sysemu.c
    M target/i386/hvf/vmcs.h
    M target/i386/hvf/vmx.h
    M target/s390x/ioinst.c
    M tests/tcg/x86_64/system/boot.S

  Log Message:
  -----------
  Fix 'writeable' typos

We have about 30 instances of the typo/variant spelling 'writeable',
and over 500 of the more common 'writable'.  Standardize on the
latter.

Change produced with:

  sed -i -e 's/\([Ww][Rr][Ii][Tt]\)[Ee]\([Aa][Bb][Ll][Ee]\)/\1\2/g' $(git grep 
-il writeable)

and then hand-undoing the instance in linux-headers/linux/kvm.h.

Most of these changes are in comments or documentation; the
exceptions are:
 * a local variable in accel/hvf/hvf-accel-ops.c
 * a local variable in accel/kvm/kvm-all.c
 * the PMCR_WRITABLE_MASK macro in target/arm/internals.h
 * the EPT_VIOLATION_GPA_WRITABLE macro in target/i386/hvf/vmcs.h
   (which is never used anywhere)
 * the AR_TYPE_WRITABLE_MASK macro in target/i386/hvf/vmx.h
   (which is never used anywhere)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Message-id: 20220505095015.2714666-1-peter.maydell@linaro.org


  Commit: d2008b3355061ab0cca823739cd98045e769a809
      
https://github.com/qemu/qemu/commit/d2008b3355061ab0cca823739cd98045e769a809
  Author: Frederic Konrad <fkonrad@amd.com>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M hw/display/xlnx_dp.c
    M include/hw/display/xlnx_dp.h

  Log Message:
  -----------
  xlnx_dp: fix the wrong register size

The core and the vblend registers size are wrong, they should respectively be
0x3B0 and 0x1E0 according to:
  
https://www.xilinx.com/htmldocs/registers/ug1087/ug1087-zynq-ultrascale-registers.html.

Let's fix that and use macros when creating the mmio region.

Fixes: 58ac482a66d ("introduce xlnx-dp")
Signed-off-by: Frederic Konrad <fkonrad@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220601172353.3220232-2-fkonrad@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 759ae1b47e7e0203eb6881304b4bbf0d935fd550
      
https://github.com/qemu/qemu/commit/759ae1b47e7e0203eb6881304b4bbf0d935fd550
  Author: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M hw/display/xlnx_dp.c
    M include/hw/display/xlnx_dp.h

  Log Message:
  -----------
  xlnx_dp: Introduce a vblank signal

Add a periodic timer which raises vblank at a frequency of 30Hz.

Note that this is a migration compatibility break for the
xlnx-zcu102 board type.

Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Frederic Konrad <fkonrad@amd.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220601172353.3220232-3-fkonrad@xilinx.com
Changes by fkonrad:
  - Switched to transaction-based ptimer API.
  - Added the DP_INT_VBLNK_START macro.
Signed-off-by: Frederic Konrad <fkonrad@amd.com>
[PMM: bump vmstate version, add commit message note about
 compat break]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 39f40d02f6af8e4718100b6a3854e963c962cfd7
      
https://github.com/qemu/qemu/commit/39f40d02f6af8e4718100b6a3854e963c962cfd7
  Author: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M hw/display/xlnx_dp.c

  Log Message:
  -----------
  xlnx_dp: Fix the interrupt disable logic

Fix interrupt disable logic. Mask value 1 indicates that interrupts are
disabled.

Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Frederic Konrad <fkonrad@amd.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220601172353.3220232-4-fkonrad@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b3f5cc3fda5775b34aa52e111d50c9d10911b352
      
https://github.com/qemu/qemu/commit/b3f5cc3fda5775b34aa52e111d50c9d10911b352
  Author: Frederic Konrad <fkonrad@amd.com>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c

  Log Message:
  -----------
  xlnx-zynqmp: fix the irq mapping for the display port and its dma

When the display port has been initially implemented the device
driver wasn't using interrupts.  Now that the display port driver
waits for vblank interrupt it has been noticed that the irq mapping
is wrong.  So use the value from the linux device tree and the
ultrascale+ reference manual.

Signed-off-by: Frederic Konrad <fkonrad@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220601172353.3220232-5-fkonrad@xilinx.com
[PMM: refold lines in commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d8cca960a9a5dbd216d2331cef3cc72f2c7338e0
      
https://github.com/qemu/qemu/commit/d8cca960a9a5dbd216d2331cef3cc72f2c7338e0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Move stage_1_mmu_idx decl to internals.h

Move the decl from ptw.h to internals.h.  Provide an inline
version for user-only, just as we do for arm_stage1_mmu_idx.
Move an endif down to make the definition in helper.c be
system only.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8ae0886002aaf917601701df933617b2449e94b5
      
https://github.com/qemu/qemu/commit/8ae0886002aaf917601701df933617b2449e94b5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/meson.build
    A target/arm/ptw.c
    A target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move get_phys_addr to ptw.c

Begin moving all of the page table walking functions
out of helper.c, starting with get_phys_addr().

Create a temporary header file, "ptw.h", in which to
share declarations between the two C files while we
are moving functions.

Move a few declarations to "internals.h", which will
remain used by multiple C files.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f2d2f5ceb87e828546f7b544f1289193f3b920ce
      
https://github.com/qemu/qemu/commit/f2d2f5ceb87e828546f7b544f1289193f3b920ce
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move get_phys_addr_v5 to ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 53c038efb7a634dd5b6ede8eb034791c0dc83f43
      
https://github.com/qemu/qemu/commit/53c038efb7a634dd5b6ede8eb034791c0dc83f43
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move get_phys_addr_v6 to ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9a12fb366d442751603dc91ab5c5f9b7c828c783
      
https://github.com/qemu/qemu/commit/9a12fb366d442751603dc91ab5c5f9b7c828c783
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move get_phys_addr_pmsav5 to ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-6-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7d2e08c96077bcf7ed31b6b7c7b7066801b4b89d
      
https://github.com/qemu/qemu/commit/7d2e08c96077bcf7ed31b6b7c7b7066801b4b89d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move get_phys_addr_pmsav7_default to ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-7-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 1f2e87e5aba133ecf4c85000a61d5d760176dd6c
      
https://github.com/qemu/qemu/commit/1f2e87e5aba133ecf4c85000a61d5d760176dd6c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move get_phys_addr_pmsav7 to ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-8-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 730d5c31d8872e94d08877ad62f44cc49bc01c90
      
https://github.com/qemu/qemu/commit/730d5c31d8872e94d08877ad62f44cc49bc01c90
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move get_phys_addr_pmsav8 to ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-9-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: fedbaa0503d2c56d4ef58ca9a08121e2af7f5e54
      
https://github.com/qemu/qemu/commit/fedbaa0503d2c56d4ef58ca9a08121e2af7f5e54
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move pmsav8_mpu_lookup to ptw.c

This is the final user of get_phys_addr_pmsav7_default
within helper.c, so make it static within ptw.c.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-10-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c8e436c9f72bca95e37a155d6ead42d55f74eed2
      
https://github.com/qemu/qemu/commit/c8e436c9f72bca95e37a155d6ead42d55f74eed2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move pmsav7_use_background_region to ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-11-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2c1f429df38822ce6955224d784f1567f8af219f
      
https://github.com/qemu/qemu/commit/2c1f429df38822ce6955224d784f1567f8af219f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Move v8m_security_lookup to ptw.c

This function has one private helper, v8m_is_sau_exempt,
so move that at the same time.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-12-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 47ff5ba9d08c2c769794a59b88f1c19ada004730
      
https://github.com/qemu/qemu/commit/47ff5ba9d08c2c769794a59b88f1c19ada004730
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move m_is_{ppb,system}_region to ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-13-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 4c74ab157b056710b043a02c8101c449c179ae11
      
https://github.com/qemu/qemu/commit/4c74ab157b056710b043a02c8101c449c179ae11
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move get_level1_table_address to ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-14-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 966f4bb7d88554ed74e1006c516ddeef37e523d6
      
https://github.com/qemu/qemu/commit/966f4bb7d88554ed74e1006c516ddeef37e523d6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move combine_cacheattrs and subroutines to ptw.c

There are a handful of helpers for combine_cacheattrs
that we can move at the same time as the main entry point.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-15-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3283222acd7579cdbc338360fa6e611027f3c8dc
      
https://github.com/qemu/qemu/commit/3283222acd7579cdbc338360fa6e611027f3c8dc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move get_phys_addr_lpae to ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-16-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 11552bb0d95484c99233ec2f09c25261885d08ed
      
https://github.com/qemu/qemu/commit/11552bb0d95484c99233ec2f09c25261885d08ed
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move arm_{ldl,ldq}_ptw to ptw.c

Move the ptw load functions, plus 3 common subroutines:
S1_ptw_translate, ptw_attrs_are_device, and regime_translation_big_endian.
This also allows get_phys_addr_lpae to become static again.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-17-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: cd6bc4d51730e9cf47489029d078d18c3bcb3ae2
      
https://github.com/qemu/qemu/commit/cd6bc4d51730e9cf47489029d078d18c3bcb3ae2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/tlb_helper.c

  Log Message:
  -----------
  target/arm: Move {arm_s1_, }regime_using_lpae_format to tlb_helper.c

These functions are used for both page table walking and for
deciding what format in which to deliver exception results.
Since ptw.c is only present for system mode, put the functions
into tlb_helper.c.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-18-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 1c73d84807712aad4c7b2e4e753d6870ab81145d
      
https://github.com/qemu/qemu/commit/1c73d84807712aad4c7b2e4e753d6870ab81145d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move arm_pamax, pamax_map into ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-19-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f8526edc2f32b66a585618afc1dabd960a4c9b95
      
https://github.com/qemu/qemu/commit/f8526edc2f32b66a585618afc1dabd960a4c9b95
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move get_S1prot, get_S2prot to ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-20-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c5168785d208527c45f455619abe2539182a9fff
      
https://github.com/qemu/qemu/commit/c5168785d208527c45f455619abe2539182a9fff
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move check_s2_mmu_setup to ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-21-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2f0ec92e9488e1ac6c7293fe37a5f1c0e1737b36
      
https://github.com/qemu/qemu/commit/2f0ec92e9488e1ac6c7293fe37a5f1c0e1737b36
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move aa32_va_parameters to ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-22-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 4845d3be1239a956a4cedd5c2ca7863837487927
      
https://github.com/qemu/qemu/commit/4845d3be1239a956a4cedd5c2ca7863837487927
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move ap_to_tw_prot etc to ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-23-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0c23d56fc149ada0823648481c09b5d2047570f4
      
https://github.com/qemu/qemu/commit/0c23d56fc149ada0823648481c09b5d2047570f4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move regime_is_user to ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-24-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3b318aaeef120a71544771cd84884ccad5fdff0a
      
https://github.com/qemu/qemu/commit/3b318aaeef120a71544771cd84884ccad5fdff0a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move regime_ttbr to ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-25-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8db1a3a0bba1dbe71a3d363b23416a3c30653ddd
      
https://github.com/qemu/qemu/commit/8db1a3a0bba1dbe71a3d363b23416a3c30653ddd
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c
    R target/arm/ptw.h

  Log Message:
  -----------
  target/arm: Move regime_translation_disabled to ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-26-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 23971205cf38e63964b7e110df7d5a293277a48e
      
https://github.com/qemu/qemu/commit/23971205cf38e63964b7e110df7d5a293277a48e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Move arm_cpu_get_phys_page_attrs_debug to ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-27-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 1d2612553640a79e049708b9d87a9cd3ddb29af6
      
https://github.com/qemu/qemu/commit/1d2612553640a79e049708b9d87a9cd3ddb29af6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Move stage_1_mmu_idx, arm_stage1_mmu_idx to ptw.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-28-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5e79887ba67e22bfd890b72f94c482176a200fbc
      
https://github.com/qemu/qemu/commit/5e79887ba67e22bfd890b72f94c482176a200fbc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Pass CPUARMState to arm_ld[lq]_ptw

The use of ARM_CPU to recover env from cs calls
object_class_dynamic_cast, which shows up on the profile.
This is pointless, because all callers already have env, and
the reverse operation, env_cpu, is only pointer arithmetic.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-29-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f45ce4c35f5e0873bbbc3119eff8539610233b7e
      
https://github.com/qemu/qemu/commit/f45ce4c35f5e0873bbbc3119eff8539610233b7e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/translate-a64.c
    M target/arm/translate-a64.h
    M target/arm/translate-sve.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Rename TBFLAG_A64 ZCR_LEN to VL

With SME, the vector length does not only come from ZCR_ELx.
Comment that this is either NVL or SVL, like the pseudocode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8b599e5c0274cd5e4a33be6a10d6cd04631a74d1
      
https://github.com/qemu/qemu/commit/8b599e5c0274cd5e4a33be6a10d6cd04631a74d1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M linux-user/aarch64/signal.c
    M linux-user/aarch64/target_prctl.h
    M target/arm/cpu.h

  Log Message:
  -----------
  linux-user/aarch64: Introduce sve_vq

Add an interface function to extract the digested vector length
rather than the raw zcr_el[1] value.  This fixes an incorrect
return from do_prctl_set_vl where we didn't take into account
the set of vector lengths supported by the cpu.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 61a8c23a3b56607ee6e745b4cf7975170df88801
      
https://github.com/qemu/qemu/commit/61a8c23a3b56607ee6e745b4cf7975170df88801
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Remove route_to_el2 check from sve_exception_el

We handle this routing in raise_exception.  Promoting the value early
means that we can't directly compare FPEXC_EL and SVEEXC_EL.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 397d922c6248509c6d490f82088f00cbc716287c
      
https://github.com/qemu/qemu/commit/397d922c6248509c6d490f82088f00cbc716287c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Remove fp checks from sve_exception_el

Instead of checking these bits in fp_exception_el and
also in sve_exception_el, document that we must compare
the results.  The only place where we have not already
checked that FP EL is zero is in rebuild_hflags_a64.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 19668718ad188e1b6a162bb52357a67fd407c96c
      
https://github.com/qemu/qemu/commit/19668718ad188e1b6a162bb52357a67fd407c96c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Add el_is_in_host

This (newish) ARM pseudocode function is easier to work with
than open-coded tests for HCR_E2H etc.  Use of the function
will be staged into the code base in parts.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c6225bebc2498e9dd85bdd4de1840925650c7a9f
      
https://github.com/qemu/qemu/commit/c6225bebc2498e9dd85bdd4de1840925650c7a9f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Use el_is_in_host for sve_zcr_len_for_el

The ARM pseudocode function NVL uses this predicate now,
and I think it's a bit clearer.  Simplify the pseudocode
condition by noting that IsInHost is always false for EL1.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: aa4451b60e6a2b1bc4e9a8f6bbf90b266e2a4390
      
https://github.com/qemu/qemu/commit/aa4451b60e6a2b1bc4e9a8f6bbf90b266e2a4390
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Use el_is_in_host for sve_exception_el

The ARM pseudocode function CheckNormalSVEEnabled uses this
predicate now, and I think it's a bit clearer.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7d38cb92aad848b9c935588815d0b3a5e157aabb
      
https://github.com/qemu/qemu/commit/7d38cb92aad848b9c935588815d0b3a5e157aabb
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Hoist arm_is_el2_enabled check in sve_exception_el

This check is buried within arm_hcr_el2_eff(), but since we
have to have the explicit check for CPTR_EL2.TZ, we might as
well just check it once at the beginning of the block.

Once this is done, we can test HCR_EL2.{E2H,TGE} directly,
rather than going through arm_hcr_el2_eff().

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 87252bdecdafd49f8f4da6244a40415c27053bc3
      
https://github.com/qemu/qemu/commit/87252bdecdafd49f8f4da6244a40415c27053bc3
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset

We don't need to constrain the value set in zcr_el[1],
because it will be done by sve_zcr_len_for_el.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9b5f422559a528f4117aa9c3098fddf3d7c535ba
      
https://github.com/qemu/qemu/commit/9b5f422559a528f4117aa9c3098fddf3d7c535ba
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Merge aarch64_sve_zcr_get_valid_len into caller

This function is used only once, and will need modification
for Streaming SVE mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 886902ece71b5e795fea3e052a32f047d2f8fe33
      
https://github.com/qemu/qemu/commit/886902ece71b5e795fea3e052a32f047d2f8fe33
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/kvm64.c
    M target/arm/kvm_arm.h

  Log Message:
  -----------
  target/arm: Use uint32_t instead of bitmap for sve vq's

The bitmap need only hold 15 bits; bitmap is over-complicated.
We can simplify operations quite a bit with plain logical ops.

The introduction of SVE_VQ_POW2_MAP eliminates the need for
looping in order to search for powers of two.  Simply perform
the logical ops and use count leading or trailing zeros as
required to find the result.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5ef3cc563699d9b96e6b1acb15c7c02cf75d8266
      
https://github.com/qemu/qemu/commit/5ef3cc563699d9b96e6b1acb15c7c02cf75d8266
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/arch_dump.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/gdbstub64.c
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_el

This will be used for both Normal and Streaming SVE, and the value
does not necessarily come from ZCR_ELx.  While we're at it, emphasize
the units in which the value is returned.

Patch produced by
    git grep -l sve_zcr_len_for_el | \
    xargs -n1 sed -i 's/sve_zcr_len_for_el/sve_vqm1_for_el/g'

and then adding a function comment.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d1ce862602ac23de7b3e8541507fc78a8c4a5766
      
https://github.com/qemu/qemu/commit/d1ce862602ac23de7b3e8541507fc78a8c4a5766
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/sve_helper.c
    A target/arm/sve_ldst_internal.h

  Log Message:
  -----------
  target/arm: Split out load/store primitives to sve_ldst_internal.h

Begin creation of sve_ldst_internal.h by moving the primitives
that access host and tlb memory.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0b68112b399d77c765a0a5d9bb4f4b4e57541ee7
      
https://github.com/qemu/qemu/commit/0b68112b399d77c765a0a5d9bb4f4b4e57541ee7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/sve_helper.c
    M target/arm/sve_ldst_internal.h

  Log Message:
  -----------
  target/arm: Export sve contiguous ldst support functions

Export all of the support functions for performing bulk
fault analysis on a set of elements at contiguous addresses
controlled by a predicate.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 820e0bb9ce1941af82d14ec4a981792cb3697956
      
https://github.com/qemu/qemu/commit/820e0bb9ce1941af82d14ec4a981792cb3697956
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/sve_helper.c
    M target/arm/vec_internal.h

  Log Message:
  -----------
  target/arm: Move expand_pred_b to vec_internal.h

Put the inline function near the array declaration.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 05dd14bdfa89ffeb1a82b08776687d44b538185b
      
https://github.com/qemu/qemu/commit/05dd14bdfa89ffeb1a82b08776687d44b538185b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/mve_helper.c

  Log Message:
  -----------
  target/arm: Use expand_pred_b in mve_helper.c

Use the function instead of the array directly.

Because the function performs its own masking, via the uint8_t
parameter, we need to do nothing extra within the users: the bits
above the first 2 (_uh) or 4 (_uw) will be discarded by assignment
to the local bmask variables, and of course _uq uses the entire
uint64_t result.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a613cf2d4ae61fbcdf084103ea10de193bfbe169
      
https://github.com/qemu/qemu/commit/a613cf2d4ae61fbcdf084103ea10de193bfbe169
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/sve_helper.c
    M target/arm/vec_helper.c
    M target/arm/vec_internal.h

  Log Message:
  -----------
  target/arm: Move expand_pred_h to vec_internal.h

Move the data to vec_helper.c and the inline to vec_internal.h.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 72db2aa353a98bd3486c9e5ef7e31ae7cf934849
      
https://github.com/qemu/qemu/commit/72db2aa353a98bd3486c9e5ef7e31ae7cf934849
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/vec_helper.c
    M target/arm/vec_internal.h

  Log Message:
  -----------
  target/arm: Export bfdotadd from vec_helper.c

We will need this over in sme_helper.c.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f305bf9436896b4cd9ef622034e166b024780874
      
https://github.com/qemu/qemu/commit/f305bf9436896b4cd9ef622034e166b024780874
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Add isar_feature_aa64_sme

This will be used for implementing FEAT_SME.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 414c54d515dba16bfaef643a8acec200c05f229a
      
https://github.com/qemu/qemu/commit/414c54d515dba16bfaef643a8acec200c05f229a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/kvm64.c

  Log Message:
  -----------
  target/arm: Add ID_AA64SMFR0_EL1

This register is allocated from the existing block of id registers,
so it is already RES0 for cpus that do not implement SME.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 028f2361d0c2d28d6f918fe618f389228ac22b60
      
https://github.com/qemu/qemu/commit/028f2361d0c2d28d6f918fe618f389228ac22b60
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-06-09 (Thu, 09 Jun 2022)

  Changed paths:
    M accel/hvf/hvf-accel-ops.c
    M accel/kvm/kvm-all.c
    M accel/tcg/user-exec.c
    M docs/interop/vhost-user.rst
    M docs/specs/vmgenid.txt
    M docs/system/arm/emulation.rst
    M hw/acpi/ghes.c
    M hw/arm/xlnx-zynqmp.c
    M hw/display/xlnx_dp.c
    M hw/intc/arm_gicv3_cpuif.c
    M hw/intc/arm_gicv3_dist.c
    M hw/intc/arm_gicv3_redist.c
    M hw/intc/riscv_aclint.c
    M hw/intc/riscv_aplic.c
    M hw/pci/shpc.c
    M hw/scsi/mfi.h
    M hw/sparc64/sun4u_iommu.c
    M hw/timer/sse-timer.c
    M include/hw/display/xlnx_dp.h
    M linux-user/aarch64/signal.c
    M linux-user/aarch64/target_prctl.h
    M python/qemu/machine/machine.py
    M target/arm/arch_dump.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/gdbstub.c
    M target/arm/gdbstub64.c
    M target/arm/helper.c
    M target/arm/hvf/hvf.c
    M target/arm/internals.h
    M target/arm/kvm64.c
    M target/arm/kvm_arm.h
    M target/arm/meson.build
    M target/arm/mve_helper.c
    A target/arm/ptw.c
    M target/arm/sve_helper.c
    A target/arm/sve_ldst_internal.h
    M target/arm/tlb_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate-a64.h
    M target/arm/translate-sve.c
    M target/arm/translate.h
    M target/arm/vec_helper.c
    M target/arm/vec_internal.h
    M target/i386/cpu-sysemu.c
    M target/i386/hvf/vmcs.h
    M target/i386/hvf/vmx.h
    M target/s390x/ioinst.c
    M tests/tcg/x86_64/system/boot.S

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20220609' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * target/arm: Declare support for FEAT_RASv1p1
 * target/arm: Implement FEAT_DoubleFault
 * Fix 'writeable' typos
 * xlnx_dp: Implement vblank interrupt
 * target/arm: Move page-table-walk code to ptw.c
 * target/arm: Preparatory patches for SME support

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# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[full]

* tag 'pull-target-arm-20220609' of 
https://git.linaro.org/people/pmaydell/qemu-arm: (55 commits)
  target/arm: Add ID_AA64SMFR0_EL1
  target/arm: Add isar_feature_aa64_sme
  target/arm: Export bfdotadd from vec_helper.c
  target/arm: Move expand_pred_h to vec_internal.h
  target/arm: Use expand_pred_b in mve_helper.c
  target/arm: Move expand_pred_b to vec_internal.h
  target/arm: Export sve contiguous ldst support functions
  target/arm: Split out load/store primitives to sve_ldst_internal.h
  target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_el
  target/arm: Use uint32_t instead of bitmap for sve vq's
  target/arm: Merge aarch64_sve_zcr_get_valid_len into caller
  target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset
  target/arm: Hoist arm_is_el2_enabled check in sve_exception_el
  target/arm: Use el_is_in_host for sve_exception_el
  target/arm: Use el_is_in_host for sve_zcr_len_for_el
  target/arm: Add el_is_in_host
  target/arm: Remove fp checks from sve_exception_el
  target/arm: Remove route_to_el2 check from sve_exception_el
  linux-user/aarch64: Introduce sve_vq
  target/arm: Rename TBFLAG_A64 ZCR_LEN to VL
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/05911658cb46...028f2361d0c2
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