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[Qemu-commits] [qemu/qemu] 3d393b: docs: add minibmc section in aspeed d
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 3d393b: docs: add minibmc section in aspeed document |
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Date: |
Wed, 25 May 2022 13:44:44 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 3d393bb7d3348142868d2af651500949881d41f0
https://github.com/qemu/qemu/commit/3d393bb7d3348142868d2af651500949881d41f0
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: 2022-05-25 (Wed, 25 May 2022)
Changed paths:
M docs/system/arm/aspeed.rst
Log Message:
-----------
docs: add minibmc section in aspeed document
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220506031521.13254-2-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: fa699e80a80950ed31661dc8ea36a8b9aee9b094
https://github.com/qemu/qemu/commit/fa699e80a80950ed31661dc8ea36a8b9aee9b094
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-05-25 (Wed, 25 May 2022)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: Add fby35 machine type
Add the 'fby35-bmc' machine type based on the kernel DTS[1] and userspace
i2c setup scripts[2]. Undefined values are inherited from the AST2600-EVB.
Reference images can be found in Facebook OpenBMC Github Release assets
as "fby35.mtd". [3]
You can boot the reference images as follows (fby35 uses dual-flash):
qemu-system-arm -machine fby35-bmc \
-drive file=fby35.mtd,format=raw,if=mtd \
-drive file=fby35.mtd,format=raw,if=mtd \
-nographic
[1]
https://github.com/facebook/openbmc-linux/blob/412d5053258007117e94b1e36015aefc1301474b/arch/arm/boot/dts/aspeed-bmc-facebook-fby35.dts
[2]
https://github.com/facebook/openbmc/blob/e2294ff5d31dd65c248fe396a385286d6d5c463d/meta-facebook/meta-fby35/recipes-fby35/plat-utils/files/setup-dev.sh
[3] https://github.com/facebook/openbmc/releases
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220503225925.1798324-2-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 264a360ae0981a22e35b3e68b3eded1cac666afd
https://github.com/qemu/qemu/commit/264a360ae0981a22e35b3e68b3eded1cac666afd
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-05-25 (Wed, 25 May 2022)
Changed paths:
M docs/system/arm/aspeed.rst
Log Message:
-----------
docs: aspeed: Add fby35 board
Add fby35 to the list of Aspeed boards.
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20220506193354.990532-2-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 188052a13377ff1f88b433255005eb9082d048e5
https://github.com/qemu/qemu/commit/188052a13377ff1f88b433255005eb9082d048e5
Author: Iris Chen <irischenlj@fb.com>
Date: 2022-05-25 (Wed, 25 May 2022)
Changed paths:
M hw/block/m25p80.c
M tests/qtest/aspeed_gpio-test.c
M tests/qtest/aspeed_smc-test.c
M tests/qtest/libqtest.c
M tests/qtest/libqtest.h
Log Message:
-----------
hw: m25p80: allow write_enable latch get/set
The write_enable latch property is not currently exposed.
This commit makes it a modifiable property.
Signed-off-by: Iris Chen <irischenlj@fb.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220513055022.951759-1-irischenlj@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 699db71520502836efc0e9102b0ffa6b0e5d0758
https://github.com/qemu/qemu/commit/699db71520502836efc0e9102b0ffa6b0e5d0758
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-05-25 (Wed, 25 May 2022)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed: Introduce a get_irq AspeedSoCClass method
and make routine aspeed_soc_get_irq() common to all SoCs. This will be
useful to share code.
Cc: Jamin Lin <jamin_lin@aspeedtech.com>
Cc: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Peter Delevoryas <pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220516055620.2380197-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ab5e86053d16721b5b92780e23bc3104fdcb1f05
https://github.com/qemu/qemu/commit/ab5e86053d16721b5b92780e23bc3104fdcb1f05
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-05-25 (Wed, 25 May 2022)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw: aspeed: Add missing UART's
This adds the missing UART memory and IRQ mappings for the AST2400, AST2500,
AST2600, and AST1030.
This also includes the new UART interfaces added in the AST2600 and AST1030
from UART6 to UART13. The addresses and interrupt numbers for these two
later chips are identical.
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220516062328.298336-2-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c5e1bdb9e243ad5563196175415f42e459040367
https://github.com/qemu/qemu/commit/c5e1bdb9e243ad5563196175415f42e459040367
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-05-25 (Wed, 25 May 2022)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw: aspeed: Add uarts_num SoC attribute
AST2400 and AST2500 have 5 UART's, while the AST2600 and AST1030 have 13.
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220516062328.298336-3-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 94d10f42109a5ba23e26012722b16f0f479990cb
https://github.com/qemu/qemu/commit/94d10f42109a5ba23e26012722b16f0f479990cb
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-05-25 (Wed, 25 May 2022)
Changed paths:
M hw/arm/aspeed_ast10x0.c
Log Message:
-----------
hw: aspeed: Ensure AST1030 respects uart-default
The AST1030 machine initialization was not respecting the Aspeed SoC
property "uart-default", which specifies which UART should be connected to
the first serial device, it was just always connecting UART5. This doesn't
change any behavior, because the default value for "uart-default" is UART5,
but it makes it possible to override this in new machine definitions using
the AST1030.
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220516062328.298336-4-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 470253b6d05ecec4bf7c8f8616db779454414292
https://github.com/qemu/qemu/commit/470253b6d05ecec4bf7c8f8616db779454414292
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-05-25 (Wed, 25 May 2022)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw: aspeed: Introduce common UART init function
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220516062328.298336-5-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6827ff20b2975e84045ba356ba3e6aadc686a53c
https://github.com/qemu/qemu/commit/6827ff20b2975e84045ba356ba3e6aadc686a53c
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-05-25 (Wed, 25 May 2022)
Changed paths:
M hw/arm/aspeed_soc.c
Log Message:
-----------
hw: aspeed: Init all UART's with serial devices
Background:
AspeedMachineClass.uart_default specifies the serial console UART, which
usually corresponds to the "stdout-path" in the device tree.
The default value is UART5, since most boards use UART5 for this:
amc->uart_default = ASPEED_DEV_UART5;
Users can override AspeedMachineClass.uart_default in their board's machine
class init to specify something besides UART5. For example, for fuji-bmc:
amc->uart_default = ASPEED_DEV_UART1;
We only connect this one UART, of the 5 UART's on the AST2400 and AST2500
and the 13 UART's on the AST2600 and AST1030, to a serial device that QEMU
users can use. None of the other UART's are initialized, and the only way
to override this attribute is by creating a specialized board definition,
requiring QEMU source code changes and rebuilding.
The result of this is that if you want to get serial console output on a
board that uses UART3, you need to add a board definition. This was
encountered by Zev in OpenBMC. [1]
Changes:
This commit initializes all of the UART's present on each Aspeed chip with
serial devices and allows the QEMU user to connect as many or few as they
like to serial devices. For example, you can still run QEMU and just connect
stdout to the machine's default UART, without specifying any additional
serial devices:
qemu-system-arm -machine fuji-bmc \
-drive file=fuji.mtd,format=raw,if=mtd \
-nographic
However, if you don't want to add a special machine definition, you can now
manually configure UART1 to connect to stdout and get serial console output,
even if the machine's default is UART5:
qemu-system-arm -machine ast2600-evb \
-drive file=fuji.mtd,format=raw,if=mtd \
-serial null -serial mon:stdio -display none
In the example above, the first "-serial null" argument is connected to
UART5, and "-serial mon:stdio" is connected to UART1.
Another example: you can get serial console output from Wedge100, which uses
UART3, by reusing the palmetto AST2400 machine and rewiring the serial
device arguments:
qemu-system-arm -machine palmetto-bmc \
-drive file=wedge100.mtd,format=raw,if=mtd \
-serial null -serial null -serial null \
-serial mon:stdio -display none
There is a slight change in behavior introduced with this change: now, each
UART's memory-mapped IO region will have a serial device model connected to
it. Previously, all reads and writes to those regions would be ineffective
and return zero values, but now some values will be nonzero, even when the
user doesn't connect a serial device backend (like a socket, file, etc). For
example, the line status register might indicate that the transmit buffer is
empty now, whereas previously it might have always indicated it was full.
[1] https://lore.kernel.org/openbmc/YnzGnWjkYdMUUNyM@hatter.bewilderbeest.net/
[2] https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
[3]
https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220516062328.298336-6-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 7b1d21a8ba1e6091f1e54c74e7c664e26300accc
https://github.com/qemu/qemu/commit/7b1d21a8ba1e6091f1e54c74e7c664e26300accc
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: 2022-05-25 (Wed, 25 May 2022)
Changed paths:
M hw/gpio/aspeed_gpio.c
M hw/gpio/trace-events
Log Message:
-----------
hw/gpio Add GPIO read/write trace event.
Add GPIO read/write trace event for aspeed model.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220525053444.27228-2-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 17075ef244d4ca52f7f097927c72b0e09f8d8a5c
https://github.com/qemu/qemu/commit/17075ef244d4ca52f7f097927c72b0e09f8d8a5c
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: 2022-05-25 (Wed, 25 May 2022)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/gpio/aspeed_gpio.c
Log Message:
-----------
hw/gpio: Add ASPEED GPIO model for AST1030
AST1030 integrates one set of Parallel GPIO Controller
with maximum 151 control pins, which are 21 groups
(A~U, exclude pin: M6 M7 Q5 Q6 Q7 R0 R1 R4 R5 R6 R7 S0 S3 S4
S5 S6 S7 ) and the group T and U are input only.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220525053444.27228-3-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 247c00294a4b3cc694f24811eef07e57eb67aa82
https://github.com/qemu/qemu/commit/247c00294a4b3cc694f24811eef07e57eb67aa82
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: 2022-05-25 (Wed, 25 May 2022)
Changed paths:
M hw/gpio/aspeed_gpio.c
M include/hw/gpio/aspeed_gpio.h
Log Message:
-----------
hw/gpio support GPIO index mode for write operation.
It did not support GPIO index mode for read operation.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220525053444.27228-4-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 554c294514dc7445c5442266a50012ed774d63fe
https://github.com/qemu/qemu/commit/554c294514dc7445c5442266a50012ed774d63fe
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: 2022-05-25 (Wed, 25 May 2022)
Changed paths:
M hw/gpio/aspeed_gpio.c
M include/hw/gpio/aspeed_gpio.h
Log Message:
-----------
hw/gpio: replace HWADDR_PRIx with PRIx64
1. replace HWADDR_PRIx with PRIx64
2. fix indent issue
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220525053444.27228-5-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 52bcd997800fab67d57bea6d93e368f6f7a93b24
https://github.com/qemu/qemu/commit/52bcd997800fab67d57bea6d93e368f6f7a93b24
Author: Howard Chiu <howard_chiu@aspeedtech.com>
Date: 2022-05-25 (Wed, 25 May 2022)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: Add i2c devices for AST2600 EVB
Add EEPROM and LM75 temperature sensor according to hardware schematic
Signed-off-by: Howard Chiu <howard_chiu@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6291d2588fff71e670673e3d25ee85526e28da38
https://github.com/qemu/qemu/commit/6291d2588fff71e670673e3d25ee85526e28da38
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-25 (Wed, 25 May 2022)
Changed paths:
M docs/system/arm/aspeed.rst
M hw/arm/aspeed.c
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M hw/block/m25p80.c
M hw/gpio/aspeed_gpio.c
M hw/gpio/trace-events
M include/hw/arm/aspeed_soc.h
M include/hw/gpio/aspeed_gpio.h
M tests/qtest/aspeed_gpio-test.c
M tests/qtest/aspeed_smc-test.c
M tests/qtest/libqtest.c
M tests/qtest/libqtest.h
Log Message:
-----------
Merge tag 'pull-aspeed-20220525' of https://github.com/legoater/qemu into
staging
aspeed queue:
* Aspeed GPIO model extensions
* GPIO support for the Aspeed AST1030 SoC
* New fby35 machine (AST2600 based)
* Extra unit tests for the GPIO and SMC models
* Initialization of all UART with serial devices
* AST2600 EVB and Documentation update
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# gpg: Signature made Wed 25 May 2022 08:58:15 AM PDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20220525' of https://github.com/legoater/qemu:
hw/arm/aspeed: Add i2c devices for AST2600 EVB
hw/gpio: replace HWADDR_PRIx with PRIx64
hw/gpio support GPIO index mode for write operation.
hw/gpio: Add ASPEED GPIO model for AST1030
hw/gpio Add GPIO read/write trace event.
hw: aspeed: Init all UART's with serial devices
hw: aspeed: Introduce common UART init function
hw: aspeed: Ensure AST1030 respects uart-default
hw: aspeed: Add uarts_num SoC attribute
hw: aspeed: Add missing UART's
aspeed: Introduce a get_irq AspeedSoCClass method
hw: m25p80: allow write_enable latch get/set
docs: aspeed: Add fby35 board
hw/arm/aspeed: Add fby35 machine type
docs: add minibmc section in aspeed document
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/7929f75f34ad...6291d2588fff