qemu-commits
[Top][All Lists]
Advanced
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-commits] [qemu/qemu] d6cd3a: target/riscv: Fix VS mode hypervisor

From: Richard Henderson
Subject: [Qemu-commits] [qemu/qemu] d6cd3a: target/riscv: Fix VS mode hypervisor CSR access
Date: Tue, 24 May 2022 15:56:25 -0700 
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: d6cd3ae0ebdfab9922f932dc303e1faa618ea547
      
https://github.com/qemu/qemu/commit/d6cd3ae0ebdfab9922f932dc303e1faa618ea547
  Author: Dylan Reid <dylan@rivosinc.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Fix VS mode hypervisor CSR access

VS mode access to hypervisor CSRs should generate virtual, not illegal,
instruction exceptions.

Don't return early and indicate an illegal instruction exception when
accessing a hypervisor CSR from VS mode. Instead, fall through to the
`hmode` predicate to return the correct virtual instruction exception.

Signed-off-by: Dylan Reid <dgreid@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220506165456.297058-1-dgreid@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 02b511985e33d71859943682860f629ead5bd20a
      
https://github.com/qemu/qemu/commit/02b511985e33d71859943682860f629ead5bd20a
  Author: eopXD <eop.chen@sifive.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: rvv: Fix early exit condition for whole register load/store

Vector whole register load instructions have EEW encoded in the opcode,
so we shouldn't take SEW here. Vector whole register store instructions
are always EEW=8.

Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165181414065.18540.14828125053334599921-0@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 77046729f943ce2055648e8339ddd688dd67dd83
      
https://github.com/qemu/qemu/commit/77046729f943ce2055648e8339ddd688dd67dd83
  Author: Atish Patra <atishp@rivosinc.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M hw/intc/riscv_aclint.c

  Log Message:
  -----------
  hw/intc: Pass correct hartid while updating mtimecmp

timecmp update function should be invoked with hartid for which
timecmp is being updated. The following patch passes the incorrect
hartid to the update function.

Fixes: e2f01f3c2e13 ("hw/intc: Make RISC-V ACLINT mtime MMIO register writable")

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220513221458.1192933-1-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6047dcc2459fc6d1c49c4aa02e2e902dd3113856
      
https://github.com/qemu/qemu/commit/6047dcc2459fc6d1c49c4aa02e2e902dd3113856
  Author: Tsukasa OI <research_trasio@irq.a4lg.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Move Zhinx* extensions on ISA string

This commit moves ISA string conversion for Zhinx and Zhinxmin extensions.
Because extension category ordering of "H" is going to be after "V",
their ordering is going to be valid (on canonical order).

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: 
<7a988aedb249b6709f9ce5464ff359b60958ca54.1652181972.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a4a9a4432e2bf280a989ca344466d7375db7993f
      
https://github.com/qemu/qemu/commit/a4a9a4432e2bf280a989ca344466d7375db7993f
  Author: Tsukasa OI <research_trasio@irq.a4lg.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Add short-isa-string option

Because some operating systems don't correctly parse long ISA extension
string, this commit adds short-isa-string boolean option to disable
generating long ISA extension strings on Device Tree.

For instance, enabling Zfinx and Zdinx extensions and booting Linux (5.17 or
earlier) with FPU support caused a kernel panic.

Operating Systems which short-isa-string might be helpful:

1.  Linux (5.17 or earlier)
2.  FreeBSD (at least 14.0-CURRENT)
3.  OpenBSD (at least current development version)

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: 
<7c1fe5f06b0a7646a47e9bcdddb1042bb60c69c8.1652181972.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4bcfc391ac627155448951b45a8432eab91c2db9
      
https://github.com/qemu/qemu/commit/4bcfc391ac627155448951b45a8432eab91c2db9
  Author: Tsukasa OI <research_trasio@irq.a4lg.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M hw/riscv/spike.c
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: Make CPU config error handling generous (virt/spike)

If specified CPU configuration is not valid, not just it prints error
message, it aborts and generates core dumps (depends on the operating
system).  This kind of error handling should be used only when a serious
runtime error occurs.

This commit makes error handling on CPU configuration more generous on
virt/spike machines.  It now just prints error message and quits (without
coredumps and aborts).

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: 
<d17381d3ea4992808cf1894f379ca67220f61b45.1652509778.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 91a3387dc42b261e95eb402bf7d043b3a043209c
      
https://github.com/qemu/qemu/commit/91a3387dc42b261e95eb402bf7d043b3a043209c
  Author: Tsukasa OI <research_trasio@irq.a4lg.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M hw/riscv/opentitan.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)

If specified CPU configuration is not valid, not just it prints error
message, it aborts and generates core dumps (depends on the operating
system).  This kind of error handling should be used only when a serious
runtime error occurs.

This commit makes error handling on CPU configuration more generous on
sifive_e/u and opentitan machines.  It now just prints error message and
quits (without coredumps and aborts).

This is separate from spike/virt because it involves different type
(TYPE_RISCV_HART_ARRAY) on sifive_e/u and opentitan machines.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: 
<09e61e58a7543da44bdb0e0f5368afc8903b4aa6.1652509778.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 61cdf4593e4e1bf10cb58a5b8939414f4cd50834
      
https://github.com/qemu/qemu/commit/61cdf4593e4e1bf10cb58a5b8939414f4cd50834
  Author: Tsukasa OI <research_trasio@irq.a4lg.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Fix coding style on "G" expansion

Because ext_? members are boolean variables, operator `&&' should be
used instead of `&'.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Message-Id: 
<91633f8349253656dd08bc8dc36498a9c7538b10.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1d398ab9dcfb8f5fb4b9a285ea3167f7ba85976d
      
https://github.com/qemu/qemu/commit/1d398ab9dcfb8f5fb4b9a285ea3167f7ba85976d
  Author: Tsukasa OI <research_trasio@irq.a4lg.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Disable "G" by default

Because "G" virtual extension expands to "IMAFD", we cannot separately
disable extensions like "F" or "D" without disabling "G".  Because all
"IMAFD" are enabled by default, it's harmless to disable "G" by default.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: 
<cab7205f1d7668f642fa242386543334af6bc1bd.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 9f6b7da5d27b744ddbdba98ba8b89c710dd3c1b7
      
https://github.com/qemu/qemu/commit/9f6b7da5d27b744ddbdba98ba8b89c710dd3c1b7
  Author: Tsukasa OI <research_trasio@irq.a4lg.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Change "G" expansion

On ISA version 20190608 or later, "G" expands to "IMAFD_Zicsr_Zifencei".
Both "Zicsr" and "Zifencei" are enabled by default and "G" is supposed to
be (virtually) enabled as well, it should be safe to change its expansion.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: 
<d1b5be550a2893a0fd32c928f832d2ff7bfafe35.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1086504c6f46a2b3be90e887dddb4741bf8c500d
      
https://github.com/qemu/qemu/commit/1086504c6f46a2b3be90e887dddb4741bf8c500d
  Author: Tsukasa OI <research_trasio@irq.a4lg.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: FP extension requirements

QEMU allowed inconsistent configurations that made floating point
arithmetic effectively unusable.

This commit adds certain checks for consistent FP arithmetic:

-   F requires Zicsr
-   Zfinx requires Zicsr
-   Zfh/Zfhmin require F
-   D requires F
-   V requires D

Because F/D/Zicsr are enabled by default (and an error will not occur unless
we manually disable one or more of prerequisites), this commit just enforces
the user to give consistent combinations.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: 
<00e7b1c6060dab32ac7d49813b1ca84d3eb63298.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: bc573816692357e4c824d5c1df73987d3f0ea0c4
      
https://github.com/qemu/qemu/commit/bc573816692357e4c824d5c1df73987d3f0ea0c4
  Author: Tsukasa OI <research_trasio@irq.a4lg.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Move/refactor ISA extension checks

We should separate "check" and "configure" steps as possible.
This commit separates both steps except vector/Zfinx-related checks.

Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: 
<c3145fa37a529484cf3047c8cb9841e9effad4b0.1652583332.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8f1b6087983ed417ca142c0a7fd7080cc279e0f5
      
https://github.com/qemu/qemu/commit/8f1b6087983ed417ca142c0a7fd7080cc279e0f5
  Author: Bernhard Beschow <shentey@gmail.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M hw/vfio/pci-quirks.c

  Log Message:
  -----------
  hw/vfio/pci-quirks: Resolve redundant property getters

The QOM API already provides getters for uint64 and uint32 values, so reuse
them.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220301225220.239065-2-shentey@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 96c7fff703d56798bd5dcb1ef6d42ead144580a3
      
https://github.com/qemu/qemu/commit/96c7fff703d56798bd5dcb1ef6d42ead144580a3
  Author: Bernhard Beschow <shentey@gmail.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv/sifive_u: Resolve redundant property accessors

The QOM API already provides accessors for uint32 values, so reuse them.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220301225220.239065-3-shentey@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: bb06941f95edd8a231bee0ac52a8a1dbf6b08e6a
      
https://github.com/qemu/qemu/commit/bb06941f95edd8a231bee0ac52a8a1dbf6b08e6a
  Author: Weiwei Li <liweiwei@iscas.ac.cn>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize

 - setting ext_g will implicitly set ext_i

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220518012611.6772-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 075eeda93166f1914097ffb84b33df4ecc50d63c
      
https://github.com/qemu/qemu/commit/075eeda93166f1914097ffb84b33df4ecc50d63c
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Fix typo of mimpid cpu option

"mimpid" cpu option was mistyped to "mipid".

Fixes: 9951ba94 ("target/riscv: Support configuarable marchid, mvendorid, mipid 
CSR values")
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220523153147.15371-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: c1fbcecb3a97ecce2cde5052319df34ca6bcc988
      
https://github.com/qemu/qemu/commit/c1fbcecb3a97ecce2cde5052319df34ca6bcc988
  Author: Anup Patel <apatel@ventanamicro.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Fix csr number based privilege checking

When hypervisor and VS CSRs are accessed from VS-mode or VU-mode,
the riscv_csrrw_check() function should generate virtual instruction
trap instead illegal instruction trap.

Fixes: 0a42f4c44088 (" target/riscv: Fix CSR perm checking for HS mode")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-Id: <20220511144528.393530-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 24826da0eeacb27a5da6be764c8e853b2cede25b
      
https://github.com/qemu/qemu/commit/24826da0eeacb27a5da6be764c8e853b2cede25b
  Author: Anup Patel <apatel@ventanamicro.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode

Currently, QEMU does not set hstatus.GVA bit for traps taken from
HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
on QEMU. This was working previously.

This patch updates riscv_cpu_do_interrupt() to fix the above issue.

Fixes: 86d0c457396b ("target/riscv: Fixup setting GVA")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220511144528.393530-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 62cf02451edb1d23bc44a35aca56a8347dfebff7
      
https://github.com/qemu/qemu/commit/62cf02451edb1d23bc44a35aca56a8347dfebff7
  Author: Anup Patel <apatel@ventanamicro.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Set [m|s]tval for both illegal and virtual instruction traps

Currently, the [m|s]tval CSRs are set with trapping instruction encoding
only for illegal instruction traps taken at the time of instruction
decoding.

In RISC-V world, a valid instructions might also trap as illegal or
virtual instruction based to trapping bits in various CSRs (such as
mstatus.TVM or hstatus.VTVM).

We improve setting of [m|s]tval CSRs for all types of illegal and
virtual instruction traps.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220511144528.393530-4-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d644e5e44ff627d6b4da73a65795f60335ba4cb9
      
https://github.com/qemu/qemu/commit/d644e5e44ff627d6b4da73a65795f60335ba4cb9
  Author: Anup Patel <apatel@ventanamicro.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: virt: Fix interrupt parent for dynamic platform devices

When both APLIC and IMSIC are present in virt machine, the APLIC should
be used as parent interrupt controller for dynamic platform devices.

In case of  multiple sockets, we should prefer interrupt controller of
socket0 for dynamic platform devices.

Fixes: 3029fab64309 ("hw/riscv: virt: Add support for generating
platform FDT entries")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220511144528.393530-9-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 5160bacc0638088a7cb0180d2be3d8c2c8a21831
      
https://github.com/qemu/qemu/commit/5160bacc0638088a7cb0180d2be3d8c2c8a21831
  Author: Hongren (Zenithal) Zheng <i@zenithal.me>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: add zicsr/zifencei to isa_string

Zicsr/Zifencei is not in 'I' since ISA version 20190608,
thus to fully express the capability of the CPU,
they should be exposed in isa_string.

Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me>
Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <YoTqwpfrodveJ7CR@Sun>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d616889ece83d006ff630c72eb5bb38ad3b86645
      
https://github.com/qemu/qemu/commit/d616889ece83d006ff630c72eb5bb38ad3b86645
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M hw/core/uboot_image.h

  Log Message:
  -----------
  hw/core: Sync uboot_image.h from U-Boot v2022.01

Sync uboot_image.h from upstream U-Boot v2022.01 release [1].

[1] https://source.denx.de/u-boot/u-boot/-/blob/v2022.01/include/image.h

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220324134812.541274-1-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8fe63fe8e512d77583d6798acd2164f1fa1e40ab
      
https://github.com/qemu/qemu/commit/8fe63fe8e512d77583d6798acd2164f1fa1e40ab
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M hw/core/loader.c

  Log Message:
  -----------
  hw/core: loader: Set is_linux to true for VxWorks uImage

VxWorks 7 uses the same boot interface as the Linux kernel on Arm
(64-bit only), PowerPC and RISC-V architectures. Add logic to set
is_linux to true for VxWorks uImage for these architectures in
load_uboot_image().

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220324134812.541274-2-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0cac736e73723850a99e5142e35d14d8f8efb232
      
https://github.com/qemu/qemu/commit/0cac736e73723850a99e5142e35d14d8f8efb232
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M hw/core/loader.c
    M hw/core/uboot_image.h
    M hw/intc/riscv_aclint.c
    M hw/riscv/opentitan.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M hw/vfio/pci-quirks.c
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  Merge tag 'pull-riscv-to-apply-20220525' of github.com:alistair23/qemu into 
staging

Third RISC-V PR for QEMU 7.1

 * Fixes for accessing VS hypervisor CSRs
 * Improvements for RISC-V Vector extension
 * Fixes for accessing mtimecmp
 * Add new short-isa-string CPU option
 * Improvements to RISC-V machine error handling
 * Disable the "G" extension by default internally, no functional change
 * Enforce floating point extension requirements
 * Cleanup ISA extension checks
 * Resolve redundant property accessors
 * Fix typo of mimpid cpu option
 * Improvements for virtulisation
 * Add zicsr/zifencei to isa_string
 * Support for VxWorks uImage

# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmKNX4sACgkQIeENKd+X
# cFRikQgAqdRtGCj9XidnHV7QJkUkckmbqp8ZLwxo3PnoNkKirO8muXlo5jt9veyz
# LGn5nx6rmKX4fjs6CAQ+pNR2Pw2qFfrQiEpQXEhK6Zg6jh576qscqgwhX9JVSmrN
# is7nxpG1J/ZtMzO70DfgzmHO8Ykf+Ca6PNM/4kBftmqsPYjD5nUu/o9RJ98jgpem
# lI3U7sHx9xdoIBUVZO6CwRpmovTAvhz7usRbtKVTSXi7+IElFweyFacxT5X5xvgm
# Wj0GhQaeOYy7sww5XfXClQCeJXJS77ZQiPIaiT0W8vKs5dhY3Eux3zqqt9hWChny
# 0vFoYwHnYS5y8cy56IKeeg0/jnZq+A==
# =NiH/
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 24 May 2022 03:43:23 PM PDT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" 
[undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20220525' of github.com:alistair23/qemu: (23 commits)
  hw/core: loader: Set is_linux to true for VxWorks uImage
  hw/core: Sync uboot_image.h from U-Boot v2022.01
  target/riscv: add zicsr/zifencei to isa_string
  hw/riscv: virt: Fix interrupt parent for dynamic platform devices
  target/riscv: Set [m|s]tval for both illegal and virtual instruction traps
  target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode
  target/riscv: Fix csr number based privilege checking
  target/riscv: Fix typo of mimpid cpu option
  target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
  hw/riscv/sifive_u: Resolve redundant property accessors
  hw/vfio/pci-quirks: Resolve redundant property getters
  target/riscv: Move/refactor ISA extension checks
  target/riscv: FP extension requirements
  target/riscv: Change "G" expansion
  target/riscv: Disable "G" by default
  target/riscv: Fix coding style on "G" expansion
  hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)
  hw/riscv: Make CPU config error handling generous (virt/spike)
  target/riscv: Add short-isa-string option
  target/riscv: Move Zhinx* extensions on ISA string
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/d46e38dd1a17...0cac736e7372
reply via email to
[Prev in Thread] Current Thread [Next in Thread]