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[Qemu-commits] [qemu/qemu] 9f225e: target/arm: Postpone interpretation o
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 9f225e: target/arm: Postpone interpretation of stage 2 des... |
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Date: |
Thu, 19 May 2022 13:28:54 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 9f225e607f215003de1e4157255bb0199adff9aa
https://github.com/qemu/qemu/commit/9f225e607f215003de1e4157255bb0199adff9aa
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Postpone interpretation of stage 2 descriptor attribute bits
In the original Arm v8 two-stage translation, both stage 1 and stage
2 specify memory attributes (memory type, cacheability,
shareability); these are then combined to produce the overall memory
attributes for the whole stage 1+2 access. In QEMU we implement this
by having get_phys_addr() fill in an ARMCacheAttrs struct, and we
convert both the stage 1 and stage 2 attribute bit formats to the
same encoding (an 8-bit attribute value matching the MAIR_EL1 fields,
plus a 2-bit shareability value).
The new FEAT_S2FWB feature allows the guest to enable a different
interpretation of the attribute bits in the stage 2 descriptors.
These bits can now be used to control details of how the stage 1 and
2 attributes should be combined (for instance they can say "always
use the stage 1 attributes" or "ignore the stage 1 attributes and
always be Device memory"). This means we need to pass the raw bit
information for stage 2 down to the function which combines the stage
1 and stage 2 information.
Add a field to ARMCacheAttrs that indicates whether the attrs field
should be interpreted as MAIR format, or as the raw stage 2 attribute
bits from the descriptor, and store the appropriate values when
filling in cacheattrs.
We only need to interpret the attrs field in a few places:
* in do_ats_write(), where we know to expect a MAIR value
(there is no ATS instruction to do a stage-2-only walk)
* in S1_ptw_translate(), where we want to know whether the
combined S1 + S2 attributes indicate Device memory that
should provoke a fault
* in combine_cacheattrs(), which does the S1 + S2 combining
Update those places accordingly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220505183950.2781801-2-peter.maydell@linaro.org
Commit: 4a0b47c8150d3ac0a90f470191d64a3b199e6269
https://github.com/qemu/qemu/commit/4a0b47c8150d3ac0a90f470191d64a3b199e6269
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Factor out FWB=0 specific part of combine_cacheattrs()
Factor out the part of combine_cacheattrs() that is specific to
handling HCR_EL2.FWB == 0. This is the part where we combine the
memory type and cacheability attributes.
The "force Outer Shareable for Device or Normal Inner-NC Outer-NC"
logic remains in combine_cacheattrs() because it holds regardless
(this is the equivalent of the pseudocode EffectiveShareability()
function).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220505183950.2781801-3-peter.maydell@linaro.org
Commit: 8c7e17ef389699fd392e8613e144816b90af3a3a
https://github.com/qemu/qemu/commit/8c7e17ef389699fd392e8613e144816b90af3a3a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement FEAT_S2FWB
Implement the handling of FEAT_S2FWB; the meat of this is in the new
combined_attrs_fwb() function which combines S1 and S2 attributes
when HCR_EL2.FWB is set.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220505183950.2781801-4-peter.maydell@linaro.org
Commit: e04bf5a793ee5e7afdda8a1d1af08888fd67a989
https://github.com/qemu/qemu/commit/e04bf5a793ee5e7afdda8a1d1af08888fd67a989
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Enable FEAT_S2FWB for -cpu max
Enable the FEAT_S2FWB for -cpu max. Since FEAT_S2FWB requires that
CLIDR_EL1.{LoUU,LoUIS} are zero, we explicitly squash these (the
inherited CLIDR_EL1 value from the Cortex-A57 has them as 1).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220505183950.2781801-5-peter.maydell@linaro.org
Commit: 75662f36e3d11b986456210670719a7837111cd7
https://github.com/qemu/qemu/commit/75662f36e3d11b986456210670719a7837111cd7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpregs.h
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/op_helper.c
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Implement FEAT_IDST
The Armv8.4 feature FEAT_IDST specifies that exceptions generated by
read accesses to the feature ID space should report a syndrome code
of 0x18 (EC_SYSTEMREGISTERTRAP) rather than 0x00 (EC_UNCATEGORIZED).
The feature ID space is defined to be:
op0 == 3, op1 == {0,1,3}, CRn == 0, CRm == {0-7}, op2 == {0-7}
In our implementation we might return the EC_UNCATEGORIZED syndrome
value for a system register access in four cases:
* no reginfo struct in the hashtable
* cp_access_ok() fails (ie ri->access doesn't permit the access)
* ri->accessfn returns CP_ACCESS_TRAP_UNCATEGORIZED at runtime
* ri->type includes ARM_CP_RAISES_EXC, and the readfn raises
an UNDEF exception at runtime
We have very few regdefs that set ARM_CP_RAISES_EXC, and none of
them are in the feature ID space. (In the unlikely event that any
are added in future they would need to take care of setting the
correct syndrome themselves.) This patch deals with the other
three cases, and enables FEAT_IDST for AArch64 -cpu max.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220509155457.3560724-1-peter.maydell@linaro.org
Commit: 3d52472f81f0e0684fcab238ab816faeee6b8bcd
https://github.com/qemu/qemu/commit/3d52472f81f0e0684fcab238ab816faeee6b8bcd
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M target/arm/translate-a64.c
M target/arm/translate-a64.h
Log Message:
-----------
target/arm: Drop unsupported_encoding() macro
The unsupported_encoding() macro logs a LOG_UNIMP message and then
generates code to raise the usual exception for an unallocated
encoding. Back when we were still implementing the A64 decoder this
was helpful for flagging up when guest code was using something we
hadn't yet implemented. Now we completely cover the A64 instruction
set it is barely used. The only remaining uses are for five
instructions whose semantics are "UNDEF, unless being run under
external halting debug":
* HLT (when not being used for semihosting)
* DCPSR1, DCPS2, DCPS3
* DRPS
QEMU doesn't implement external halting debug, so for us the UNDEF is
the architecturally correct behaviour (because it's not possible to
execute these instructions with halting debug enabled). The
LOG_UNIMP doesn't serve a useful purpose; replace these uses of
unsupported_encoding() with unallocated_encoding(), and delete the
macro.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220509160443.3561604-1-peter.maydell@linaro.org
Commit: 272f75e89088c968c861fef516a4ebc70846dcd5
https://github.com/qemu/qemu/commit/272f75e89088c968c861fef516a4ebc70846dcd5
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parameters
We allow a GICv3 to be connected to any CPU, but we don't do anything
to handle the case where the CPU type doesn't in hardware have a
GICv3 CPU interface and so the various GIC configuration fields
(gic_num_lrs, vprebits, vpribits) are not specified.
The current behaviour is that we will add the EL1 CPU interface
registers, but will not put in the EL2 CPU interface registers, even
if the CPU has EL2, which will leave the GIC in a broken state and
probably result in the guest crashing as it tries to set it up. This
only affects the virt board when using the cortex-a15 or cortex-a7
CPU types (both 32-bit) with -machine gic-version=3 (or 'max')
and -machine virtualization=on.
Instead of failing to set up the EL2 registers, if the CPU doesn't
define the GIC configuration set it to a reasonable default, matching
the standard configuration for most Arm CPUs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220512151457.3899052-2-peter.maydell@linaro.org
Commit: 9c6f933e71ccfde036d7e19c1ddc2b1a82cc45c0
https://github.com/qemu/qemu/commit/9c6f933e71ccfde036d7e19c1ddc2b1a82cc45c0
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1
As noted in the comment, the PRIbits field in ICV_CTLR_EL1 is
supposed to match the ICH_VTR_EL2 PRIbits setting; that is, it is the
virtual priority bit setting, not the physical priority bit setting.
(For QEMU currently we always implement 8 bits of physical priority,
so the PRIbits field was previously 7, since it is defined to be
"priority bits - 1".)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220512151457.3899052-3-peter.maydell@linaro.org
Message-id: 20220506162129.2896966-2-peter.maydell@linaro.org
Commit: 9774c0f7ba6ae2980a291cb53a13661ddaa2f5de
https://github.com/qemu/qemu/commit/9774c0f7ba6ae2980a291cb53a13661ddaa2f5de
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M hw/intc/arm_gicv3_kvm.c
Log Message:
-----------
hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant
The GIC_MIN_BPR constant defines the minimum BPR value that the TCG
emulated GICv3 supports. We're currently using this also as the
value we reset the KVM GICv3 ICC_BPR registers to, but this is only
right by accident.
We want to make the emulated GICv3 use a configurable number of
priority bits, which means that GIC_MIN_BPR will no longer be a
constant. Replace the uses in the KVM reset code with literal 0,
plus a constant explaining why this is reasonable.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220512151457.3899052-4-peter.maydell@linaro.org
Message-id: 20220506162129.2896966-3-peter.maydell@linaro.org
Commit: 84597ff39484ec171567c7c80061100eb4a6c331
https://github.com/qemu/qemu/commit/84597ff39484ec171567c7c80061100eb4a6c331
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
M include/hw/intc/arm_gicv3_common.h
Log Message:
-----------
hw/intc/arm_gicv3: Support configurable number of physical priority bits
The GICv3 code has always supported a configurable number of virtual
priority and preemption bits, but our implementation currently
hardcodes the number of physical priority bits at 8. This is not
what most hardware implementations provide; for instance the
Cortex-A53 provides only 5 bits of physical priority.
Make the number of physical priority/preemption bits driven by fields
in the GICv3CPUState, the way that we already do for virtual
priority/preemption bits. We set cs->pribits to 8, so there is no
behavioural change in this commit. A following commit will add the
machinery for CPUs to set this to the correct value for their
implementation.
Note that changing the number of priority bits would be a migration
compatibility break, because the semantics of the icc_apr[][] array
changes.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220512151457.3899052-5-peter.maydell@linaro.org
Message-id: 20220506162129.2896966-4-peter.maydell@linaro.org
Commit: 39f29e599355f9512482b67624e7a6c9000c5ddd
https://github.com/qemu/qemu/commit/39f29e599355f9512482b67624e7a6c9000c5ddd
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M hw/core/machine.c
M hw/intc/arm_gicv3_common.c
M hw/intc/arm_gicv3_cpuif.c
M include/hw/intc/arm_gicv3_common.h
M target/arm/cpu.h
M target/arm/cpu64.c
Log Message:
-----------
hw/intc/arm_gicv3: Use correct number of priority bits for the CPU
Make the GICv3 set its number of bits of physical priority from the
implementation-specific value provided in the CPU state struct, in
the same way we already do for virtual priority bits. Because this
would be a migration compatibility break, we provide a property
force-8-bit-prio which is enabled for 7.0 and earlier versioned board
models to retain the legacy "always use 8 bits" behaviour.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220512151457.3899052-6-peter.maydell@linaro.org
Message-id: 20220506162129.2896966-5-peter.maydell@linaro.org
Commit: 5d55f827677a521feaab6dc651168e6136954e88
https://github.com/qemu/qemu/commit/5d55f827677a521feaab6dc651168e6136954e88
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3: Provide ich_num_aprs()
We previously open-coded the expression for the number of virtual APR
registers and the assertion that it was not going to cause us to
overflow the cs->ich_apr[] array. Factor this out into a new
ich_num_aprs() function, for consistency with the icc_num_aprs()
function we just added for the physical APR handling.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220512151457.3899052-7-peter.maydell@linaro.org
Message-id: 20220506162129.2896966-6-peter.maydell@linaro.org
Commit: e1be11a5a440bfa552e0a8bb109d72294054e3f0
https://github.com/qemu/qemu/commit/e1be11a5a440bfa552e0a8bb109d72294054e3f0
Author: Chris Howard <cvz185@web.de>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
Fix aarch64 debug register names.
Give all the debug registers their correct names including the
index, rather than having multiple registers all with the
same name string, which is confusing when viewed over the
gdbstub interface.
Signed-off-by: CHRIS HOWARD <cvz185@web.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 4127D8CA-D54A-47C7-A039-0DB7361E30C0@web.de
[PMM: expanded commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6e76d35f2375c3ef58aaaccbe5cee54b20a1f74a
https://github.com/qemu/qemu/commit/6e76d35f2375c3ef58aaaccbe5cee54b20a1f74a
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M hw/adc/zynq-xadc.c
M include/hw/adc/zynq-xadc.h
Log Message:
-----------
hw/adc/zynq-xadc: Use qemu_irq typedef
Except hw/core/irq.c which implements the forward-declared opaque
qemu_irq structure, hw/adc/zynq-xadc.{c,h} are the only files not
using the typedef. Fix this single exception.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Message-id: 20220509202035.50335-1-philippe.mathieu.daude@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1a13efcc56f0a50149da25ecca1f81f346496f86
https://github.com/qemu/qemu/commit/1a13efcc56f0a50149da25ecca1f81f346496f86
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm/helper.c: Delete stray obsolete comment
In commit 88ce6c6ee85d we switched from directly fishing the number
of breakpoints and watchpoints out of the ID register fields to
abstracting out functions to do this job, but we forgot to delete the
now-obsolete comment in define_debug_regs() about the relation
between the ID field value and the actual number of breakpoints and
watchpoints. Delete the obsolete comment.
Reported-by: CHRIS HOWARD <cvz185@web.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220513131801.4082712-1-peter.maydell@linaro.org
Commit: 24526bb92f69a323a9339dd94e823ad1d680f483
https://github.com/qemu/qemu/commit/24526bb92f69a323a9339dd94e823ad1d680f483
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/kvm64.c
Log Message:
-----------
target/arm: Make number of counters in PMCR follow the CPU
Currently we give all the v7-and-up CPUs a PMU with 4 counters. This
means that we don't provide the 6 counters that are required by the
Arm BSA (Base System Architecture) specification if the CPU supports
the Virtualization extensions.
Instead of having a single PMCR_NUM_COUNTERS, make each CPU type
specify the PMCR reset value (obtained from the appropriate TRM), and
use the 'N' field of that value to define the number of counters
provided.
This means that we now supply 6 counters instead of 4 for:
Cortex-A9, Cortex-A15, Cortex-A53, Cortex-A57, Cortex-A72,
Cortex-A76, Neoverse-N1, '-cpu max'
This CPU goes from 4 to 8 counters:
A64FX
These CPUs remain with 4 counters:
Cortex-A7, Cortex-A8
This CPU goes down from 4 to 3 counters:
Cortex-R5
Note that because we now use the PMCR reset value of the specific
implementation, we no longer set the LC bit out of reset. This has
an UNKNOWN value out of reset for all cores with any AArch32 support,
so guest software should be setting it anyway if it wants it.
This change was originally landed in commit f7fb73b8cdd3f7 (during
the 6.0 release cycle) but was then reverted by commit
21c2dd77a6aa517 before that release because it did not work with KVM.
This version fixes that by creating the scratch vCPU in
kvm_arm_get_host_cpu_features() with the KVM_ARM_VCPU_PMU_V3 feature
if KVM supports it, and then only asking KVM for the PMCR_EL0 value
if the vCPU has a PMU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[PMM: Added the correct value for a64fx]
Message-id: 20220513122852.4063586-1-peter.maydell@linaro.org
Commit: e8ca920f3d1cedf7f2ebb41d13cd4d5946d3d882
https://github.com/qemu/qemu/commit/e8ca920f3d1cedf7f2ebb41d13cd4d5946d3d882
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Fix incorrect non-secure flash dtb node name
In the virt board with secure=on we put two nodes in the dtb
for flash devices: one for the secure-only flash, and one
for the non-secure flash. We get the reg properties for these
correct, but in the DT node name, which by convention includes
the base address of devices, we used the wrong address. Fix it.
Spotted by dtc, which will complain
Warning (unique_unit_address): /flash@0: duplicate unit-address (also used in
node /secflash@0)
if you dump the dtb from QEMU with -machine dumpdtb=file.dtb
and then decompile it with dtc.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220513131316.4081539-2-peter.maydell@linaro.org
Commit: afdcbddcc92ef75ed1905e6ae7aa00db06e86dfc
https://github.com/qemu/qemu/commit/afdcbddcc92ef75ed1905e6ae7aa00db06e86dfc
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Drop #size-cells and #address-cells from gpio-keys dtb node
The virt board generates a gpio-keys node in the dtb, but it
incorrectly gives this node #size-cells and #address-cells
properties. If you dump the dtb with 'machine dumpdtb=file.dtb'
and run it through dtc, dtc will warn about this:
Warning (avoid_unnecessary_addr_size): /gpio-keys: unnecessary
#address-cells/#size-cells without "ranges" or child "reg" property
Remove the bogus properties.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220513131316.4081539-3-peter.maydell@linaro.org
Commit: 9598c1bb39b2d4f0d3a55072cc70251c452132cd
https://github.com/qemu/qemu/commit/9598c1bb39b2d4f0d3a55072cc70251c452132cd
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M hw/arm/musicpal.c
M hw/dma/xilinx_axidma.c
M hw/dma/xlnx_csu_dma.c
M hw/m68k/mcf5206.c
M hw/m68k/mcf5208.c
M hw/net/can/xlnx-zynqmp-can.c
M hw/net/fsl_etsec/etsec.c
M hw/net/lan9118.c
M hw/rtc/exynos4210_rtc.c
M hw/timer/allwinner-a10-pit.c
M hw/timer/altera_timer.c
M hw/timer/arm_timer.c
M hw/timer/digic-timer.c
M hw/timer/etraxfs_timer.c
M hw/timer/exynos4210_mct.c
M hw/timer/exynos4210_pwm.c
M hw/timer/grlib_gptimer.c
M hw/timer/imx_epit.c
M hw/timer/imx_gpt.c
M hw/timer/mss-timer.c
M hw/timer/sh_timer.c
M hw/timer/slavio_timer.c
M hw/timer/xilinx_timer.c
M include/hw/ptimer.h
M tests/unit/ptimer-test.c
Log Message:
-----------
ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY
The traditional ptimer behaviour includes a collection of weird edge
case behaviours. In 2016 we improved the ptimer implementation to
fix these and generally make the behaviour more flexible, with
ptimers opting in to the new behaviour by passing an appropriate set
of policy flags to ptimer_init(). For backwards-compatibility, we
defined PTIMER_POLICY_DEFAULT (which sets no flags) to give the old
weird behaviour.
This turns out to be a poor choice of name, because people writing
new devices which use ptimers are misled into thinking that the
default is probably a sensible choice of flags, when in fact it is
almost always not what you want. Rename PTIMER_POLICY_DEFAULT to
PTIMER_POLICY_LEGACY and beef up the comment to more clearly say that
new devices should not be using it.
The code-change part of this commit was produced by
sed -i -e 's/PTIMER_POLICY_DEFAULT/PTIMER_POLICY_LEGACY/g' $(git grep -l
PTIMER_POLICY_DEFAULT)
with the exception of a test name string change in
tests/unit/ptimer-test.c which was added manually.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220516103058.162280-1-peter.maydell@linaro.org
Commit: 07b034ea828eb089de1a88e0043a8f3065f2d205
https://github.com/qemu/qemu/commit/07b034ea828eb089de1a88e0043a8f3065f2d205
Author: Florian Lugou <florian.lugou@provenrun.com>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Fix PAuth keys access checks for disabled SEL2
As per the description of the HCR_EL2.APK field in the ARMv8 ARM,
Pointer Authentication keys accesses should only be trapped to Secure
EL2 if it is enabled.
Signed-off-by: Florian Lugou <florian.lugou@provenrun.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220517145242.1215271-1-florian.lugou@provenrun.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5814d587fe861fe9cab651638959f6db843df54e
https://github.com/qemu/qemu/commit/5814d587fe861fe9cab651638959f6db843df54e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
Log Message:
-----------
target/arm: Enable FEAT_HCX for -cpu max
This feature adds a new register, HCRX_EL2, which controls
many of the newer AArch64 features. So far the register is
effectively RES0, because none of the new features are done.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220517054850.177016-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fab8ad39fb75a0d9f097db67b2a334444754e88e
https://github.com/qemu/qemu/commit/fab8ad39fb75a0d9f097db67b2a334444754e88e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M hw/arm/boot.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Use FIELD definitions for CPACR, CPTR_ELx
We had a few CPTR_* bits defined, but missed quite a few.
Complete all of the fields up to ARMv9.2.
Use FIELD_EX64 instead of manual extract32.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220517054850.177016-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3a650ac995ca36fb9974b82ba50aac8d1fd18b6a
https://github.com/qemu/qemu/commit/3a650ac995ca36fb9974b82ba50aac8d1fd18b6a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-19 (Thu, 19 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M hw/adc/zynq-xadc.c
M hw/arm/boot.c
M hw/arm/musicpal.c
M hw/arm/virt.c
M hw/core/machine.c
M hw/dma/xilinx_axidma.c
M hw/dma/xlnx_csu_dma.c
M hw/intc/arm_gicv3_common.c
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/arm_gicv3_kvm.c
M hw/m68k/mcf5206.c
M hw/m68k/mcf5208.c
M hw/net/can/xlnx-zynqmp-can.c
M hw/net/fsl_etsec/etsec.c
M hw/net/lan9118.c
M hw/rtc/exynos4210_rtc.c
M hw/timer/allwinner-a10-pit.c
M hw/timer/altera_timer.c
M hw/timer/arm_timer.c
M hw/timer/digic-timer.c
M hw/timer/etraxfs_timer.c
M hw/timer/exynos4210_mct.c
M hw/timer/exynos4210_pwm.c
M hw/timer/grlib_gptimer.c
M hw/timer/imx_epit.c
M hw/timer/imx_gpt.c
M hw/timer/mss-timer.c
M hw/timer/sh_timer.c
M hw/timer/slavio_timer.c
M hw/timer/xilinx_timer.c
M include/hw/adc/zynq-xadc.h
M include/hw/intc/arm_gicv3_common.h
M include/hw/ptimer.h
M target/arm/cpregs.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/kvm64.c
M target/arm/op_helper.c
M target/arm/translate-a64.c
M target/arm/translate-a64.h
M tests/unit/ptimer-test.c
Log Message:
-----------
Merge tag 'pull-target-arm-20220519' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Implement FEAT_S2FWB
* Implement FEAT_IDST
* Drop unsupported_encoding() macro
* hw/intc/arm_gicv3: Use correct number of priority bits for the CPU
* Fix aarch64 debug register names
* hw/adc/zynq-xadc: Use qemu_irq typedef
* target/arm/helper.c: Delete stray obsolete comment
* Make number of counters in PMCR follow the CPU
* hw/arm/virt: Fix dtb nits
* ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY
* target/arm: Fix PAuth keys access checks for disabled SEL2
* Enable FEAT_HCX for -cpu max
* Use FIELD definitions for CPACR, CPTR_ELx
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# gpg: Signature made Thu 19 May 2022 10:35:53 AM PDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
* tag 'pull-target-arm-20220519' of
https://git.linaro.org/people/pmaydell/qemu-arm: (22 commits)
target/arm: Use FIELD definitions for CPACR, CPTR_ELx
target/arm: Enable FEAT_HCX for -cpu max
target/arm: Fix PAuth keys access checks for disabled SEL2
ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY
hw/arm/virt: Drop #size-cells and #address-cells from gpio-keys dtb node
hw/arm/virt: Fix incorrect non-secure flash dtb node name
target/arm: Make number of counters in PMCR follow the CPU
target/arm/helper.c: Delete stray obsolete comment
hw/adc/zynq-xadc: Use qemu_irq typedef
Fix aarch64 debug register names.
hw/intc/arm_gicv3: Provide ich_num_aprs()
hw/intc/arm_gicv3: Use correct number of priority bits for the CPU
hw/intc/arm_gicv3: Support configurable number of physical priority bits
hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant
hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1
hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parameters
target/arm: Drop unsupported_encoding() macro
target/arm: Implement FEAT_IDST
target/arm: Enable FEAT_S2FWB for -cpu max
target/arm: Implement FEAT_S2FWB
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/78ac2eebbab9...3a650ac995ca