[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 06134e: virtio: fix feature negotiation for A
|
From: |
Richard Henderson |
|
Subject: |
[Qemu-commits] [qemu/qemu] 06134e: virtio: fix feature negotiation for ACCESS_PLATFORM |
|
Date: |
Mon, 16 May 2022 20:00:56 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 06134e2bc35dc21543d4cbcf31f858c03d383442
https://github.com/qemu/qemu/commit/06134e2bc35dc21543d4cbcf31f858c03d383442
Author: Halil Pasic <pasic@linux.ibm.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/virtio/virtio-bus.c
Log Message:
-----------
virtio: fix feature negotiation for ACCESS_PLATFORM
Unlike most virtio features ACCESS_PLATFORM is considered mandatory by
QEMU, i.e. the driver must accept it if offered by the device. The
virtio specification says that the driver SHOULD accept the
ACCESS_PLATFORM feature if offered, and that the device MAY fail to
operate if ACCESS_PLATFORM was offered but not negotiated.
While a SHOULD ain't exactly a MUST, we are certainly allowed to fail
the device when the driver fences ACCESS_PLATFORM. With commit
2943b53f68 ("virtio: force VIRTIO_F_IOMMU_PLATFORM") we already made the
decision to do so whenever the get_dma_as() callback is implemented (by
the bus), which in practice means for the entirety of virtio-pci.
That means, if the device needs to translate I/O addresses, then
ACCESS_PLATFORM is mandatory. The aforementioned commit tells us in the
commit message that this is for security reasons. More precisely if we
were to allow a less then trusted driver (e.g. an user-space driver, or
a nested guest) to make the device bypass the IOMMU by not negotiating
ACCESS_PLATFORM, then the guest kernel would have no ability to
control/police (by programming the IOMMU) what pieces of guest memory
the driver may manipulate using the device. Which would break security
assumptions within the guest.
If ACCESS_PLATFORM is offered not because we want the device to utilize
an IOMMU and do address translation, but because the device does not
have access to the entire guest RAM, and needs the driver to grant
access to the bits it needs access to (e.g. confidential guest support),
we still require the guest to have the corresponding logic and to accept
ACCESS_PLATFORM. If the driver does not accept ACCESS_PLATFORM, then
things are bound to go wrong, and we may see failures much less graceful
than failing the device because the driver didn't negotiate
ACCESS_PLATFORM.
So let us make ACCESS_PLATFORM mandatory for the driver regardless
of whether the get_dma_as() callback is implemented or not.
Signed-off-by: Halil Pasic <pasic@linux.ibm.com>
Fixes: 2943b53f68 ("virtio: force VIRTIO_F_IOMMU_PLATFORM")
Message-Id: <20220307112939.2780117-1-pasic@linux.ibm.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Commit: 250227f4fa4efd6032da6c39d8fb2e6c9192d6ce
https://github.com/qemu/qemu/commit/250227f4fa4efd6032da6c39d8fb2e6c9192d6ce
Author: Jason Wang <jasowang@redhat.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel-iommu: correct the value used for error_setg_errno()
error_setg_errno() expects a normal errno value, not a negated
one, so we should use ENOTSUP instead of -ENOSUP.
Fixes: Coverity CID 1487174
Fixes: ("intel_iommu: support snoop control")
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220401022824.9337-1-jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Xu <peterx@redhat.com>
Commit: cf04aba2a9d276336c45d2434f94458838a01034
https://github.com/qemu/qemu/commit/cf04aba2a9d276336c45d2434f94458838a01034
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/pci/pci.c
M include/hw/pci/pci.h
Log Message:
-----------
hw/pci/cxl: Add a CXL component type (interface)
A CXL component is a hardware entity that implements CXL component
registers from the CXL 2.0 spec (8.2.3). Currently these represent 3
general types.
1. Host Bridge
2. Ports (root, upstream, downstream)
3. Devices (memory, other)
A CXL component can be conceptually thought of as a PCIe device with
extra functionality when enumerated and enabled. For this reason, CXL
does here, and will continue to add on to existing PCI code paths.
Host bridges will typically need to be handled specially and so they can
implement this newly introduced interface or not. All other components
should implement this interface. Implementing this interface allows the
core PCI code to treat these devices as special where appropriate.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Adam Manzanares <a.manzanares@samsung.com>
Message-Id: <20220429144110.25167-2-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 9e58f52d3f809712762bef735a02290fd4436b0c
https://github.com/qemu/qemu/commit/9e58f52d3f809712762bef735a02290fd4436b0c
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/Kconfig
A hw/cxl/Kconfig
A hw/cxl/cxl-component-utils.c
A hw/cxl/meson.build
M hw/meson.build
A include/hw/cxl/cxl.h
A include/hw/cxl/cxl_component.h
A include/hw/cxl/cxl_pci.h
Log Message:
-----------
hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)
A CXL 2.0 component is any entity in the CXL topology. All components
have a analogous function in PCIe. Except for the CXL host bridge, all
have a PCIe config space that is accessible via the common PCIe
mechanisms. CXL components are enumerated via DVSEC fields in the
extended PCIe header space. CXL components will minimally implement some
subset of CXL.mem and CXL.cache registers defined in 8.2.5 of the CXL
2.0 specification. Two headers and a utility library are introduced to
support the minimum functionality needed to enumerate components.
The cxl_pci header manages bits associated with PCI, specifically the
DVSEC and related fields. The cxl_component.h variant has data
structures and APIs that are useful for drivers implementing any of the
CXL 2.0 components. The library takes care of making use of the DVSEC
bits and the CXL.[mem|cache] registers. Per spec, the registers are
little endian.
None of the mechanisms required to enumerate a CXL capable hostbridge
are introduced at this point.
Note that the CXL.mem and CXL.cache registers used are always 4B wide.
It's possible in the future that this constraint will not hold.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Adam Manzanares <a.manzanares@samsung.com>
Message-Id: <20220429144110.25167-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 502730ee3cc3acbf421f07c26a15652f4929e309
https://github.com/qemu/qemu/commit/502730ee3cc3acbf421f07c26a15652f4929e309
Author: Jonathan Cameron <jonathan.cameron@huawei.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add entry for Compute Express Link Emulation
The CXL emulation will be jointly maintained by Ben Widawsky
and Jonathan Cameron. Broken out as a separate patch
to improve visibility.
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-4-Jonathan.Cameron@huawei.com>
Commit: cd90126b4ced427697d79eb5002544a7621ec647
https://github.com/qemu/qemu/commit/cd90126b4ced427697d79eb5002544a7621ec647
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M include/hw/cxl/cxl.h
A include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/device: Introduce a CXL device (8.2.8)
A CXL device is a type of CXL component. Conceptually, a CXL device
would be a leaf node in a CXL topology. From an emulation perspective,
CXL devices are the most complex and so the actual implementation is
reserved for discrete commits.
This new device type is specifically catered towards the eventual
implementation of a Type3 CXL.mem device, 8.2.8.5 in the CXL 2.0
specification.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Adam Manzanares <a.manzanares@samsung.com>
Message-Id: <20220429144110.25167-5-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 6364adacdfa6a24e3f5b08f6b5ffa789a5d828a7
https://github.com/qemu/qemu/commit/6364adacdfa6a24e3f5b08f6b5ffa789a5d828a7
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
A hw/cxl/cxl-device-utils.c
M hw/cxl/meson.build
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/device: Implement the CAP array (8.2.8.1-2)
This implements all device MMIO up to the first capability. That
includes the CXL Device Capabilities Array Register, as well as all of
the CXL Device Capability Header Registers. The latter are filled in as
they are implemented in the following patches.
Endianness and alignment are managed by softmmu memory core.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 464e14ac438e21c532889d78caf54a1dc837012a
https://github.com/qemu/qemu/commit/464e14ac438e21c532889d78caf54a1dc837012a
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/cxl/cxl-device-utils.c
A hw/cxl/cxl-mailbox-utils.c
M hw/cxl/meson.build
M include/hw/cxl/cxl.h
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/device: Implement basic mailbox (8.2.8.4)
This is the beginning of implementing mailbox support for CXL 2.0
devices. The implementation recognizes when the doorbell is rung,
handles the command/payload, clears the doorbell while returning error
codes and data.
Generally the mailbox mechanism is designed to permit communication
between the host OS and the firmware running on the device. For our
purposes, we emulate both the firmware, implemented primarily in
cxl-mailbox-utils.c, and the hardware.
No commands are implemented yet.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-7-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: ce3b4e5c152fe1c05aaf03b5bbe7579338446318
https://github.com/qemu/qemu/commit/ce3b4e5c152fe1c05aaf03b5bbe7579338446318
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/cxl/cxl-device-utils.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/device: Add memory device utilities
Memory devices implement extra capabilities on top of CXL devices. This
adds support for that.
A large part of memory devices is the mailbox/command interface. All of
the mailbox handling is done in the mailbox-utils library. Longer term,
new CXL devices that are being emulated may want to handle commands
differently, and therefore would need a mechanism to opt in/out of the
specific generic handlers. As such, this is considered sufficient for
now, but may need more depth in the future.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-8-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 57c02b355fd38c279bf54b5f492e6fdc7114a188
https://github.com/qemu/qemu/commit/57c02b355fd38c279bf54b5f492e6fdc7114a188
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1)
Using the previously implemented stubbed helpers, it is now possible to
easily add the missing, required commands to the implementation.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-9-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 557a79c83e73e5c524a1d44626b509644efa0103
https://github.com/qemu/qemu/commit/557a79c83e73e5c524a1d44626b509644efa0103
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/device: Timestamp implementation (8.2.9.3)
Errata F4 to CXL 2.0 clarified the meaning of the timer as the
sum of the value set with the timestamp set command and the number
of nano seconds since it was last set.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-10-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 056172691bbfc2cd7c7e8ac6a14f78b45ddadba1
https://github.com/qemu/qemu/commit/056172691bbfc2cd7c7e8ac6a14f78b45ddadba1
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl/device: Add log commands (8.2.9.4) + CEL
CXL specification provides for the ability to obtain logs from the
device. Logs are either spec defined, like the "Command Effects Log"
(CEL), or vendor specific. UUIDs are defined for all log types.
The CEL is a mechanism to provide information to the host about which
commands are supported. It is useful both to determine which spec'd
optional commands are supported, as well as provide a list of vendor
specified commands that might be used. The CEL is already created as
part of mailbox initialization, but here it is now exported to hosts
that use these log commands.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-11-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 25a2e524e34e9a7cdf709a380b9deaada9dc4995
https://github.com/qemu/qemu/commit/25a2e524e34e9a7cdf709a380b9deaada9dc4995
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/pci-bridge/pci_expander_bridge.c
Log Message:
-----------
hw/pxb: Use a type for realizing expanders
This opens up the possibility for more types of expanders (other than
PCI and PCIe). We'll need this to create a CXL expander.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-12-Jonathan.Cameron@huawei.com>
Commit: 9dccb1216bf9d120579612979f4d58fd97bf0150
https://github.com/qemu/qemu/commit/9dccb1216bf9d120579612979f4d58fd97bf0150
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/pci-bridge/pci_expander_bridge.c
M include/hw/pci/pci_bus.h
Log Message:
-----------
hw/pci/cxl: Create a CXL bus type
The easiest way to differentiate a CXL bus, and a PCIE bus is using a
flag. A CXL bus, in hardware, is backward compatible with PCIE, and
therefore the code tries pretty hard to keep them in sync as much as
possible.
The other way to implement this would be to try to cast the bus to the
correct type. This is less code and useful for debugging via simply
looking at the flags.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-13-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: abb3009baf90e5984ff1c230af0bc92a45e64864
https://github.com/qemu/qemu/commit/abb3009baf90e5984ff1c230af0bc92a45e64864
Author: Jonathan Cameron <jonathan.cameron@huawei.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/core/machine.c
M hw/i386/pc.c
M include/hw/boards.h
M include/hw/cxl/cxl.h
Log Message:
-----------
cxl: Machine level control on whether CXL support is enabled
There are going to be some potential overheads to CXL enablement,
for example the host bridge region reserved in memory maps.
Add a machine level control so that CXL is disabled by default.
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-14-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 4f8db8711cbd27c9acf17e685987e9e74815e087
https://github.com/qemu/qemu/commit/4f8db8711cbd27c9acf17e685987e9e74815e087
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/pci-bridge/pci_expander_bridge.c
M hw/pci/pci.c
M include/hw/pci/pci.h
M scripts/device-crash-test
Log Message:
-----------
hw/pxb: Allow creation of a CXL PXB (host bridge)
This works like adding a typical pxb device, except the name is
'pxb-cxl' instead of 'pxb-pcie'. An example command line would be as
follows:
-device pxb-cxl,id=cxl.0,bus="pcie.0",bus_nr=1
A CXL PXB is backward compatible with PCIe. What this means in practice
is that an operating system that is unaware of CXL should still be able
to enumerate this topology as if it were PCIe.
One can create multiple CXL PXB host bridges, but a host bridge can only
be connected to the main root bus. Host bridges cannot appear elsewhere
in the topology.
Note that as of this patch, the ACPI tables needed for the host bridge
(specifically, an ACPI object in _SB named ACPI0016 and the CEDT) aren't
created. So while this patch internally creates it, it cannot be
properly used by an operating system or other system software.
Also necessary is to add an exception to scripts/device-crash-test
similar to that for exiting pxb as both must created on a PCIexpress
host bus.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan.Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-15-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 33c47ab967558dfb02b3439b37e7dcfcdced0157
https://github.com/qemu/qemu/commit/33c47ab967558dfb02b3439b37e7dcfcdced0157
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
A tests/qtest/cxl-test.c
M tests/qtest/meson.build
Log Message:
-----------
qtest/cxl: Introduce initial test for pxb-cxl only.
Initial test with just pxb-cxl. Other tests will be added
alongside functionality.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-16-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: d86d30192b7bc5a10fa6c82c073f55aea25f9291
https://github.com/qemu/qemu/commit/d86d30192b7bc5a10fa6c82c073f55aea25f9291
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/pci-bridge/Kconfig
A hw/pci-bridge/cxl_root_port.c
M hw/pci-bridge/meson.build
M hw/pci-bridge/pcie_root_port.c
M hw/pci/pci.c
Log Message:
-----------
hw/cxl/rp: Add a root port
This adds just enough of a root port implementation to be able to
enumerate root ports (creating the required DVSEC entries). What's not
here yet is the MMIO nor the ability to write some of the DVSEC entries.
This can be added with the qemu commandline by adding a rootport to a
specific CXL host bridge. For example:
-device cxl-rp,id=rp0,bus="cxl.0",addr=0.0,chassis=4
Like the host bridge patch, the ACPI tables aren't generated at this
point and so system software cannot use it.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-17-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: e1706ea83da0120be6708b66394ec3a9f3ec48ca
https://github.com/qemu/qemu/commit/e1706ea83da0120be6708b66394ec3a9f3ec48ca
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/cxl/cxl-component-utils.c
M hw/cxl/cxl-mailbox-utils.c
M hw/mem/Kconfig
A hw/mem/cxl_type3.c
M hw/mem/meson.build
M include/hw/cxl/cxl_device.h
M include/hw/cxl/cxl_pci.h
M include/hw/pci/pci_ids.h
Log Message:
-----------
hw/cxl/device: Add a memory device (8.2.8.5)
A CXL memory device (AKA Type 3) is a CXL component that contains some
combination of volatile and persistent memory. It also implements the
previously defined mailbox interface as well as the memory device
firmware interface.
Although the memory device is configured like a normal PCIe device, the
memory traffic is on an entirely separate bus conceptually (using the
same physical wires as PCIe, but different protocol).
Once the CXL topology is fully configure and address decoders committed,
the guest physical address for the memory device is part of a larger
window which is owned by the platform. The creation of these windows
is later in this series.
The following example will create a 256M device in a 512M window:
-object "memory-backend-file,id=cxl-mem1,share,mem-path=cxl-type3,size=512M"
-device "cxl-type3,bus=rp0,memdev=cxl-mem1,id=cxl-pmem0"
Note: Dropped PCDIMM info interfaces for now. They can be added if
appropriate at a later date.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-18-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 947515fc4274bd46cc93f82c3121df6ee4968786
https://github.com/qemu/qemu/commit/947515fc4274bd46cc93f82c3121df6ee4968786
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/mem/cxl_type3.c
Log Message:
-----------
hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12)
A device's volatile and persistent memory are known Host Defined Memory
(HDM) regions. The mechanism by which the device is programmed to claim
the addresses associated with those regions is through dedicated logic
known as the HDM decoder. In order to allow the OS to properly program
the HDMs, the HDM decoders must be modeled.
There are two ways the HDM decoders can be implemented, the legacy
mechanism is through the PCIe DVSEC programming from CXL 1.1 (8.1.3.8),
and MMIO is found in 8.2.5.12 of the spec. For now, 8.1.3.8 is not
implemented.
Much of CXL device logic is implemented in cxl-utils. The HDM decoder
however is implemented directly by the device implementation.
Whilst the implementation currently does no validity checks on the
encoder set up, future work will add sanity checking specific to
the type of cxl component.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Co-developed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-19-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 092c6b11f2ab835f50b3167d0559c197a21a051e
https://github.com/qemu/qemu/commit/092c6b11f2ab835f50b3167d0559c197a21a051e
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
Log Message:
-----------
hw/cxl/device: Add some trivial commands
GET_FW_INFO and GET_PARTITION_INFO, for this emulation, is equivalent to
info already returned in the IDENTIFY command. To have a more robust
implementation, add those.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-20-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 639daf8e93bcf266d0518eecbcfe12d26644a0a9
https://github.com/qemu/qemu/commit/639daf8e93bcf266d0518eecbcfe12d26644a0a9
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
M hw/mem/cxl_type3.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/device: Plumb real Label Storage Area (LSA) sizing
This should introduce no change. Subsequent work will make use of this
new class member.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-21-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 3ebe676a3463b886cfc112b3eff58e4991051b0d
https://github.com/qemu/qemu/commit/3ebe676a3463b886cfc112b3eff58e4991051b0d
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/cxl/cxl-mailbox-utils.c
M hw/mem/cxl_type3.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
hw/cxl/device: Implement get/set Label Storage Area (LSA)
Implement get and set handlers for the Label Storage Area
used to hold data describing persistent memory configuration
so that it can be ensured it is seen in the same configuration
after reboot.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-22-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 92fd46b68a0ca2f37d46fd69616034b2703966b2
https://github.com/qemu/qemu/commit/92fd46b68a0ca2f37d46fd69616034b2703966b2
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M tests/qtest/cxl-test.c
Log Message:
-----------
qtests/cxl: Add initial root port and CXL type3 tests
At this stage we can boot configurations with host bridges,
root ports and type 3 memory devices, so add appropriate
tests.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-23-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 6e4e3ae936e6bc1501fc0d67444738cec7a1e78a
https://github.com/qemu/qemu/commit/6e4e3ae936e6bc1501fc0d67444738cec7a1e78a
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/i386/acpi-build.c
M hw/i386/pc.c
M hw/pci-bridge/pci_expander_bridge.c
M include/hw/cxl/cxl.h
Log Message:
-----------
hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142)
CXL host bridges themselves may have MMIO. Since host bridges don't have
a BAR they are treated as special for MMIO. This patch includes
i386/pc support.
Also hook up the device reset now that we have have the MMIO
space in which the results are visible.
Note that we duplicate the PCI express case for the aml_build but
the implementations will diverge when the CXL specific _OSC is
introduced.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Co-developed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-24-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 2a3282c68ee21cd04ee9d9ef62549f1771929828
https://github.com/qemu/qemu/commit/2a3282c68ee21cd04ee9d9ef62549f1771929828
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/acpi/Kconfig
A hw/acpi/cxl-stub.c
A hw/acpi/cxl.c
M hw/acpi/meson.build
M hw/i386/acpi-build.c
A include/hw/acpi/cxl.h
Log Message:
-----------
acpi/cxl: Add _OSC implementation (9.14.2)
CXL 2.0 specification adds 2 new dwords to the existing _OSC definition
from PCIe. The new dwords are accessed with a new uuid. This
implementation supports what is in the specification.
iasl -d decodes the result of this patch as:
Name (SUPP, Zero)
Name (CTRL, Zero)
Name (SUPC, Zero)
Name (CTRC, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If (((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host
Bridge Device */) || (Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc")
/* Unknown UUID */)))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
Local0 = CDW3 /* \_SB_.PC0C._OSC.CDW3 */
Local0 &= 0x1F
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != Local0))
{
CDW1 |= 0x10
}
SUPP = CDW2 /* \_SB_.PC0C._OSC.CDW2 */
CTRL = CDW3 /* \_SB_.PC0C._OSC.CDW3 */
CDW3 = Local0
If ((Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc") /* Unknown
UUID */))
{
CreateDWordField (Arg3, 0x0C, CDW4)
CreateDWordField (Arg3, 0x10, CDW5)
SUPC = CDW4 /* \_SB_.PC0C._OSC.CDW4 */
CTRC = CDW5 /* \_SB_.PC0C._OSC.CDW5 */
CDW5 |= One
}
Return (Arg3)
}
Else
{
CDW1 |= 0x04
Return (Arg3)
}
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-25-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 3d6a69b6eb973e5761c8dc489990dcd983f6c099
https://github.com/qemu/qemu/commit/3d6a69b6eb973e5761c8dc489990dcd983f6c099
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/acpi/cxl.c
M hw/i386/acpi-build.c
M hw/pci-bridge/pci_expander_bridge.c
M include/hw/acpi/cxl.h
M include/hw/pci/pci_bridge.h
Log Message:
-----------
acpi/cxl: Create the CEDT (9.14.1)
The CXL Early Discovery Table is defined in the CXL 2.0 specification as
a way for the OS to get CXL specific information from the system
firmware.
CXL 2.0 specification adds an _HID, ACPI0016, for CXL capable host
bridges, with a _CID of PNP0A08 (PCIe host bridge). CXL aware software
is able to use this initiate the proper _OSC method, and get the _UID
which is referenced by the CEDT. Therefore the existence of an ACPI0016
device allows a CXL aware driver perform the necessary actions. For a
CXL capable OS, this works. For a CXL unaware OS, this works.
CEDT awaremess requires more. The motivation for ACPI0017 is to provide
the possibility of having a Linux CXL module that can work on a legacy
Linux kernel. Linux core PCI/ACPI which won't be built as a module,
will see the _CID of PNP0A08 and bind a driver to it. If we later loaded
a driver for ACPI0016, Linux won't be able to bind it to the hardware
because it has already bound the PNP0A08 driver. The ACPI0017 device is
an opportunity to have an object to bind a driver will be used by a
Linux driver to walk the CXL topology and do everything that we would
have preferred to do with ACPI0016.
There is another motivation for an ACPI0017 device which isn't
implemented here. An operating system needs an attach point for a
non-volatile region provider that understands cross-hostbridge
interleaving. Since QEMU emulation doesn't support interleaving yet,
this is more important on the OS side, for now.
As of CXL 2.0 spec, only 1 sub structure is defined, the CXL Host Bridge
Structure (CHBS) which is primarily useful for telling the OS exactly
where the MMIO for the host bridge is.
Link:
https://lore.kernel.org/linux-cxl/20210115034911.nkgpzc756d6qmjpl@intel.com/T/#t
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-26-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 829de299d1a4dcac3cd6c494d1c974bdbc608611
https://github.com/qemu/qemu/commit/829de299d1a4dcac3cd6c494d1c974bdbc608611
Author: Jonathan Cameron <jonathan.cameron@huawei.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/cxl/cxl-component-utils.c
M include/hw/cxl/cxl_component.h
Log Message:
-----------
hw/cxl/component: Add utils for interleave parameter encoding/decoding
Both registers and the CFMWS entries in CDAT use simple encodings
for the number of interleave ways and the interleave granularity.
Introduce simple conversion functions to/from the unencoded
number / size. So far the iw decode has not been needed so is
it not implemented.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-27-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: aadfe320919b15e24ac070e9b25085e07599a613
https://github.com/qemu/qemu/commit/aadfe320919b15e24ac070e9b25085e07599a613
Author: Jonathan Cameron <jonathan.cameron@huawei.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
A hw/cxl/cxl-host-stubs.c
A hw/cxl/cxl-host.c
M hw/cxl/meson.build
M include/hw/cxl/cxl.h
M qapi/machine.json
M qemu-options.hx
M softmmu/vl.c
Log Message:
-----------
hw/cxl/host: Add support for CXL Fixed Memory Windows.
The concept of these is introduced in [1] in terms of the
description the CEDT ACPI table. The principal is more general.
Unlike once traffic hits the CXL root bridges, the host system
memory address routing is implementation defined and effectively
static once observable by standard / generic system software.
Each CXL Fixed Memory Windows (CFMW) is a region of PA space
which has fixed system dependent routing configured so that
accesses can be routed to the CXL devices below a set of target
root bridges. The accesses may be interleaved across multiple
root bridges.
For QEMU we could have fully specified these regions in terms
of a base PA + size, but as the absolute address does not matter
it is simpler to let individual platforms place the memory regions.
ExampleS:
-cxl-fixed-memory-window targets.0=cxl.0,size=128G
-cxl-fixed-memory-window targets.0=cxl.1,size=128G
-cxl-fixed-memory-window
targets.0=cxl0,targets.1=cxl.1,size=256G,interleave-granularity=2k
Specifies
* 2x 128G regions not interleaved across root bridges, one for each of
the root bridges with ids cxl.0 and cxl.1
* 256G region interleaved across root bridges with ids cxl.0 and cxl.1
with a 2k interleave granularity.
When system software enumerates the devices below a given root bridge
it can then decide which CFMW to use. If non interleave is desired
(or possible) it can use the appropriate CFMW for the root bridge in
question. If there are suitable devices to interleave across the
two root bridges then it may use the 3rd CFMS.
A number of other designs were considered but the following constraints
made it hard to adapt existing QEMU approaches to this particular problem.
1) The size must be known before a specific architecture / board brings
up it's PA memory map. We need to set up an appropriate region.
2) Using links to the host bridges provides a clean command line interface
but these links cannot be established until command line devices have
been added.
Hence the two step process used here of first establishing the size,
interleave-ways and granularity + caching the ids of the host bridges
and then, once available finding the actual host bridges so they can
be used later to support interleave decoding.
[1] CXL 2.0 ECN: CEDT CFMWS & QTG DSM (computeexpresslink.org / specifications)
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Acked-by: Markus Armbruster <armbru@redhat.com> # QAPI Schema
Message-Id: <20220429144110.25167-28-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 21df6ab97ff2c0de76ce683808356aaf98d9d1d2
https://github.com/qemu/qemu/commit/21df6ab97ff2c0de76ce683808356aaf98d9d1d2
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/acpi/cxl.c
Log Message:
-----------
acpi/cxl: Introduce CFMWS structures in CEDT
The CEDT CXL Fixed Window Memory Window Structures (CFMWs)
define regions of the host phyiscal address map which
(via an impdef means) are configured such that they have
a particular interleave setup across one or more CXL Host Bridges.
Reported-by: Alison Schofield <alison.schofield@intel.com>
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-29-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: fc1e01e009fd4b1e08399253591b32e01f10808f
https://github.com/qemu/qemu/commit/fc1e01e009fd4b1e08399253591b32e01f10808f
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/arm/Kconfig
M hw/pci-host/gpex-acpi.c
Log Message:
-----------
hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl
This adds code to instantiate the slightly extended ACPI root port
description in DSDT as per the CXL 2.0 specification.
Basically a cut and paste job from the i386/pc code.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-30-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: aa970ed586f9c7f178b813bda2919e329b841e3c
https://github.com/qemu/qemu/commit/aa970ed586f9c7f178b813bda2919e329b841e3c
Author: Jonathan Cameron <jonathan.cameron@huawei.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/pci/pcie_port.c
M include/hw/pci/pcie_port.h
Log Message:
-----------
pci/pcie_port: Add pci_find_port_by_pn()
Simple function to search a PCIBus to find a port by
it's port number.
CXL interleave decoding uses the port number as a target
so it is necessary to locate the port when doing interleave
decoding.
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-31-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 0b4aec246972f238a22d04403289eee97e8c8be6
https://github.com/qemu/qemu/commit/0b4aec246972f238a22d04403289eee97e8c8be6
Author: Jonathan Cameron <jonathan.cameron@huawei.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/pci-bridge/pci_expander_bridge.c
M include/hw/cxl/cxl_component.h
Log Message:
-----------
CXL/cxl_component: Add cxl_get_hb_cstate()
Accessor to get hold of the cxl state for a CXL host bridge
without exposing the internals of the implementation.
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-32-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 5fcc499ee3457709657b23655e385613a437068d
https://github.com/qemu/qemu/commit/5fcc499ee3457709657b23655e385613a437068d
Author: Jonathan Cameron <jonathan.cameron@huawei.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/mem/cxl_type3.c
M include/hw/cxl/cxl_device.h
Log Message:
-----------
mem/cxl_type3: Add read and write functions for associated hostmem.
Once a read or write reaches a CXL type 3 device, the HDM decoders
on the device are used to establish the Device Physical Address
which should be accessed. These functions peform the required maths
and then use a device specific address space to access the
hostmem->mr to fullfil the actual operation. Note that failed writes
are silent, but failed reads return poison. Note this is based
loosely on:
https://lore.kernel.org/qemu-devel/20200817161853.593247-6-f4bug@amsat.org/
[RFC PATCH 0/9] hw/misc: Add support for interleaved memory accesses
Only lightly tested so far. More complex test cases yet to be written.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-33-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: eb19d9079efc4e986a37b0c3172ecd9b617fd04a
https://github.com/qemu/qemu/commit/eb19d9079efc4e986a37b0c3172ecd9b617fd04a
Author: Jonathan Cameron <jonathan.cameron@huawei.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/cxl/cxl-host-stubs.c
M hw/cxl/cxl-host.c
M include/hw/cxl/cxl.h
Log Message:
-----------
cxl/cxl-host: Add memops for CFMWS region.
These memops perform interleave decoding, walking down the
CXL topology from CFMWS described host interleave
decoder via CXL host bridge HDM decoders, through the CXL
root ports and finally call CXL type 3 specific read and write
functions.
Note that, whilst functional the current implementation does
not support:
* switches
* multiple HDM decoders at a given level.
* unaligned accesses across the interleave boundaries
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Message-Id: <20220429144110.25167-34-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 3540bf56e47dce55e5035a039db97c0affc66fba
https://github.com/qemu/qemu/commit/3540bf56e47dce55e5035a039db97c0affc66fba
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/cxl/cxl-component-utils.c
Log Message:
-----------
hw/cxl/component Add a dumb HDM decoder handler
Add a trivial handler for now to cover the root bridge
where we could do some error checking in future.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-35-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 6d302cf46dfffa85a1a460d4431b1633c9ef2ff3
https://github.com/qemu/qemu/commit/6d302cf46dfffa85a1a460d4431b1633c9ef2ff3
Author: Jonathan Cameron <jonathan.cameron@huawei.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/i386/pc.c
Log Message:
-----------
i386/pc: Enable CXL fixed memory windows
Add the CFMWs memory regions to the memorymap and adjust the
PCI window to avoid hitting the same memory.
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Message-Id: <20220429144110.25167-36-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 502f99abaa58e82b186cc914e7d39d5f2bc0f1b4
https://github.com/qemu/qemu/commit/502f99abaa58e82b186cc914e7d39d5f2bc0f1b4
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
A tests/data/acpi/q35/CEDT.cxl
A tests/data/acpi/q35/DSDT.cxl
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: q35: Allow addition of a CXL test.
Add exceptions for the DSDT and the new CEDT tables
specific to a new CXL test in the following patch.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-37-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 65fc04ff3cf5b91c0490c80714f97ae6a43d7ee8
https://github.com/qemu/qemu/commit/65fc04ff3cf5b91c0490c80714f97ae6a43d7ee8
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
qtests/bios-tables-test: Add a test for CXL emulation.
The DSDT includes several CXL specific elements and the CEDT
table is only present if we enable CXL.
The test exercises all current functionality with several
CFMWS, CHBS structures in CEDT and ACPI0016/ACPI00017 and _OSC
entries in DSDT.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-38-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: aa48799530ad506c311566da5ea8ef654cdb8a4e
https://github.com/qemu/qemu/commit/aa48799530ad506c311566da5ea8ef654cdb8a4e
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M tests/data/acpi/q35/CEDT.cxl
M tests/data/acpi/q35/DSDT.cxl
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: Add tables for CXL emulation.
Tables that differ from normal Q35 tables when running the CXL test.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-39-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 3b503d56a1880aecb94399054ae5137051de935a
https://github.com/qemu/qemu/commit/3b503d56a1880aecb94399054ae5137051de935a
Author: Ben Widawsky <ben.widawsky@intel.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M tests/qtest/cxl-test.c
Log Message:
-----------
qtest/cxl: Add more complex test cases with CFMWs
Add CXL Fixed Memory Windows to the CXL tests.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Co-developed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-40-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: aa69abe6e8b0f2dbc3022359a8947fa37bf988b9
https://github.com/qemu/qemu/commit/aa69abe6e8b0f2dbc3022359a8947fa37bf988b9
Author: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M docs/system/device-emulation.rst
A docs/system/devices/cxl.rst
Log Message:
-----------
docs/cxl: Add initial Compute eXpress Link (CXL) documentation.
Provide an introduction to the main components of a CXL system,
with detailed explanation of memory interleaving, example command
lines and kernel configuration.
This was a challenging document to write due to the need to extract
only that subset of CXL information which is relevant to either
users of QEMU emulation of CXL or to those interested in the
implementation. Much of CXL is concerned with specific elements of
the protocol, management of memory pooling etc which is simply
not relevant to what is currently planned for CXL emulation
in QEMU. All comments welcome
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-43-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 495fe3a78749c39c0e772c4e1a55d6cb8a7e5292
https://github.com/qemu/qemu/commit/495fe3a78749c39c0e772c4e1a55d6cb8a7e5292
Author: Eugenio Pérez <eperezma@redhat.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/virtio/vhost-shadow-virtqueue.c
M hw/virtio/vhost-shadow-virtqueue.h
Log Message:
-----------
vhost: Track descriptor chain in private at SVQ
The device could have access to modify them, and it definitely have
access when we implement packed vq. Harden SVQ maintaining a private
copy of the descriptor chain. Other fields like buffer addresses are
already maintained sepparatedly.
Signed-off-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20220512175747.142058-2-eperezma@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 81abfa5724c9a6502d7a1d3a67c55f2a303a1170
https://github.com/qemu/qemu/commit/81abfa5724c9a6502d7a1d3a67c55f2a303a1170
Author: Eugenio Pérez <eperezma@redhat.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/virtio/vhost-shadow-virtqueue.c
Log Message:
-----------
vhost: Fix device's used descriptor dequeue
Only the first one of them were properly enqueued back.
Fixes: 100890f7ca ("vhost: Shadow virtqueue buffers forwarding")
Signed-off-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20220512175747.142058-3-eperezma@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 639036477ef890958415967e753ca2cbb348c16c
https://github.com/qemu/qemu/commit/639036477ef890958415967e753ca2cbb348c16c
Author: Eugenio Pérez <eperezma@redhat.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/virtio/vhost-vdpa.c
Log Message:
-----------
vdpa: Fix bad index calculus at vhost_vdpa_get_vring_base
Fixes: 6d0b222666 ("vdpa: Adapt vhost_vdpa_get_vring_base to SVQ")
Acked-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20220512175747.142058-4-eperezma@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1c82fdfef8a227518ffecae9d419bcada995c202
https://github.com/qemu/qemu/commit/1c82fdfef8a227518ffecae9d419bcada995c202
Author: Eugenio Pérez <eperezma@redhat.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/virtio/vhost-vdpa.c
Log Message:
-----------
vdpa: Fix index calculus at vhost_vdpa_svqs_start
With the introduction of MQ the index of the vq needs to be calculated
with the device model vq_index.
Signed-off-by: Eugenio Pérez <eperezma@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220512175747.142058-5-eperezma@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: d792199de55ca5cb5334016884039c740290b5c7
https://github.com/qemu/qemu/commit/d792199de55ca5cb5334016884039c740290b5c7
Author: Philippe Mathieu-Daudé <philmd@redhat.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/net/virtio-net.c
M hw/virtio/virtio-crypto.c
Log Message:
-----------
hw/virtio: Replace g_memdup() by g_memdup2()
Per
https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538
The old API took the size of the memory to duplicate as a guint,
whereas most memory functions take memory sizes as a gsize. This
made it easy to accidentally pass a gsize to g_memdup(). For large
values, that would lead to a silent truncation of the size from 64
to 32 bits, and result in a heap area being returned which is
significantly smaller than what the caller expects. This can likely
be exploited in various modules to cause a heap buffer overflow.
Replace g_memdup() by the safer g_memdup2() wrapper.
Acked-by: Jason Wang <jasowang@redhat.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20220512175747.142058-6-eperezma@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 5181db132b587754dda3a520eec923b87a65bbb7
https://github.com/qemu/qemu/commit/5181db132b587754dda3a520eec923b87a65bbb7
Author: Eugenio Pérez <eperezma@redhat.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M hw/virtio/vhost-shadow-virtqueue.c
Log Message:
-----------
vhost: Fix element in vhost_svq_add failure
Coverity rightly reports that is not free in that case.
Fixes: Coverity CID 1487559
Fixes: 100890f7ca ("vhost: Shadow virtqueue buffers forwarding")
Signed-off-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <20220512175747.142058-7-eperezma@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: dc89f32d92bba795b0665f075b78d8881cf67ab3
https://github.com/qemu/qemu/commit/dc89f32d92bba795b0665f075b78d8881cf67ab3
Author: David Woodhouse <dwmw2@infradead.org>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/i386/pc.c
M hw/i386/x86.c
M target/i386/kvm/kvm-cpu.c
Log Message:
-----------
target/i386: Fix sanity check on max APIC ID / X2APIC enablement
The check on x86ms->apic_id_limit in pc_machine_done() had two problems.
Firstly, we need KVM to support the X2APIC API in order to allow IRQ
delivery to APICs >= 255. So we need to call/check kvm_enable_x2apic(),
which was done elsewhere in *some* cases but not all.
Secondly, microvm needs the same check. So move it from pc_machine_done()
to x86_cpus_init() where it will work for both.
The check in kvm_cpu_instance_init() is now redundant and can be dropped.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Acked-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20220314142544.150555-1-dwmw2@infradead.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 8646d9c773d88c3f9a20919a96afa35e6230c1ee
https://github.com/qemu/qemu/commit/8646d9c773d88c3f9a20919a96afa35e6230c1ee
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/i386/intel_iommu.c
M include/hw/i386/intel_iommu.h
Log Message:
-----------
intel_iommu: Support IR-only mode without DMA translation
By setting none of the SAGAW bits we can indicate to a guest that DMA
translation isn't supported. Tested by booting Windows 10, as well as
Linux guests with the fix at https://git.kernel.org/torvalds/c/c40aaaac10
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Peter Xu <peterx@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220314142544.150555-2-dwmw2@infradead.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 175f3a59863d7263597011ae86bc57108539ba35
https://github.com/qemu/qemu/commit/175f3a59863d7263597011ae86bc57108539ba35
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel_iommu: Only allow interrupt remapping to be enabled if it's supported
We should probably check if we were meant to be exposing IR, before
letting the guest turn the IRE bit on.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Peter Xu <peterx@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220314142544.150555-3-dwmw2@infradead.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 77250171bdc02aee106083fd2a068147befa1a38
https://github.com/qemu/qemu/commit/77250171bdc02aee106083fd2a068147befa1a38
Author: David Woodhouse <dwmw2@infradead.org>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel_iommu: Fix irqchip / X2APIC configuration checks
We don't need to check kvm_enable_x2apic(). It's perfectly OK to support
interrupt remapping even if we can't address CPUs above 254. Kind of
pointless, but still functional.
The check on kvm_enable_x2apic() needs to happen *anyway* in order to
allow CPUs above 254 even without an IOMMU, so allow that to happen
elsewhere.
However, we do require the *split* irqchip in order to rewrite I/OAPIC
destinations. So fix that check while we're here.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Acked-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20220314142544.150555-4-dwmw2@infradead.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a48a5bcd641773dca66840908d2c6d9552e3d1c6
https://github.com/qemu/qemu/commit/a48a5bcd641773dca66840908d2c6d9552e3d1c6
Author: Jason Wang <jasowang@redhat.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
Log Message:
-----------
intel-iommu: remove VTD_FR_RESERVED_ERR
This fault reason is not used and is duplicated with SPT.2 condition
code. So let's remove it.
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220210092815.45174-1-jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Commit: ea97a1bde7b7940bb2100b645b6f1abc7330e248
https://github.com/qemu/qemu/commit/ea97a1bde7b7940bb2100b645b6f1abc7330e248
Author: Jason Wang <jasowang@redhat.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
Log Message:
-----------
intel-iommu: block output address in interrupt address range
According to vtd spec v3.3 3.14:
"""
Software must not program paging-structure entries to remap any
address to the interrupt address range. Untranslated requests and
translation requests that result in an address in the interrupt range
will be blocked with condition code LGN.4 or SGN.8.
"""
This patch blocks the request that result in interrupt address range.
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220210092815.45174-2-jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Commit: ceb058955ab529937498acfd3c9259a2a64b2d4e
https://github.com/qemu/qemu/commit/ceb058955ab529937498acfd3c9259a2a64b2d4e
Author: Jason Wang <jasowang@redhat.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel-iommu: update root_scalable before switching as during post_load
We need check whether passthrough is enabled during
vtd_switch_address_space() by checking the context entries. This
requires the root_scalable to be set correctly otherwise we may try to
check legacy rsvd bits instead of scalable ones.
Fixing this by updating root_scalable before switching the address
spaces during post_load.
Fixes: fb43cf739e ("intel_iommu: scalable mode emulation")
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220317080522.14621-1-jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Commit: 147a372e7580dc5cf4310d159db2f374e38ac30e
https://github.com/qemu/qemu/commit/147a372e7580dc5cf4310d159db2f374e38ac30e
Author: Jason Wang <jasowang@redhat.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel-iommu: update iq_dw during post load
We need to update iq_dw according to the DMA_IRQ_REG during post
load. Otherwise we may get wrong IOTLB invalidation descriptor after
migration.
Fixes: fb43cf739e ("intel_iommu: scalable mode emulation")
Signed-off-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20220317080522.14621-2-jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Commit: 1eed051c8c8cd84e69f619b0adc22df543ed7f06
https://github.com/qemu/qemu/commit/1eed051c8c8cd84e69f619b0adc22df543ed7f06
Author: Ilya Maximets <i.maximets@ovn.org>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/net/vhost_net.c
Log Message:
-----------
vhost_net: Print feature masks in hex
"0x200000000" is much more readable than "8589934592".
The change saves one step (conversion) while debugging.
Signed-off-by: Ilya Maximets <i.maximets@ovn.org>
Message-Id: <20220318140440.596019-1-i.maximets@ovn.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: e1b1f5341a860e87c6f208e2eea7a3b2bab454dd
https://github.com/qemu/qemu/commit/e1b1f5341a860e87c6f208e2eea7a3b2bab454dd
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/virtio/vhost-scsi-pci.c
M hw/virtio/vhost-user-blk-pci.c
M hw/virtio/vhost-user-fs-pci.c
M hw/virtio/vhost-user-i2c-pci.c
M hw/virtio/vhost-user-input-pci.c
M hw/virtio/vhost-user-rng-pci.c
M hw/virtio/vhost-user-scsi-pci.c
M hw/virtio/vhost-user-vsock-pci.c
M hw/virtio/vhost-vsock-pci.c
M hw/virtio/virtio-9p-pci.c
M hw/virtio/virtio-balloon-pci.c
M hw/virtio/virtio-blk-pci.c
M hw/virtio/virtio-input-host-pci.c
M hw/virtio/virtio-input-pci.c
M hw/virtio/virtio-iommu-pci.c
M hw/virtio/virtio-net-pci.c
M hw/virtio/virtio-pci.c
R hw/virtio/virtio-pci.h
M hw/virtio/virtio-rng-pci.c
M hw/virtio/virtio-scsi-pci.c
M hw/virtio/virtio-serial-pci.c
A include/hw/virtio/virtio-pci.h
Log Message:
-----------
hw/virtio: move virtio-pci.h into shared include space
This allows other device classes that will be exposed via PCI to be
able to do so in the appropriate hw/ directory. I resisted the
temptation to re-order headers to be more aesthetically pleasing.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20200925125147.26943-4-alex.bennee@linaro.org>
Message-Id: <20220321153037.3622127-2-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 31cc62bb5bd43b6c36b1f42d5bde6baca4dffaee
https://github.com/qemu/qemu/commit/31cc62bb5bd43b6c36b1f42d5bde6baca4dffaee
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/virtio/trace-events
M hw/virtio/virtio-pci.c
Log Message:
-----------
virtio-pci: add notification trace points
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20200925125147.26943-6-alex.bennee@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220321153037.3622127-3-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 6ca6d8ee9dd053eaa625aad48d95d12f4418ef4c
https://github.com/qemu/qemu/commit/6ca6d8ee9dd053eaa625aad48d95d12f4418ef4c
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/virtio/trace-events
M hw/virtio/vhost-user.c
Log Message:
-----------
hw/virtio: add vhost_user_[read|write] trace points
These are useful when trying to debug the initial vhost-user
negotiation, especially when it hard to get logging from the low level
library on the other side.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220321153037.3622127-4-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 43725d4844cc516e8c1b92c7903aeb0e88360f1b
https://github.com/qemu/qemu/commit/43725d4844cc516e8c1b92c7903aeb0e88360f1b
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M docs/interop/vhost-user.rst
Log Message:
-----------
docs: vhost-user: clean up request/reply description
It is not necessary to mention which side is sending/receiving
each payload; it is more interesting to say which is the request
and which is the reply. This also matches what vhost-user-gpu.rst
already does.
While at it, ensure that all messages list both the request and
the reply payload.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20210226143413.188046-2-pbonzini@redhat.com>
Message-Id: <20220321153037.3622127-5-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 0647098d2ed69171b8bdce495cfdd1c5223010f1
https://github.com/qemu/qemu/commit/0647098d2ed69171b8bdce495cfdd1c5223010f1
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M docs/interop/vhost-user.rst
Log Message:
-----------
docs: vhost-user: rewrite section on ring state machine
This section is using the word "back-end" to refer to the
"slave's back-end", and talking about the "client" for
what the rest of the document calls the "slave".
Rework it to free the use of the term "back-end", which in
the next patch will replace "slave".
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20210226143413.188046-3-pbonzini@redhat.com>
Message-Id: <20220321153037.3622127-6-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: bd59f2a1823a458ac27c09e1f27f30098745381e
https://github.com/qemu/qemu/commit/bd59f2a1823a458ac27c09e1f27f30098745381e
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M docs/interop/vhost-user-gpu.rst
M docs/interop/vhost-user.rst
Log Message:
-----------
docs: vhost-user: replace master/slave with front-end/back-end
This matches the nomenclature that is generally used. Also commonly used
is client/server, but it is not as clear because sometimes the front-end
exposes a passive (server) socket that the back-end connects to.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20210226143413.188046-4-pbonzini@redhat.com>
Message-Id: <20220321153037.3622127-7-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: fa9972662ce5b6d50fe7190efeb48a5a9fecca91
https://github.com/qemu/qemu/commit/fa9972662ce5b6d50fe7190efeb48a5a9fecca91
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M docs/interop/vhost-user.rst
Log Message:
-----------
vhost-user.rst: add clarifying language about protocol negotiation
Make the language about feature negotiation explicitly clear about the
handling of the VHOST_USER_F_PROTOCOL_FEATURES feature bit. Try and
avoid the sort of bug introduced in vhost.rs REPLY_ACK processing:
https://github.com/rust-vmm/vhost/pull/24
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Jiang Liu <gerry@linux.alibaba.com>
Message-Id: <20210226111619.21178-1-alex.bennee@linaro.org>
Message-Id: <20220321153037.3622127-8-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 467eeb0f80798457ba83040f7adb1e6b29c7c6a9
https://github.com/qemu/qemu/commit/467eeb0f80798457ba83040f7adb1e6b29c7c6a9
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M subprojects/libvhost-user/libvhost-user.c
M subprojects/libvhost-user/libvhost-user.h
Log Message:
-----------
libvhost-user: expose vu_request_to_string
This is useful for more human readable debug messages in vhost-user
programs.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220321153037.3622127-9-alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: bcf317f8591083fc11c3167f8048c826475efc39
https://github.com/qemu/qemu/commit/bcf317f8591083fc11c3167f8048c826475efc39
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M docs/devel/index-internals.rst
A docs/devel/virtio-backends.rst
Log Message:
-----------
docs/devel: start documenting writing VirtIO devices
While writing my own VirtIO devices I've gotten confused with how
things are structured and what sort of shared infrastructure there is.
If we can document how everything is supposed to work we can then
maybe start cleaning up inconsistencies in the code.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Stefan Hajnoczi <stefanha@redhat.com>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-Id: <20220309164929.19395-1-alex.bennee@linaro.org>
Message-Id: <20220321153037.3622127-10-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 27351992bf238f669dd08655d31ad111905bf899
https://github.com/qemu/qemu/commit/27351992bf238f669dd08655d31ad111905bf899
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M include/hw/virtio/vhost.h
Log Message:
-----------
include/hw: start documenting the vhost API
While trying to get my head around the nest of interactions for vhost
devices I though I could start by documenting the key API functions.
This patch documents the main API hooks for creating and starting a
vhost device as well as how the configuration changes are handled.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Stefan Hajnoczi <stefanha@redhat.com>
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20220321153037.3622127-11-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 56534930b5cd3a6c7259cfeba69f08ba28c8f62a
https://github.com/qemu/qemu/commit/56534930b5cd3a6c7259cfeba69f08ba28c8f62a
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/scsi/vhost-user-scsi.c
M hw/virtio/vhost-user.c
M include/hw/virtio/vhost-user.h
Log Message:
-----------
hw/virtio/vhost-user: don't suppress F_CONFIG when supported
Previously we would silently suppress VHOST_USER_PROTOCOL_F_CONFIG
during the protocol negotiation if the QEMU stub hadn't implemented
the vhost_dev_config_notifier. However this isn't the only way we can
handle config messages, the existing vdc->get/set_config can do this
as well.
Lightly re-factor the code to check for both potential methods and
instead of silently squashing the feature error out. It is unlikely
that a vhost-user backend expecting to handle CONFIG messages will
behave correctly if they never get sent.
Fixes: 1c3e5a2617 ("vhost-user: back SET/GET_CONFIG requests with a protocol
feature")
Cc: Maxime Coquelin <maxime.coquelin@redhat.com>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220321153037.3622127-13-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 503e355465ba0eafad49c2e174995d2e234ed288
https://github.com/qemu/qemu/commit/503e355465ba0eafad49c2e174995d2e234ed288
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/virtio/trace-events
M hw/virtio/vhost-user.c
M include/hw/virtio/vhost-user.h
Log Message:
-----------
virtio/vhost-user: dynamically assign VhostUserHostNotifiers
At a couple of hundred bytes per notifier allocating one for every
potential queue is very wasteful as most devices only have a few
queues. Instead of having this handled statically dynamically assign
them and track in a GPtrArray.
[AJB: it's hard to trigger the vhost notifiers code, I assume as it
requires a KVM guest with appropriate backend]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220321153037.3622127-14-alex.bennee@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 3857cd5c7ffd0bcc49bd2b66654af0909c847d02
https://github.com/qemu/qemu/commit/3857cd5c7ffd0bcc49bd2b66654af0909c847d02
Author: Jonah Palmer <jonah.palmer@oracle.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/9pfs/virtio-9p-device.c
M hw/block/vhost-user-blk.c
M hw/block/virtio-blk.c
M hw/char/virtio-serial-bus.c
M hw/display/virtio-gpu-base.c
M hw/input/virtio-input.c
M hw/net/virtio-net.c
M hw/scsi/virtio-scsi.c
M hw/virtio/vhost-user-fs.c
M hw/virtio/vhost-user-i2c.c
M hw/virtio/vhost-user-rng.c
M hw/virtio/vhost-user-vsock.c
M hw/virtio/vhost-vsock-common.c
M hw/virtio/vhost-vsock.c
M hw/virtio/virtio-balloon.c
M hw/virtio/virtio-crypto.c
M hw/virtio/virtio-iommu.c
M hw/virtio/virtio-mem.c
M hw/virtio/virtio-pmem.c
M hw/virtio/virtio-rng.c
M hw/virtio/virtio.c
M include/hw/virtio/vhost-vsock-common.h
M include/hw/virtio/virtio-gpu.h
M include/hw/virtio/virtio.h
Log Message:
-----------
virtio: drop name parameter for virtio_init()
This patch drops the name parameter for the virtio_init function.
The pair between the numeric device ID and the string device ID
(name) of a virtio device already exists, but not in a way that
lets us map between them.
This patch lets us do this and removes the need for the name
parameter in the virtio_init function.
Signed-off-by: Jonah Palmer <jonah.palmer@oracle.com>
Message-Id: <1648819405-25696-2-git-send-email-jonah.palmer@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c255488d67dc0d52052a12e0242bf00dcbe5223f
https://github.com/qemu/qemu/commit/c255488d67dc0d52052a12e0242bf00dcbe5223f
Author: Jonah Palmer <jonah.palmer@oracle.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/block/vhost-user-blk.c
M hw/display/vhost-user-gpu.c
M hw/input/vhost-user-input.c
M hw/net/virtio-net.c
M hw/scsi/vhost-scsi.c
M hw/virtio/vhost-user-fs.c
M hw/virtio/vhost-user-rng.c
M hw/virtio/vhost-vsock-common.c
M hw/virtio/vhost.c
M hw/virtio/virtio-crypto.c
M hw/virtio/virtio.c
M include/hw/virtio/virtio.h
Log Message:
-----------
virtio: add vhost support for virtio devices
This patch adds a get_vhost() callback function for VirtIODevices that
returns the device's corresponding vhost_dev structure, if the vhost
device is running. This patch also adds a vhost_started flag for
VirtIODevices.
Previously, a VirtIODevice wouldn't be able to tell if its corresponding
vhost device was active or not.
Signed-off-by: Jonah Palmer <jonah.palmer@oracle.com>
Message-Id: <1648819405-25696-3-git-send-email-jonah.palmer@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 37cbfcebdd0e7ffbfb8332a8794a91a4a8f1819d
https://github.com/qemu/qemu/commit/37cbfcebdd0e7ffbfb8332a8794a91a4a8f1819d
Author: Michael S. Tsirkin <mst@redhat.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M docs/interop/vhost-user.rst
Log Message:
-----------
vhost-user: more master/slave things
we switched to front-end/back-end, but newer patches
reintroduced old language. Fix this up.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 76b1b64370007234279ea4cc8b09c98cbd2523de
https://github.com/qemu/qemu/commit/76b1b64370007234279ea4cc8b09c98cbd2523de
Author: Kevin Wolf <kwolf@redhat.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M docs/interop/vhost-user.rst
Log Message:
-----------
docs/vhost-user: Clarifications for VHOST_USER_ADD/REM_MEM_REG
The specification for VHOST_USER_ADD/REM_MEM_REG messages is unclear
in several points, which has led to clients having incompatible
implementations. This changes the specification to be more explicit
about them:
* VHOST_USER_ADD_MEM_REG is not specified as receiving a file
descriptor, though it obviously does need to do so. All
implementations agree on this one, fix the specification.
* VHOST_USER_REM_MEM_REG is not specified as receiving a file
descriptor either, and it also has no reason to do so. rust-vmm does
not send file descriptors for removing a memory region (in agreement
with the specification), libvhost-user and QEMU do (which is a bug),
though libvhost-user doesn't actually make any use of it.
Change the specification so that for compatibility QEMU's behaviour
becomes legal, even if discouraged, but rust-vmm's behaviour becomes
the explicitly recommended mode of operation.
* VHOST_USER_ADD_MEM_REG doesn't have a documented return value, which
is the desired behaviour in the non-postcopy case. It also implemented
like this in QEMU and rust-vmm, though libvhost-user is buggy and
sometimes sends an unexpected reply. This will be fixed in a separate
patch.
However, in postcopy mode it does reply like VHOST_USER_SET_MEM_TABLE.
This behaviour is shared between libvhost-user and QEMU; rust-vmm
doesn't implement postcopy mode yet. Mention it explicitly in the
spec.
* The specification doesn't mention how VHOST_USER_REM_MEM_REG
identifies the memory region to be removed. Change it to describe the
existing behaviour of libvhost-user (guest address, user address and
size must match).
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Message-Id: <20220407133657.155281-2-kwolf@redhat.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 8e58f6ec24f64b7d88f2b01d39049011f5097fae
https://github.com/qemu/qemu/commit/8e58f6ec24f64b7d88f2b01d39049011f5097fae
Author: Francisco Iglesias <frasse.iglesias@gmail.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M include/hw/pci/pcie_host.h
Log Message:
-----------
include/hw/pci/pcie_host: Correct PCIE_MMCFG_BUS_MASK
According to [1] address bits 27 - 20 are mapped to the bus number (the
TLPs bus number field is 8 bits). Below is the formula taken from Table
7-1 in [1].
"
Memory Address | PCI Express Configuration Space
A[(20+n-1):20] | Bus Number, 1 ≤ n ≤ 8
"
[1] PCI Express® Base Specification Revision 5.0 Version 1.0
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220411221836.17699-2-frasse.iglesias@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1f1a7b226923c655530d6bbe7d85d87e3df2d6f1
https://github.com/qemu/qemu/commit/1f1a7b226923c655530d6bbe7d85d87e3df2d6f1
Author: Francisco Iglesias <frasse.iglesias@gmail.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M include/hw/pci/pcie_host.h
Log Message:
-----------
include/hw/pci/pcie_host: Correct PCIE_MMCFG_SIZE_MAX
According to 7.2.2 in [1] bit 27 is the last bit that can be part of the
bus number, this makes the ECAM max size equal to '1 << 28'. This patch
restores back this value into the PCIE_MMCFG_SIZE_MAX define (which was
changed in commit 58d5b22bbd5 ("ppc4xx: Add device models found in PPC440
core SoCs")).
[1] PCI Express® Base Specification Revision 5.0 Version 1.0
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220411221836.17699-3-frasse.iglesias@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 9dee7e510969787be49771e4653a123a26d1069f
https://github.com/qemu/qemu/commit/9dee7e510969787be49771e4653a123a26d1069f
Author: Xiaoyao Li <xiaoyao.li@intel.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/i386/microvm.c
M hw/i386/pc.c
M hw/i386/x86.c
M include/hw/i386/microvm.h
M include/hw/i386/pc.h
M include/hw/i386/x86.h
Log Message:
-----------
hw/i386: Make pit a property of common x86 base machine type
Both pc and microvm have pit property individually. Let's just make it
the property of common x86 base machine type.
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-Id: <20220310122811.807794-2-xiaoyao.li@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: c300bbe8d2a84003775c2ebb2b2885b80b1d9c32
https://github.com/qemu/qemu/commit/c300bbe8d2a84003775c2ebb2b2885b80b1d9c32
Author: Xiaoyao Li <xiaoyao.li@intel.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/i386/microvm.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/i386/x86.c
M include/hw/i386/microvm.h
M include/hw/i386/x86.h
Log Message:
-----------
hw/i386: Make pic a property of common x86 base machine type
Legacy PIC (8259) cannot be supported for TDX guests since TDX module
doesn't allow directly interrupt injection. Using posted interrupts
for the PIC is not a viable option as the guest BIOS/kernel will not
do EOI for PIC IRQs, i.e. will leave the vIRR bit set.
Make PIC the property of common x86 machine type. Hence all x86
machines, including microvm, can disable it.
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Sergio Lopez <slp@redhat.com>
Message-Id: <20220310122811.807794-3-xiaoyao.li@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 18aa91cddd8caa14aae094f9b59c0381959cb320
https://github.com/qemu/qemu/commit/18aa91cddd8caa14aae094f9b59c0381959cb320
Author: Wei Huang <wei.huang2@amd.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/i386/amd_iommu.c
Log Message:
-----------
hw/i386/amd_iommu: Fix IOMMU event log encoding errors
Coverity issues several UNINIT warnings against amd_iommu.c [1]. This
patch fixes them by clearing evt before encoding. On top of it, this
patch changes the event log size to 16 bytes per IOMMU specification,
and fixes the event log entry format in amdvi_encode_event().
[1] CID 1487116/1487200/1487190/1487232/1487115/1487258
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Wei Huang <wei.huang2@amd.com>
Message-Id: <20220422055146.3312226-1-wei.huang2@amd.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: aa8581945a13712ff3eed0ad3ba7a9664fc1604b
https://github.com/qemu/qemu/commit/aa8581945a13712ff3eed0ad3ba7a9664fc1604b
Author: Si-Wei Liu <si-wei.liu@oracle.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/net/virtio-net.c
Log Message:
-----------
virtio-net: setup vhost_dev and notifiers for cvq only when feature is
negotiated
When the control virtqueue feature is absent or not negotiated,
vhost_net_start() still tries to set up vhost_dev and install
vhost notifiers for the control virtqueue, which results in
erroneous ioctl calls with incorrect queue index sending down
to driver. Do that only when needed.
Fixes: 22288fe ("virtio-net: vhost control virtqueue support")
Signed-off-by: Si-Wei Liu <si-wei.liu@oracle.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <1651890498-24478-2-git-send-email-si-wei.liu@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 68b0a6395f36a8f48f56f46d05f30be2067598b0
https://github.com/qemu/qemu/commit/68b0a6395f36a8f48f56f46d05f30be2067598b0
Author: Si-Wei Liu <si-wei.liu@oracle.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/net/virtio-net.c
Log Message:
-----------
virtio-net: align ctrl_vq index for non-mq guest for vhost_vdpa
With MQ enabled vdpa device and non-MQ supporting guest e.g.
booting vdpa with mq=on over OVMF of single vqp, below assert
failure is seen:
../hw/virtio/vhost-vdpa.c:560: vhost_vdpa_get_vq_index: Assertion `idx >=
dev->vq_index && idx < dev->vq_index + dev->nvqs' failed.
0 0x00007f8ce3ff3387 in raise () at /lib64/libc.so.6
1 0x00007f8ce3ff4a78 in abort () at /lib64/libc.so.6
2 0x00007f8ce3fec1a6 in __assert_fail_base () at /lib64/libc.so.6
3 0x00007f8ce3fec252 in () at /lib64/libc.so.6
4 0x0000558f52d79421 in vhost_vdpa_get_vq_index (dev=<optimized out>,
idx=<optimized out>) at ../hw/virtio/vhost-vdpa.c:563
5 0x0000558f52d79421 in vhost_vdpa_get_vq_index (dev=<optimized out>,
idx=<optimized out>) at ../hw/virtio/vhost-vdpa.c:558
6 0x0000558f52d7329a in vhost_virtqueue_mask (hdev=0x558f55c01800,
vdev=0x558f568f91f0, n=2, mask=<optimized out>) at ../hw/virtio/vhost.c:1557
7 0x0000558f52c6b89a in virtio_pci_set_guest_notifier
(d=d@entry=0x558f568f0f60, n=n@entry=2, assign=assign@entry=true,
with_irqfd=with_irqfd@entry=false)
at ../hw/virtio/virtio-pci.c:974
8 0x0000558f52c6c0d8 in virtio_pci_set_guest_notifiers (d=0x558f568f0f60,
nvqs=3, assign=true) at ../hw/virtio/virtio-pci.c:1019
9 0x0000558f52bf091d in vhost_net_start (dev=dev@entry=0x558f568f91f0,
ncs=0x558f56937cd0, data_queue_pairs=data_queue_pairs@entry=1, cvq=cvq@entry=1)
at ../hw/net/vhost_net.c:361
10 0x0000558f52d4e5e7 in virtio_net_set_status (status=<optimized out>,
n=0x558f568f91f0) at ../hw/net/virtio-net.c:289
11 0x0000558f52d4e5e7 in virtio_net_set_status (vdev=0x558f568f91f0, status=15
'\017') at ../hw/net/virtio-net.c:370
12 0x0000558f52d6c4b2 in virtio_set_status (vdev=vdev@entry=0x558f568f91f0,
val=val@entry=15 '\017') at ../hw/virtio/virtio.c:1945
13 0x0000558f52c69eff in virtio_pci_common_write (opaque=0x558f568f0f60,
addr=<optimized out>, val=<optimized out>, size=<optimized out>) at
../hw/virtio/virtio-pci.c:1292
14 0x0000558f52d15d6e in memory_region_write_accessor (mr=0x558f568f19d0,
addr=20, value=<optimized out>, size=1, shift=<optimized out>, mask=<optimized
out>, attrs=...)
at ../softmmu/memory.c:492
15 0x0000558f52d127de in access_with_adjusted_size (addr=addr@entry=20,
value=value@entry=0x7f8cdbffe748, size=size@entry=1, access_size_min=<optimized
out>, access_size_max=<optimized out>, access_fn=0x558f52d15cf0
<memory_region_write_accessor>, mr=0x558f568f19d0, attrs=...) at
../softmmu/memory.c:554
16 0x0000558f52d157ef in memory_region_dispatch_write
(mr=mr@entry=0x558f568f19d0, addr=20, data=<optimized out>, op=<optimized out>,
attrs=attrs@entry=...)
at ../softmmu/memory.c:1504
17 0x0000558f52d078e7 in flatview_write_continue (fv=fv@entry=0x7f8accbc3b90,
addr=addr@entry=103079215124, attrs=..., ptr=ptr@entry=0x7f8ce6300028,
len=len@entry=1, addr1=<optimized out>, l=<optimized out>, mr=0x558f568f19d0)
at /home/opc/qemu-upstream/include/qemu/host-utils.h:165
18 0x0000558f52d07b06 in flatview_write (fv=0x7f8accbc3b90, addr=103079215124,
attrs=..., buf=0x7f8ce6300028, len=1) at ../softmmu/physmem.c:2822
19 0x0000558f52d0b36b in address_space_write (as=<optimized out>,
addr=<optimized out>, attrs=..., buf=buf@entry=0x7f8ce6300028, len=<optimized
out>)
at ../softmmu/physmem.c:2914
20 0x0000558f52d0b3da in address_space_rw (as=<optimized out>, addr=<optimized
out>, attrs=...,
attrs@entry=..., buf=buf@entry=0x7f8ce6300028, len=<optimized out>,
is_write=<optimized out>) at ../softmmu/physmem.c:2924
21 0x0000558f52dced09 in kvm_cpu_exec (cpu=cpu@entry=0x558f55c2da60) at
../accel/kvm/kvm-all.c:2903
22 0x0000558f52dcfabd in kvm_vcpu_thread_fn (arg=arg@entry=0x558f55c2da60) at
../accel/kvm/kvm-accel-ops.c:49
23 0x0000558f52f9f04a in qemu_thread_start (args=<optimized out>) at
../util/qemu-thread-posix.c:556
24 0x00007f8ce4392ea5 in start_thread () at /lib64/libpthread.so.0
25 0x00007f8ce40bb9fd in clone () at /lib64/libc.so.6
The cause for the assert failure is due to that the vhost_dev index
for the ctrl vq was not aligned with actual one in use by the guest.
Upon multiqueue feature negotiation in virtio_net_set_multiqueue(),
if guest doesn't support multiqueue, the guest vq layout would shrink
to a single queue pair, consisting of 3 vqs in total (rx, tx and ctrl).
This results in ctrl_vq taking a different vhost_dev group index than
the default. We can map vq to the correct vhost_dev group by checking
if MQ is supported by guest and successfully negotiated. Since the
MQ feature is only present along with CTRL_VQ, we ensure the index
2 is only meant for the control vq while MQ is not supported by guest.
Fixes: 22288fe ("virtio-net: vhost control virtqueue support")
Suggested-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: Si-Wei Liu <si-wei.liu@oracle.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <1651890498-24478-3-git-send-email-si-wei.liu@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 9bd055073e375c8a0d7ebce925e05d914d69fc7f
https://github.com/qemu/qemu/commit/9bd055073e375c8a0d7ebce925e05d914d69fc7f
Author: Si-Wei Liu <si-wei.liu@oracle.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M net/vhost-vdpa.c
Log Message:
-----------
vhost-vdpa: fix improper cleanup in net_init_vhost_vdpa
... such that no memory leaks on dangling net clients in case of
error.
Signed-off-by: Si-Wei Liu <si-wei.liu@oracle.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <1651890498-24478-4-git-send-email-si-wei.liu@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 6f3910b5eee00b8cc959e94659c0d524c482a418
https://github.com/qemu/qemu/commit/6f3910b5eee00b8cc959e94659c0d524c482a418
Author: Si-Wei Liu <si-wei.liu@oracle.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/net/vhost_net.c
Log Message:
-----------
vhost-net: fix improper cleanup in vhost_net_start
vhost_net_start() missed a corresponding stop_one() upon error from
vhost_set_vring_enable(). While at it, make the error handling for
err_start more robust. No real issue was found due to this though.
Signed-off-by: Si-Wei Liu <si-wei.liu@oracle.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <1651890498-24478-5-git-send-email-si-wei.liu@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 6aee7e4233f6467f69531fcd352adff028f3f5ea
https://github.com/qemu/qemu/commit/6aee7e4233f6467f69531fcd352adff028f3f5ea
Author: Si-Wei Liu <si-wei.liu@oracle.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/virtio/vhost-vdpa.c
Log Message:
-----------
vhost-vdpa: backend feature should set only once
The vhost_vdpa_one_time_request() branch in
vhost_vdpa_set_backend_cap() incorrectly sends down
ioctls on vhost_dev with non-zero index. This may
end up with multiple VHOST_SET_BACKEND_FEATURES
ioctl calls sent down on the vhost-vdpa fd that is
shared between all these vhost_dev's.
To fix it, send down ioctl only once via the first
vhost_dev with index 0. Toggle the polarity of the
vhost_vdpa_one_time_request() test should do the
trick.
Fixes: 4d191cfdc7de ("vhost-vdpa: classify one time request")
Signed-off-by: Si-Wei Liu <si-wei.liu@oracle.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Acked-by: Eugenio Pérez <eperezma@redhat.com>
Message-Id: <1651890498-24478-6-git-send-email-si-wei.liu@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: d71b0609fc04217e28d17009f04d74b08be6f466
https://github.com/qemu/qemu/commit/d71b0609fc04217e28d17009f04d74b08be6f466
Author: Si-Wei Liu <si-wei.liu@oracle.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/virtio/vhost-vdpa.c
Log Message:
-----------
vhost-vdpa: change name and polarity for vhost_vdpa_one_time_request()
The name vhost_vdpa_one_time_request() was confusing. No
matter whatever it returns, its typical occurrence had
always been at requests that only need to be applied once.
And the name didn't suggest what it actually checks for.
Change it to vhost_vdpa_first_dev() with polarity flipped
for better readibility of code. That way it is able to
reflect what the check is really about.
This call is applicable to request which performs operation
only once, before queues are set up, and usually at the beginning
of the caller function. Document the requirement for it in place.
Signed-off-by: Si-Wei Liu <si-wei.liu@oracle.com>
Message-Id: <1651890498-24478-7-git-send-email-si-wei.liu@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Commit: 2a7888cc3aa31faee839fa5dddad354ff8941f4c
https://github.com/qemu/qemu/commit/2a7888cc3aa31faee839fa5dddad354ff8941f4c
Author: Si-Wei Liu <si-wei.liu@oracle.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M hw/net/virtio-net.c
Log Message:
-----------
virtio-net: don't handle mq request in userspace handler for vhost-vdpa
virtio_queue_host_notifier_read() tends to read pending event
left behind on ioeventfd in the vhost_net_stop() path, and
attempts to handle outstanding kicks from userspace vq handler.
However, in the ctrl_vq handler, virtio_net_handle_mq() has a
recursive call into virtio_net_set_status(), which may lead to
segmentation fault as shown in below stack trace:
0 0x000055f800df1780 in qdev_get_parent_bus (dev=0x0) at ../hw/core/qdev.c:376
1 0x000055f800c68ad8 in virtio_bus_device_iommu_enabled (vdev=vdev@entry=0x0)
at ../hw/virtio/virtio-bus.c:331
2 0x000055f800d70d7f in vhost_memory_unmap (dev=<optimized out>) at
../hw/virtio/vhost.c:318
3 0x000055f800d70d7f in vhost_memory_unmap (dev=<optimized out>,
buffer=0x7fc19bec5240, len=2052, is_write=1, access_len=2052) at
../hw/virtio/vhost.c:336
4 0x000055f800d71867 in vhost_virtqueue_stop (dev=dev@entry=0x55f8037ccc30,
vdev=vdev@entry=0x55f8044ec590, vq=0x55f8037cceb0, idx=0) at
../hw/virtio/vhost.c:1241
5 0x000055f800d7406c in vhost_dev_stop (hdev=hdev@entry=0x55f8037ccc30,
vdev=vdev@entry=0x55f8044ec590) at ../hw/virtio/vhost.c:1839
6 0x000055f800bf00a7 in vhost_net_stop_one (net=0x55f8037ccc30,
dev=0x55f8044ec590) at ../hw/net/vhost_net.c:315
7 0x000055f800bf0678 in vhost_net_stop (dev=dev@entry=0x55f8044ec590,
ncs=0x55f80452bae0, data_queue_pairs=data_queue_pairs@entry=7, cvq=cvq@entry=1)
at ../hw/net/vhost_net.c:423
8 0x000055f800d4e628 in virtio_net_set_status (status=<optimized out>,
n=0x55f8044ec590) at ../hw/net/virtio-net.c:296
9 0x000055f800d4e628 in virtio_net_set_status (vdev=vdev@entry=0x55f8044ec590,
status=15 '\017') at ../hw/net/virtio-net.c:370
10 0x000055f800d534d8 in virtio_net_handle_ctrl (iov_cnt=<optimized out>,
iov=<optimized out>, cmd=0 '\000', n=0x55f8044ec590) at
../hw/net/virtio-net.c:1408
11 0x000055f800d534d8 in virtio_net_handle_ctrl (vdev=0x55f8044ec590,
vq=0x7fc1a7e888d0) at ../hw/net/virtio-net.c:1452
12 0x000055f800d69f37 in virtio_queue_host_notifier_read (vq=0x7fc1a7e888d0) at
../hw/virtio/virtio.c:2331
13 0x000055f800d69f37 in virtio_queue_host_notifier_read
(n=n@entry=0x7fc1a7e8894c) at ../hw/virtio/virtio.c:3575
14 0x000055f800c688e6 in virtio_bus_cleanup_host_notifier (bus=<optimized out>,
n=n@entry=14) at ../hw/virtio/virtio-bus.c:312
15 0x000055f800d73106 in vhost_dev_disable_notifiers
(hdev=hdev@entry=0x55f8035b51b0, vdev=vdev@entry=0x55f8044ec590)
at ../../../include/hw/virtio/virtio-bus.h:35
16 0x000055f800bf00b2 in vhost_net_stop_one (net=0x55f8035b51b0,
dev=0x55f8044ec590) at ../hw/net/vhost_net.c:316
17 0x000055f800bf0678 in vhost_net_stop (dev=dev@entry=0x55f8044ec590,
ncs=0x55f80452bae0, data_queue_pairs=data_queue_pairs@entry=7, cvq=cvq@entry=1)
at ../hw/net/vhost_net.c:423
18 0x000055f800d4e628 in virtio_net_set_status (status=<optimized out>,
n=0x55f8044ec590) at ../hw/net/virtio-net.c:296
19 0x000055f800d4e628 in virtio_net_set_status (vdev=0x55f8044ec590, status=15
'\017') at ../hw/net/virtio-net.c:370
20 0x000055f800d6c4b2 in virtio_set_status (vdev=0x55f8044ec590, val=<optimized
out>) at ../hw/virtio/virtio.c:1945
21 0x000055f800d11d9d in vm_state_notify (running=running@entry=false,
state=state@entry=RUN_STATE_SHUTDOWN) at ../softmmu/runstate.c:333
22 0x000055f800d04e7a in do_vm_stop (state=state@entry=RUN_STATE_SHUTDOWN,
send_stop=send_stop@entry=false) at ../softmmu/cpus.c:262
23 0x000055f800d04e99 in vm_shutdown () at ../softmmu/cpus.c:280
24 0x000055f800d126af in qemu_cleanup () at ../softmmu/runstate.c:812
25 0x000055f800ad5b13 in main (argc=<optimized out>, argv=<optimized out>,
envp=<optimized out>) at ../softmmu/main.c:51
For now, temporarily disable handling MQ request from the ctrl_vq
userspace hanlder to avoid the recursive virtio_net_set_status()
call. Some rework is needed to allow changing the number of
queues without going through a full virtio_net_set_status cycle,
particularly for vhost-vdpa backend.
This patch will need to be reverted as soon as future patches of
having the change of #queues handled in userspace is merged.
Fixes: 402378407db ("vhost-vdpa: multiqueue support")
Signed-off-by: Si-Wei Liu <si-wei.liu@oracle.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <1651890498-24478-8-git-send-email-si-wei.liu@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 6852c21db229c4bf4c1db772444bdfbbd027e5b8
https://github.com/qemu/qemu/commit/6852c21db229c4bf4c1db772444bdfbbd027e5b8
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M contrib/vhost-user-scsi/vhost-user-scsi.c
Log Message:
-----------
vhost-user-scsi: avoid unlink(NULL) with fd passing
Commit 747421e949fc1eb3ba66b5fcccdb7ba051918241 ("Implements Backend
Program conventions for vhost-user-scsi") introduced fd-passing support
as part of implementing the vhost-user backend program conventions.
When fd passing is used the UNIX domain socket path is NULL and we must
not call unlink(2).
The unlink(2) call is necessary when the listen socket, lsock, was
created successfully since that means the UNIX domain socket is visible
in the file system.
Fixes: Coverity CID 1488353
Fixes: 747421e949fc1eb3ba66b5fcccdb7ba051918241 ("Implements Backend Program
conventions for vhost-user-scsi")
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20220516155701.1789638-1-stefanha@redhat.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: eec398119fc6911d99412c37af06a6bc27871f85
https://github.com/qemu/qemu/commit/eec398119fc6911d99412c37af06a6bc27871f85
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-16 (Mon, 16 May 2022)
Changed paths:
M MAINTAINERS
M contrib/vhost-user-scsi/vhost-user-scsi.c
M docs/devel/index-internals.rst
A docs/devel/virtio-backends.rst
M docs/interop/vhost-user-gpu.rst
M docs/interop/vhost-user.rst
M docs/system/device-emulation.rst
A docs/system/devices/cxl.rst
M hw/9pfs/virtio-9p-device.c
M hw/Kconfig
M hw/acpi/Kconfig
A hw/acpi/cxl-stub.c
A hw/acpi/cxl.c
M hw/acpi/meson.build
M hw/arm/Kconfig
M hw/block/vhost-user-blk.c
M hw/block/virtio-blk.c
M hw/char/virtio-serial-bus.c
M hw/core/machine.c
A hw/cxl/Kconfig
A hw/cxl/cxl-component-utils.c
A hw/cxl/cxl-device-utils.c
A hw/cxl/cxl-host-stubs.c
A hw/cxl/cxl-host.c
A hw/cxl/cxl-mailbox-utils.c
A hw/cxl/meson.build
M hw/display/vhost-user-gpu.c
M hw/display/virtio-gpu-base.c
M hw/i386/acpi-build.c
M hw/i386/amd_iommu.c
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
M hw/i386/microvm.c
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/i386/x86.c
M hw/input/vhost-user-input.c
M hw/input/virtio-input.c
M hw/mem/Kconfig
A hw/mem/cxl_type3.c
M hw/mem/meson.build
M hw/meson.build
M hw/net/vhost_net.c
M hw/net/virtio-net.c
M hw/pci-bridge/Kconfig
A hw/pci-bridge/cxl_root_port.c
M hw/pci-bridge/meson.build
M hw/pci-bridge/pci_expander_bridge.c
M hw/pci-bridge/pcie_root_port.c
M hw/pci-host/gpex-acpi.c
M hw/pci/pci.c
M hw/pci/pcie_port.c
M hw/scsi/vhost-scsi.c
M hw/scsi/vhost-user-scsi.c
M hw/scsi/virtio-scsi.c
M hw/virtio/trace-events
M hw/virtio/vhost-scsi-pci.c
M hw/virtio/vhost-shadow-virtqueue.c
M hw/virtio/vhost-shadow-virtqueue.h
M hw/virtio/vhost-user-blk-pci.c
M hw/virtio/vhost-user-fs-pci.c
M hw/virtio/vhost-user-fs.c
M hw/virtio/vhost-user-i2c-pci.c
M hw/virtio/vhost-user-i2c.c
M hw/virtio/vhost-user-input-pci.c
M hw/virtio/vhost-user-rng-pci.c
M hw/virtio/vhost-user-rng.c
M hw/virtio/vhost-user-scsi-pci.c
M hw/virtio/vhost-user-vsock-pci.c
M hw/virtio/vhost-user-vsock.c
M hw/virtio/vhost-user.c
M hw/virtio/vhost-vdpa.c
M hw/virtio/vhost-vsock-common.c
M hw/virtio/vhost-vsock-pci.c
M hw/virtio/vhost-vsock.c
M hw/virtio/vhost.c
M hw/virtio/virtio-9p-pci.c
M hw/virtio/virtio-balloon-pci.c
M hw/virtio/virtio-balloon.c
M hw/virtio/virtio-blk-pci.c
M hw/virtio/virtio-bus.c
M hw/virtio/virtio-crypto.c
M hw/virtio/virtio-input-host-pci.c
M hw/virtio/virtio-input-pci.c
M hw/virtio/virtio-iommu-pci.c
M hw/virtio/virtio-iommu.c
M hw/virtio/virtio-mem.c
M hw/virtio/virtio-net-pci.c
M hw/virtio/virtio-pci.c
R hw/virtio/virtio-pci.h
M hw/virtio/virtio-pmem.c
M hw/virtio/virtio-rng-pci.c
M hw/virtio/virtio-rng.c
M hw/virtio/virtio-scsi-pci.c
M hw/virtio/virtio-serial-pci.c
M hw/virtio/virtio.c
A include/hw/acpi/cxl.h
M include/hw/boards.h
A include/hw/cxl/cxl.h
A include/hw/cxl/cxl_component.h
A include/hw/cxl/cxl_device.h
A include/hw/cxl/cxl_pci.h
M include/hw/i386/intel_iommu.h
M include/hw/i386/microvm.h
M include/hw/i386/pc.h
M include/hw/i386/x86.h
M include/hw/pci/pci.h
M include/hw/pci/pci_bridge.h
M include/hw/pci/pci_bus.h
M include/hw/pci/pci_ids.h
M include/hw/pci/pcie_host.h
M include/hw/pci/pcie_port.h
M include/hw/virtio/vhost-user.h
M include/hw/virtio/vhost-vsock-common.h
M include/hw/virtio/vhost.h
M include/hw/virtio/virtio-gpu.h
A include/hw/virtio/virtio-pci.h
M include/hw/virtio/virtio.h
M net/vhost-vdpa.c
M qapi/machine.json
M qemu-options.hx
M scripts/device-crash-test
M softmmu/vl.c
M subprojects/libvhost-user/libvhost-user.c
M subprojects/libvhost-user/libvhost-user.h
M target/i386/kvm/kvm-cpu.c
A tests/data/acpi/q35/CEDT.cxl
A tests/data/acpi/q35/DSDT.cxl
M tests/qtest/bios-tables-test.c
A tests/qtest/cxl-test.c
M tests/qtest/meson.build
Log Message:
-----------
Merge tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu
into staging
virtio,pc,pci: fixes,cleanups,features
most of CXL support
fixes, cleanups all over the place
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# -----BEGIN PGP SIGNATURE-----
#
# iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmKCuLIPHG1zdEByZWRo
# YXQuY29tAAoJECgfDbjSjVRpdDUH/12SmWaAo+0+SdIHgWFFxsmg3t/EdcO38fgi
# MV+GpYdbp6TlU3jdQhrMZYmFdkVVydBdxk93ujCLbFS0ixTsKj31j0IbZMfdcGgv
# SLqnV+E3JdHqnGP39q9a9rdwYWyqhkgHoldxilIFW76ngOSapaZVvnwnOMAMkf77
# 1LieL4/Xq7N9Ho86Zrs3IczQcf0czdJRDaFaSIu8GaHl8ELyuPhlSm6CSqqrEEWR
# PA/COQsLDbLOMxbfCi5v88r5aaxmGNZcGbXQbiH9qVHw65nlHyLH9UkNTdJn1du1
# f2GYwwa7eekfw/LCvvVwxO1znJrj02sfFai7aAtQYbXPvjvQiqA=
# =xdSk
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 16 May 2022 01:48:50 PM PDT
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [undefined]
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (86
commits)
vhost-user-scsi: avoid unlink(NULL) with fd passing
virtio-net: don't handle mq request in userspace handler for vhost-vdpa
vhost-vdpa: change name and polarity for vhost_vdpa_one_time_request()
vhost-vdpa: backend feature should set only once
vhost-net: fix improper cleanup in vhost_net_start
vhost-vdpa: fix improper cleanup in net_init_vhost_vdpa
virtio-net: align ctrl_vq index for non-mq guest for vhost_vdpa
virtio-net: setup vhost_dev and notifiers for cvq only when feature is
negotiated
hw/i386/amd_iommu: Fix IOMMU event log encoding errors
hw/i386: Make pic a property of common x86 base machine type
hw/i386: Make pit a property of common x86 base machine type
include/hw/pci/pcie_host: Correct PCIE_MMCFG_SIZE_MAX
include/hw/pci/pcie_host: Correct PCIE_MMCFG_BUS_MASK
docs/vhost-user: Clarifications for VHOST_USER_ADD/REM_MEM_REG
vhost-user: more master/slave things
virtio: add vhost support for virtio devices
virtio: drop name parameter for virtio_init()
virtio/vhost-user: dynamically assign VhostUserHostNotifiers
hw/virtio/vhost-user: don't suppress F_CONFIG when supported
include/hw: start documenting the vhost API
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/afdb415e67e1...eec398119fc6