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[Qemu-commits] [qemu/qemu] 14d5ad: MAINTAINERS/.mailmap: update email fo
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 14d5ad: MAINTAINERS/.mailmap: update email for Leif Lindholm |
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Date: |
Mon, 09 May 2022 09:39:23 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 14d5addcaedae2e8666aeda71510e1d4be5bb50d
https://github.com/qemu/qemu/commit/14d5addcaedae2e8666aeda71510e1d4be5bb50d
Author: Leif Lindholm <quic_llindhol@quicinc.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M .mailmap
M MAINTAINERS
Log Message:
-----------
MAINTAINERS/.mailmap: update email for Leif Lindholm
NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
separate infrastructure for a transitional period. We've now switched
over to contributing as Qualcomm Innovation Center (quicinc), so update
my email address to reflect this.
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[Fixed commit message typo]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 696ba3771894f7a0b233e634dc9d401330568e35
https://github.com/qemu/qemu/commit/696ba3771894f7a0b233e634dc9d401330568e35
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpregs.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Handle cpreg registration for missing EL
More gracefully handle cpregs when EL2 and/or EL3 are missing.
If the reg is entirely inaccessible, do not register it at all.
If the reg is for EL2, and EL3 is present but EL2 is not,
either discard, squash to res0, const, or keep unchanged.
Per rule RJFFP, mark the 4 aarch32 hypervisor access registers
with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address
translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF.
Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ.
This will simplify cpreg registration for conditional arm features.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 99a90811d09e58630c1c43c43b644501ce12ced0
https://github.com/qemu/qemu/commit/99a90811d09e58630c1c43c43b644501ce12ced0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Drop EL3 no EL2 fallbacks
Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local
vpidr_regs definition, and rely on the squashing to ARM_CP_CONST
while registering for v8.
This is a behavior change for v7 cpus with Security Extensions and
without Virtualization Extensions, in that the virtualization cpregs
are now correctly not present. This would be a migration compatibility
break, except that we have an existing bug in which migration of 32-bit
cpus with Security Extensions enabled does not work.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 60360d82a1022f8db9cbe5ed312de14b490fa46e
https://github.com/qemu/qemu/commit/60360d82a1022f8db9cbe5ed312de14b490fa46e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Merge zcr reginfo
Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
while registering.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 52d187275b3a306c6bc83c083885ae34e0939f0d
https://github.com/qemu/qemu/commit/52d187275b3a306c6bc83c083885ae34e0939f0d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Adjust definition of CONTEXTIDR_EL2
This register is present for either VHE or Debugv8p2.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7c1aaf98ff6b06e96de1a25fa8e3214eb402bd77
https://github.com/qemu/qemu/commit/7c1aaf98ff6b06e96de1a25fa8e3214eb402bd77
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Move cortex impdef sysregs to cpu_tcg.c
Previously we were defining some of these in user-only mode,
but none of them are accessible from user-only, therefore
define them only in system mode.
This will shortly be used from cpu_tcg.c also.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7e834daf0abe785041804a63f6b65b095ece8e6c
https://github.com/qemu/qemu/commit/7e834daf0abe785041804a63f6b65b095ece8e6c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Update qemu-system-arm -cpu max to cortex-a57
Instead of starting with cortex-a15 and adding v8 features to
a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
This fixes the long-standing to-do where we only enabled v8
features for user-only.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e14cc941f109cb93fab28a2b3fe79c700c7b6eeb
https://github.com/qemu/qemu/commit/e14cc941f109cb93fab28a2b3fe79c700c7b6eeb
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
We set this for qemu-system-aarch64, but failed to do so
for the strictly 32-bit emulation.
Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b6f8b358c2a2784433f51299279cd8e04fc981ac
https://github.com/qemu/qemu/commit/b6f8b358c2a2784433f51299279cd8e04fc981ac
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Split out aa32_max_features
Share the code to set AArch32 max features so that we no
longer have code drift between qemu{-system,}-{arm,aarch64}.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ef696cfbae6290d448ca0b36f9e41e3e0ec3d50d
https://github.com/qemu/qemu/commit/ef696cfbae6290d448ca0b36f9e41e3e0ec3d50d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Annotate arm_max_initfn with FEAT identifiers
Update the legacy feature names to the current names.
Provide feature names for id changes that were not marked.
Sort the field updates into increasing bitfield order.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b13c91c04b15f5216de9df3878da7dc4c1395979
https://github.com/qemu/qemu/commit/b13c91c04b15f5216de9df3878da7dc4c1395979
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Use field names for manipulating EL2 and EL3 modes
Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
during arm_cpu_realizefn.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 033a4f15336646c5dbc07587a7924d71c12a9525
https://github.com/qemu/qemu/commit/033a4f15336646c5dbc07587a7924d71c12a9525
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu.c
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Enable FEAT_Debugv8p2 for -cpu max
The only portion of FEAT_Debugv8p2 that is relevant to QEMU
is CONTEXTIDR_EL2, which is also conditionally implemented
with FEAT_VHE. The rest of the debug extension concerns the
External debug interface, which is outside the scope of QEMU.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8fc756b6be0d0de777b2092d324907ced7365543
https://github.com/qemu/qemu/commit/8fc756b6be0d0de777b2092d324907ced7365543
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Enable FEAT_Debugv8p4 for -cpu max
This extension concerns changes to the External Debug interface,
with Secure and Non-secure access to the debug registers, and all
of it is outside the scope of QEMU. Indicating support for this
is mandatory with FEAT_SEL2, which we do implement.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 58e93b48aa1b9f0e6de7e57f6f68b6dda7a8198a
https://github.com/qemu/qemu/commit/58e93b48aa1b9f0e6de7e57f6f68b6dda7a8198a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Add minimal RAS registers
Add only the system registers required to implement zero error
records. This means that all values for ERRSELR are out of range,
which means that it and all of the indexed error record registers
need not be implemented.
Add the EL2 registers required for injecting virtual SError.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: da3d8b13624246702f7b8b88e37ee525a2f39ad2
https://github.com/qemu/qemu/commit/da3d8b13624246702f7b8b88e37ee525a2f39ad2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Enable SCR and HCR bits for RAS
Enable writes to the TERR and TEA bits when RAS is enabled.
These bits are otherwise RES0.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3c29632feba7724be447b621f3527136e5c32744
https://github.com/qemu/qemu/commit/3c29632feba7724be447b621f3527136e5c32744
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/syndrome.h
Log Message:
-----------
target/arm: Implement virtual SError exceptions
Virtual SError exceptions are raised by setting HCR_EL2.VSE,
and are routed to EL1 just like other virtual exceptions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 13954587ea240c305d43cffd1adc8959146f43fd
https://github.com/qemu/qemu/commit/13954587ea240c305d43cffd1adc8959146f43fd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M target/arm/a32.decode
M target/arm/helper.h
M target/arm/op_helper.c
M target/arm/t32.decode
M target/arm/translate-a64.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Implement ESB instruction
Check for and defer any pending virtual SError.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e95c74c5e5522f6270092b788c3a96dfd8a93671
https://github.com/qemu/qemu/commit/e95c74c5e5522f6270092b788c3a96dfd8a93671
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Enable FEAT_RAS for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 880cd10e84775d3cca599bf872a9362b02322747
https://github.com/qemu/qemu/commit/880cd10e84775d3cca599bf872a9362b02322747
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Enable FEAT_IESB for -cpu max
This feature is AArch64 only, and applies to physical SErrors,
which QEMU does not implement, thus the feature is a nop.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 74b17e16695b93261b1c3ffb73031d574aba2b8e
https://github.com/qemu/qemu/commit/74b17e16695b93261b1c3ffb73031d574aba2b8e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Enable FEAT_CSV2 for -cpu max
This extension concerns branch speculation, which TCG does
not implement. Thus we can trivially enable this feature.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7cb1e61851332ea661d4ef6c1d958e3cdbffe2d8
https://github.com/qemu/qemu/commit/7cb1e61851332ea661d4ef6c1d958e3cdbffe2d8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
Log Message:
-----------
target/arm: Enable FEAT_CSV2_2 for -cpu max
There is no branch prediction in TCG, therefore there is no
need to actually include the context number into the predictor.
Therefore all we need to do is add the state for SCXTNUM_ELx.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3082b86b107ec7a26352bd18ada295ac1cc4faca
https://github.com/qemu/qemu/commit/3082b86b107ec7a26352bd18ada295ac1cc4faca
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Enable FEAT_CSV3 for -cpu max
This extension concerns cache speculation, which TCG does
not implement. Thus we can trivially enable this feature.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6d9650191ae301dc545dd9fd0727c57ec935503e
https://github.com/qemu/qemu/commit/6d9650191ae301dc545dd9fd0727c57ec935503e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Enable FEAT_DGH for -cpu max
This extension concerns not merging memory access, which TCG does
not implement. Thus we can trivially enable this feature.
Add a comment to handle_hint for the DGH instruction, but no code.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2f6283fc8e5219ce5f82ba60216ed5145a246470
https://github.com/qemu/qemu/commit/2f6283fc8e5219ce5f82ba60216ed5145a246470
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/virt.rst
M hw/arm/sbsa-ref.c
M hw/arm/virt.c
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Define cortex-a76
Enable the a76 for virt and sbsa board use.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5db6de806ab6f6db457300fc527f9b367fd97f21
https://github.com/qemu/qemu/commit/5db6de806ab6f6db457300fc527f9b367fd97f21
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M docs/system/arm/virt.rst
M hw/arm/sbsa-ref.c
M hw/arm/virt.c
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Define neoverse-n1
Enable the n1 for virt and sbsa board use.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-25-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 90ea2cceb286c66b8460725f5573d8a157e65bdf
https://github.com/qemu/qemu/commit/90ea2cceb286c66b8460725f5573d8a157e65bdf
Author: Leif Lindholm <quic_llindhol@quicinc.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/arm/sbsa-ref.c
Log Message:
-----------
hw/arm: add versioning to sbsa-ref machine DT
The sbsa-ref machine is continuously evolving. Some of the changes we
want to make in the near future, to align with real components (e.g.
the GIC-700), will break compatibility for existing firmware.
Introduce two new properties to the DT generated on machine generation:
- machine-version-major
To be incremented when a platform change makes the machine
incompatible with existing firmware.
- machine-version-minor
To be incremented when functionality is added to the machine
without causing incompatibility with existing firmware.
to be reset to 0 when machine-version-major is incremented.
This versioning scheme is *neither*:
- A QEMU versioned machine type; a given version of QEMU will emulate
a given version of the platform.
- A reflection of level of SBSA (now SystemReady SR) support provided.
The version will increment on guest-visible functional changes only,
akin to a revision ID register found on a physical platform.
These properties are both introduced with the value 0.
(Hence, a machine where the DT is lacking these nodes is equivalent
to version 0.0.)
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Radoslaw Biernacki <rad@semihalf.com>
Cc: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1dcf7001d4bae651129d46d5628b29e93a411d0b
https://github.com/qemu/qemu/commit/1dcf7001d4bae651129d46d5628b29e93a411d0b
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/core/machine-hmp-cmds.c
M hw/core/machine.c
M qapi/machine.json
Log Message:
-----------
qapi/machine.json: Add cluster-id
This adds cluster-id in CPU instance properties, which will be used
by arm/virt machine. Besides, the cluster-id is also verified or
dumped in various spots:
* hw/core/machine.c::machine_set_cpu_numa_node() to associate
CPU with its NUMA node.
* hw/core/machine.c::machine_numa_finish_cpu_init() to record
CPU slots with no NUMA mapping set.
* hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump
cluster-id.
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20220503140304.855514-2-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ac7199a2523ce2ccf8e685087a5d177eeca89b09
https://github.com/qemu/qemu/commit/ac7199a2523ce2ccf8e685087a5d177eeca89b09
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tests/qtest/numa-test.c
Log Message:
-----------
qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
The CPU topology isn't enabled on arm/virt machine yet, but we're
going to do it in next patch. After the CPU topology is enabled by
next patch, "thread-id=1" becomes invalid because the CPU core is
preferred on arm/virt machine. It means these two CPUs have 0/1
as their core IDs, but their thread IDs are all 0. It will trigger
test failure as the following message indicates:
[14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test ERROR
1.48s killed by signal 6 SIGABRT
>>>
G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \
QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon
\
QTEST_QEMU_BINARY=./qemu-system-aarch64
\
QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83
\
/home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k
――――――――――――――――――――――――――――――――――――――――――――――
stderr:
qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found
This fixes the issue by providing comprehensive SMP configurations
in aarch64_numa_cpu(). The SMP configurations aren't used before
the CPU topology is enabled in next patch.
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Message-id: 20220503140304.855514-3-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c9ec4cb5e4936f980889e717524e73896b0200ed
https://github.com/qemu/qemu/commit/c9ec4cb5e4936f980889e717524e73896b0200ed
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Consider SMP configuration in CPU topology
Currently, the SMP configuration isn't considered when the CPU
topology is populated. In this case, it's impossible to provide
the default CPU-to-NUMA mapping or association based on the socket
ID of the given CPU.
This takes account of SMP configuration when the CPU topology
is populated. The die ID for the given CPU isn't assigned since
it's not supported on arm/virt machine. Besides, the used SMP
configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted
to avoid testing failure
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20220503140304.855514-4-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e280ecb39bc1629f74ea5479d464fd1608dc8f76
https://github.com/qemu/qemu/commit/e280ecb39bc1629f74ea5479d464fd1608dc8f76
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M tests/qtest/numa-test.c
Log Message:
-----------
qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
In aarch64_numa_cpu(), the CPU and NUMA association is something
like below. Two threads in the same core/cluster/socket are
associated with two individual NUMA nodes, which is unreal as
Igor Mammedov mentioned. We don't expect the association to break
NUMA-to-socket boundary, which matches with the real world.
NUMA-node socket cluster core thread
------------------------------------------
0 0 0 0 0
1 0 0 0 1
This corrects the topology for CPUs and their association with
NUMA nodes. After this patch is applied, the CPU and NUMA
association becomes something like below, which looks real.
Besides, socket/cluster/core/thread IDs are all checked when
the NUMA node IDs are verified. It helps to check if the CPU
topology is properly populated or not.
NUMA-node socket cluster core thread
------------------------------------------
0 1 0 0 0
1 0 0 0 0
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Gavin Shan <gshan@redhat.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20220503140304.855514-5-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4c18bc192386dfbca530e7f550e0992df657818a
https://github.com/qemu/qemu/commit/4c18bc192386dfbca530e7f550e0992df657818a
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Fix CPU's default NUMA node ID
When CPU-to-NUMA association isn't explicitly provided by users,
the default one is given by mc->get_default_cpu_node_id(). However,
the CPU topology isn't fully considered in the default association
and this causes CPU topology broken warnings on booting Linux guest.
For example, the following warning messages are observed when the
Linux guest is booted with the following command lines.
/home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \
-accel kvm -machine virt,gic-version=host \
-cpu host \
-smp 6,sockets=2,cores=3,threads=1 \
-m 1024M,slots=16,maxmem=64G \
-object memory-backend-ram,id=mem0,size=128M \
-object memory-backend-ram,id=mem1,size=128M \
-object memory-backend-ram,id=mem2,size=128M \
-object memory-backend-ram,id=mem3,size=128M \
-object memory-backend-ram,id=mem4,size=128M \
-object memory-backend-ram,id=mem4,size=384M \
-numa node,nodeid=0,memdev=mem0 \
-numa node,nodeid=1,memdev=mem1 \
-numa node,nodeid=2,memdev=mem2 \
-numa node,nodeid=3,memdev=mem3 \
-numa node,nodeid=4,memdev=mem4 \
-numa node,nodeid=5,memdev=mem5
:
alternatives: patching kernel code
BUG: arch topology borken
the CLS domain not a subset of the MC domain
<the above error log repeats>
BUG: arch topology borken
the DIE domain not a subset of the NODE domain
With current implementation of mc->get_default_cpu_node_id(),
CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately.
That's incorrect because CPU#0/1/2 should be associated with same
NUMA node because they're seated in same socket.
This fixes the issue by considering the socket ID when the default
CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids().
With this applied, no more CPU topology broken warnings are seen
from the Linux guest. The 6 CPUs are associated with NODE#0/1, but
there are no CPUs associated with NODE#2/3/4/5.
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Message-id: 20220503140304.855514-6-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ae9141d4a3265553503bf07d3574b40f84615a34
https://github.com/qemu/qemu/commit/ae9141d4a3265553503bf07d3574b40f84615a34
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M hw/acpi/aml-build.c
Log Message:
-----------
hw/acpi/aml-build: Use existing CPU topology to build PPTT table
When the PPTT table is built, the CPU topology is re-calculated, but
it's unecessary because the CPU topology has been populated in
virt_possible_cpu_arch_ids() on arm/virt machine.
This reworks build_pptt() to avoid by reusing the existing IDs in
ms->possible_cpus. Currently, the only user of build_pptt() is
arm/virt machine.
Signed-off-by: Gavin Shan <gshan@redhat.com>
Tested-by: Yanan Wang <wangyanan55@huawei.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-id: 20220503140304.855514-7-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b0c3c60366ed43eb1569eb18c10df6eb993534c3
https://github.com/qemu/qemu/commit/b0c3c60366ed43eb1569eb18c10df6eb993534c3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-09 (Mon, 09 May 2022)
Changed paths:
M .mailmap
M MAINTAINERS
M docs/system/arm/emulation.rst
M docs/system/arm/virt.rst
M hw/acpi/aml-build.c
M hw/arm/sbsa-ref.c
M hw/arm/virt.c
M hw/core/machine-hmp-cmds.c
M hw/core/machine.c
M qapi/machine.json
M target/arm/a32.decode
M target/arm/cpregs.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/arm/helper.c
M target/arm/helper.h
M target/arm/internals.h
M target/arm/op_helper.c
M target/arm/syndrome.h
M target/arm/t32.decode
M target/arm/translate-a64.c
M target/arm/translate.c
M tests/qtest/numa-test.c
Log Message:
-----------
Merge tag 'pull-target-arm-20220509' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* MAINTAINERS/.mailmap: update email for Leif Lindholm
* hw/arm: add version information to sbsa-ref machine DT
* Enable new features for -cpu max:
FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only),
FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH
* Emulate Cortex-A76
* Emulate Neoverse-N1
* Fix the virt board default NUMA topology
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# gpg: Signature made Mon 09 May 2022 04:57:47 AM PDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
* tag 'pull-target-arm-20220509' of
https://git.linaro.org/people/pmaydell/qemu-arm: (32 commits)
hw/acpi/aml-build: Use existing CPU topology to build PPTT table
hw/arm/virt: Fix CPU's default NUMA node ID
qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
hw/arm/virt: Consider SMP configuration in CPU topology
qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
qapi/machine.json: Add cluster-id
hw/arm: add versioning to sbsa-ref machine DT
target/arm: Define neoverse-n1
target/arm: Define cortex-a76
target/arm: Enable FEAT_DGH for -cpu max
target/arm: Enable FEAT_CSV3 for -cpu max
target/arm: Enable FEAT_CSV2_2 for -cpu max
target/arm: Enable FEAT_CSV2 for -cpu max
target/arm: Enable FEAT_IESB for -cpu max
target/arm: Enable FEAT_RAS for -cpu max
target/arm: Implement ESB instruction
target/arm: Implement virtual SError exceptions
target/arm: Enable SCR and HCR bits for RAS
target/arm: Add minimal RAS registers
target/arm: Enable FEAT_Debugv8p4 for -cpu max
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/7e314198157b...b0c3c60366ed
- [Qemu-commits] [qemu/qemu] 14d5ad: MAINTAINERS/.mailmap: update email for Leif Lindholm,
Richard Henderson <=