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[Qemu-commits] [qemu/qemu] 0269a6: target/xtensa: fix missing tcg_temp_f
From: |
Richard Henderson |
Subject: |
[Qemu-commits] [qemu/qemu] 0269a6: target/xtensa: fix missing tcg_temp_free in gen_wi... |
Date: |
Fri, 06 May 2022 19:43:44 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 0269a6cf4ebff2eb6d8f893a5179be818efa90c2
https://github.com/qemu/qemu/commit/0269a6cf4ebff2eb6d8f893a5179be818efa90c2
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-06 (Fri, 06 May 2022)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: fix missing tcg_temp_free in gen_window_check
pc and w are allocated with tcg_const_i32 but not freed in
gen_window_check. Use tcg_constant_i32 for them both.
Fixes: 2db59a76c421 ("target-xtensa: record available window in TB flags")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 2b570a178a59338ad7512478c7dda06f07658506
https://github.com/qemu/qemu/commit/2b570a178a59338ad7512478c7dda06f07658506
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-06 (Fri, 06 May 2022)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: use tcg_contatnt_* for numeric literals
Replace tcg_const_* for numeric literals with tcg_constant_*.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: f99fbd125b916b484d2d92428e3cd8746cbef14c
https://github.com/qemu/qemu/commit/f99fbd125b916b484d2d92428e3cd8746cbef14c
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-06 (Fri, 06 May 2022)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: use tcg_constant_* for exceptions
Use tcg_contant_* for exception number, exception cause, debug cause
code and exception PC.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 4ee412df69907b5fc91489732b4013f23dc91083
https://github.com/qemu/qemu/commit/4ee412df69907b5fc91489732b4013f23dc91083
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-06 (Fri, 06 May 2022)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: use tcg_constant_* for TLB opcodes
dtlb is a boolean flag, use tcg_constant_* for it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: dad266a1e35f0b24f07e6e18c67a02edf347c0b3
https://github.com/qemu/qemu/commit/dad266a1e35f0b24f07e6e18c67a02edf347c0b3
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-06 (Fri, 06 May 2022)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: use tcg_constant_* for numbered special registers
Numbered special registers are small arrays of consecutive SRs. Use
tcg_constant_* for the SR index.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 867e354cbda0cac2d20a478ef39d01aa3bf67118
https://github.com/qemu/qemu/commit/867e354cbda0cac2d20a478ef39d01aa3bf67118
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-06 (Fri, 06 May 2022)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: use tcg_constant_* for FPU conversion opcodes
FPU conversion opcodes pass scale (range 0..15) and rounding mode to
their helpers. Use tcg_constant_* for them.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 6ade0ce972042a8e6d6a62373644cd1bd0f5ba4f
https://github.com/qemu/qemu/commit/6ade0ce972042a8e6d6a62373644cd1bd0f5ba4f
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-06 (Fri, 06 May 2022)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: use tcg_constant_* for remaining opcodes
- gen_jumpi passes target PC to the helper;
- gen_callw_slot uses callinc (1..3);
- gen_brcondi passes immediate field (less than 32 different possible
values) to the helper;
- disas_xtensa_insn passes PC to the helpers;
- translate_entry passes PC, stack register number (0..15) and stack
frame size to the helper;
- gen_check_exclusive passes PC and boolean flag to the helper;
- test_exceptions_retw passes PC to the helper;
- gen_check_atomctl passes PC to the helper;
- translate_ssai passes immediate shift amount (0..31) to the helper;
- gen_waiti passes next PC and an immediate (0..15) to the helper;
use tcg_constant_* for the constants listed above. Fold gen_waiti body
into the translate_waiti as it's the only user.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 8c48e36548a124dff8ad25b28f9cd2210dcdc407
https://github.com/qemu/qemu/commit/8c48e36548a124dff8ad25b28f9cd2210dcdc407
Author: Simon Safar <simon@simonsafar.com>
Date: 2022-05-06 (Fri, 06 May 2022)
Changed paths:
A target/xtensa/core-lx106.c
A target/xtensa/core-lx106/core-isa.h
A target/xtensa/core-lx106/gdb-config.c.inc
A target/xtensa/core-lx106/xtensa-modules.c.inc
M target/xtensa/cores.list
Log Message:
-----------
target/xtensa: import core lx106
This is the core used in e.g. ESP8266 chips. Importing them
using import_core.sh, with the required files sourced from
https://github.com/espressif/xtensa-overlays
core-lx106.c was generated by the script; the only change is removing
the reference to core-matmap.h which doesn't seem to be available.
Signed-off-by: Simon Safar <simon@simonsafar.com>
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com>
Message-Id: <20220423040835.29254-1-simon@simonsafar.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 9e377be1f042e8618c54ee786d1022caa0e2409d
https://github.com/qemu/qemu/commit/9e377be1f042e8618c54ee786d1022caa0e2409d
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-06 (Fri, 06 May 2022)
Changed paths:
M target/xtensa/cpu.c
M target/xtensa/cpu.h
M target/xtensa/op_helper.c
Log Message:
-----------
target/xtensa: add clock input to xtensa CPU
Create clock input for the xtensa CPU device and initialize its
frequency to the default core frequency specified in the config.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: c6f3f334d157ff6b9bdc4e1b9d9874234138836a
https://github.com/qemu/qemu/commit/c6f3f334d157ff6b9bdc4e1b9d9874234138836a
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-06 (Fri, 06 May 2022)
Changed paths:
M hw/xtensa/mx_pic.c
Log Message:
-----------
hw/xtensa: fix reset value of MIROUT register of MX PIC
MX PIC comes out of reset with IRQ routing registers set to 0, thus
not delivering any external IRQ to any connected CPU by default.
Fix the model to match the hardware.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: b9400b1fbaeb69af3e3052721fad79b2e46efc65
https://github.com/qemu/qemu/commit/b9400b1fbaeb69af3e3052721fad79b2e46efc65
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-06 (Fri, 06 May 2022)
Changed paths:
M tests/tcg/xtensa/crt.S
Log Message:
-----------
tests/tcg/xtensa: fix build for cores without windowed registers
Don't try to initialize windowbase/windowstart in crt.S if they don't
exist.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 8164f14bb98dce986b755af4b3dfee3eb99c95a1
https://github.com/qemu/qemu/commit/8164f14bb98dce986b755af4b3dfee3eb99c95a1
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-06 (Fri, 06 May 2022)
Changed paths:
M tests/tcg/xtensa/test_sr.S
Log Message:
-----------
tests/tcg/xtensa: restore vecbase SR after test
Writing garbage into the vecbase SR results in hang in the subsequent
tests that expect to raise an exception. Restore vecbase SR to its
reset value after the test.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 64407f6a9e0731c11a65119b7372dbe5b3a42eb9
https://github.com/qemu/qemu/commit/64407f6a9e0731c11a65119b7372dbe5b3a42eb9
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-06 (Fri, 06 May 2022)
Changed paths:
M tests/tcg/xtensa/test_break.S
Log Message:
-----------
tests/tcg/xtensa: fix watchpoint test
xtensa core may have only one set of DBREAKA/DBREAKC registers. Don't
hardcode register numbers in the test as 0 and 1, use macros that only
index valid DBREAK* registers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: e120c8335d1dfa9d194e3db8cc5195a6b47fb20c
https://github.com/qemu/qemu/commit/e120c8335d1dfa9d194e3db8cc5195a6b47fb20c
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-06 (Fri, 06 May 2022)
Changed paths:
M tests/tcg/xtensa/test_timer.S
Log Message:
-----------
tests/tcg/xtensa: remove dependency on the loop option
xtensa core may not have the loop option, but still have timers. Don't
use loop opcode in the timer test.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 703cebcfac65356aa2b19c0a5e4aa1b4be23a328
https://github.com/qemu/qemu/commit/703cebcfac65356aa2b19c0a5e4aa1b4be23a328
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-06 (Fri, 06 May 2022)
Changed paths:
M tests/tcg/xtensa/test_phys_mem.S
Log Message:
-----------
tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3
Autorefill tests in the phys_mem test suite are disabled for cores that
have spanning TLB way, i.e. for all MMUv3 cores. Instead of disabling it
invalidate TLB mappings for entries that conflict with the test.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: da60ecd6d8bf6551a0211714a5abb11711e0222c
https://github.com/qemu/qemu/commit/da60ecd6d8bf6551a0211714a5abb11711e0222c
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-06 (Fri, 06 May 2022)
Changed paths:
M tests/tcg/xtensa/test_mmu.S
Log Message:
-----------
tests/tcg/xtensa: enable mmu tests for MMUv3
MMU test suite is disabled for cores that have spanning TLB way, i.e.
for all MMUv3 cores. Instead of disabling it make testing region virtual
addresses explicit and invalidate TLB mappings for entries that conflict
with the test.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 4be4c5b826989bed67a16f6e5b931d8374589c08
https://github.com/qemu/qemu/commit/4be4c5b826989bed67a16f6e5b931d8374589c08
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-06 (Fri, 06 May 2022)
Changed paths:
M tests/tcg/xtensa/test_timer.S
Log Message:
-----------
tests/tcg/xtensa: fix vectors and checks in timer test
Timer test assumes that timer 0 IRQ has level 1 and other timers have
higher level IRQs. This assumption is not correct and the levels may be
arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and
using it for vector selection and by making the check for the timer
exception cause conditional.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 59491e97f89eaeee275f57fb6bb40f0152429fb3
https://github.com/qemu/qemu/commit/59491e97f89eaeee275f57fb6bb40f0152429fb3
Author: Max Filippov <jcmvbkbc@gmail.com>
Date: 2022-05-06 (Fri, 06 May 2022)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: implement cache test option opcodes
We don't model caches, so for l*ct opcodes return tags with all bits
(including Valid) set to 0. For all other opcodes don't do anything.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Commit: 11314643c35401b18c5374f4ec82ee7d3d5d2692
https://github.com/qemu/qemu/commit/11314643c35401b18c5374f4ec82ee7d3d5d2692
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-05-06 (Fri, 06 May 2022)
Changed paths:
M hw/xtensa/mx_pic.c
A target/xtensa/core-lx106.c
A target/xtensa/core-lx106/core-isa.h
A target/xtensa/core-lx106/gdb-config.c.inc
A target/xtensa/core-lx106/xtensa-modules.c.inc
M target/xtensa/cores.list
M target/xtensa/cpu.c
M target/xtensa/cpu.h
M target/xtensa/op_helper.c
M target/xtensa/translate.c
M tests/tcg/xtensa/crt.S
M tests/tcg/xtensa/test_break.S
M tests/tcg/xtensa/test_mmu.S
M tests/tcg/xtensa/test_phys_mem.S
M tests/tcg/xtensa/test_sr.S
M tests/tcg/xtensa/test_timer.S
Log Message:
-----------
Merge tag '20220506-xtensa-1' of https://github.com/OSLL/qemu-xtensa into
staging
target/xtensa updates for v7.1:
- expand test coverage to MMUv3, cores without windowed registers or
loop option;
- import lx106 core (used in the esp8266 IoT chips);
- use tcg_constant_* in the front end;
- add clock input to the xtensa CPU;
- fix reset state of the xtensa MX PIC;
- implement cache testing opcodes.
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# gpg: Signature made Fri 06 May 2022 05:40:26 PM CDT
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# gpg: issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg: aka "Max Filippov <max.filippov@cogentembedded.com>"
[undefined]
# gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [undefined]
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* tag '20220506-xtensa-1' of https://github.com/OSLL/qemu-xtensa:
target/xtensa: implement cache test option opcodes
tests/tcg/xtensa: fix vectors and checks in timer test
tests/tcg/xtensa: enable mmu tests for MMUv3
tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3
tests/tcg/xtensa: remove dependency on the loop option
tests/tcg/xtensa: fix watchpoint test
tests/tcg/xtensa: restore vecbase SR after test
tests/tcg/xtensa: fix build for cores without windowed registers
hw/xtensa: fix reset value of MIROUT register of MX PIC
target/xtensa: add clock input to xtensa CPU
target/xtensa: import core lx106
target/xtensa: use tcg_constant_* for remaining opcodes
target/xtensa: use tcg_constant_* for FPU conversion opcodes
target/xtensa: use tcg_constant_* for numbered special registers
target/xtensa: use tcg_constant_* for TLB opcodes
target/xtensa: use tcg_constant_* for exceptions
target/xtensa: use tcg_contatnt_* for numeric literals
target/xtensa: fix missing tcg_temp_free in gen_window_check
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/13220a46e27e...11314643c354
- [Qemu-commits] [qemu/qemu] 0269a6: target/xtensa: fix missing tcg_temp_free in gen_wi...,
Richard Henderson <=