[Qemu-commits] [qemu/qemu] dd7f19: hw: aspeed_scu: Add AST2600 apb

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[Qemu-commits] [qemu/qemu] dd7f19: hw: aspeed_scu: Add AST2600 apb_freq

From:	Richard Henderson
Subject:	[Qemu-commits] [qemu/qemu] dd7f19: hw: aspeed_scu: Add AST2600 apb_freq and hpll calc...
Date:	Tue, 03 May 2022 07:06:11 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: dd7f19a963ca4e1bbfb65b72d555efcc507a2d78
      
https://github.com/qemu/qemu/commit/dd7f19a963ca4e1bbfb65b72d555efcc507a2d78
  Author: Steven Lee <steven_lee@aspeedtech.com>
  Date:   2022-05-02 (Mon, 02 May 2022)

  Changed paths:
    M hw/misc/aspeed_scu.c
    M include/hw/misc/aspeed_scu.h

  Log Message:
  -----------
  hw: aspeed_scu: Add AST2600 apb_freq and hpll calculation function

AST2600's HPLL register offset and bit definition are different from
AST2500. Add a hpll calculation function and an apb frequency calculation
function based on SCU200 register description in ast2600v11.pdf.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: checkpatch fixes ]
Message-Id: <20220315075753.8591-2-steven_lee@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: bad23bb64447594e3027f4792dbe46edfc9204f6
      
https://github.com/qemu/qemu/commit/bad23bb64447594e3027f4792dbe46edfc9204f6
  Author: Steven Lee <steven_lee@aspeedtech.com>
  Date:   2022-05-02 (Mon, 02 May 2022)

  Changed paths:
    M hw/misc/aspeed_scu.c
    M include/hw/misc/aspeed_scu.h

  Log Message:
  -----------
  hw: aspeed_scu: Introduce clkin_25Mhz attribute

AST2600 clkin is always 25MHz, introduce clkin_25Mhz attribute
for aspeed_scu_get_clkin() to return the correct clkin for ast2600.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220315075753.8591-3-steven_lee@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: c2651cf45dd3ac5674bc720d2303668f0905507d
      
https://github.com/qemu/qemu/commit/c2651cf45dd3ac5674bc720d2303668f0905507d
  Author: Joel Stanley <joel@jms.id.au>
  Date:   2022-05-02 (Mon, 02 May 2022)

  Changed paths:
    M hw/misc/aspeed_sbc.c

  Log Message:
  -----------
  aspeed: sbc: Correct default reset values

In order to correctly report secure boot running firmware, these values
must be set. They are taken from a running machine when secure boot is
enabled.

We don't yet have documentation from ASPEED on what they mean. Set the
raw values for now, and in the future improve the model with properties
to set these on a per-machine basis.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220310052159.183975-1-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: fe31a2ecf02afda011df80e8a513a3c0eb9bc1e8
      
https://github.com/qemu/qemu/commit/fe31a2ecf02afda011df80e8a513a3c0eb9bc1e8
  Author: Joel Stanley <joel@jms.id.au>
  Date:   2022-05-02 (Mon, 02 May 2022)

  Changed paths:
    M hw/arm/aspeed_ast2600.c
    M include/hw/arm/aspeed_soc.h

  Log Message:
  -----------
  aspeed: Add eMMC Boot Controller stub

Guest code (u-boot) pokes at this on boot. No functionality is required
for guest code to work correctly, but it helps to document the region
being read from.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220318092211.723938-1-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 5c5e044583a5dcfc361ad94b6acf1942e54dcc6b
      
https://github.com/qemu/qemu/commit/5c5e044583a5dcfc361ad94b6acf1942e54dcc6b
  Author: Steven Lee <steven_lee@aspeedtech.com>
  Date:   2022-05-02 (Mon, 02 May 2022)

  Changed paths:
    M hw/adc/aspeed_adc.c
    M include/hw/adc/aspeed_adc.h

  Log Message:
  -----------
  aspeed/adc: Add AST1030 support

Per ast1030_v7.pdf, AST1030 ADC engine is identical to AST2600's ADC.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220401083850.15266-2-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 2850df6a81bcdc2e063dfdd56751ee2d11c58030
      
https://github.com/qemu/qemu/commit/2850df6a81bcdc2e063dfdd56751ee2d11c58030
  Author: Steven Lee <steven_lee@aspeedtech.com>
  Date:   2022-05-02 (Mon, 02 May 2022)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: Add AST1030 support

AST1030 spi controller's address decoding unit is 1MB that is identical
to ast2600, but fmc address decoding unit is 512kb.
Introduce seg_to_reg and reg_to_seg handlers for ast1030 fmc controller.
In addition, add ast1030 fmc, spi1, and spi2 class init handler.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220401083850.15266-3-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 018134abb26981f4720aad848d13171005da04dd
      
https://github.com/qemu/qemu/commit/018134abb26981f4720aad848d13171005da04dd
  Author: Steven Lee <steven_lee@aspeedtech.com>
  Date:   2022-05-02 (Mon, 02 May 2022)

  Changed paths:
    M hw/watchdog/wdt_aspeed.c
    M include/hw/watchdog/wdt_aspeed.h

  Log Message:
  -----------
  aspeed/wdt: Fix ast2500/ast2600 default reload value

Per ast2500_2520_datasheet_v1.8 and ast2600v11.pdf, the default value of
WDT00 and WDT04 is 0x014FB180 for ast2500/ast2600.
Add default_status and default_reload_value attributes for storing
counter status and reload value as they are different from ast2400.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220401083850.15266-4-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: e259e01ecbe524171ddc8e6bd1dddc400a3f5c84
      
https://github.com/qemu/qemu/commit/e259e01ecbe524171ddc8e6bd1dddc400a3f5c84
  Author: Steven Lee <steven_lee@aspeedtech.com>
  Date:   2022-05-02 (Mon, 02 May 2022)

  Changed paths:
    M hw/watchdog/wdt_aspeed.c
    M include/hw/watchdog/wdt_aspeed.h

  Log Message:
  -----------
  aspeed/wdt: Add AST1030 support

AST1030 wdt controller is similiar to AST2600's wdt, but it has extra
registers.
Introduce ast1030 object class and increse the number of regs(offset) of
ast1030 model.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220401083850.15266-5-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: c5b89a4f476fb77e5a302c18b76098190a3d549d
      
https://github.com/qemu/qemu/commit/c5b89a4f476fb77e5a302c18b76098190a3d549d
  Author: Steven Lee <steven_lee@aspeedtech.com>
  Date:   2022-05-02 (Mon, 02 May 2022)

  Changed paths:
    M hw/timer/aspeed_timer.c
    M include/hw/timer/aspeed_timer.h

  Log Message:
  -----------
  aspeed/timer: Add AST1030 support

ast1030 tmc(timer controller) is identical to ast2600 tmc.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220401083850.15266-6-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: fa541a60dd4ed863ce500e00a43041528ae4f301
      
https://github.com/qemu/qemu/commit/fa541a60dd4ed863ce500e00a43041528ae4f301
  Author: Steven Lee <steven_lee@aspeedtech.com>
  Date:   2022-05-02 (Mon, 02 May 2022)

  Changed paths:
    M hw/misc/aspeed_scu.c
    M include/hw/misc/aspeed_scu.h

  Log Message:
  -----------
  aspeed/scu: Add AST1030 support

Per ast1030_v07.pdf, AST1030 SOC doesn't have SCU300, the pclk divider
selection is defined in SCU310[11:8].
Add a get_apb_freq function and a class init handler for ast1030.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220401083850.15266-7-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 356b230ed13889e09d087a96498887de695df17e
      
https://github.com/qemu/qemu/commit/356b230ed13889e09d087a96498887de695df17e
  Author: Steven Lee <steven_lee@aspeedtech.com>
  Date:   2022-05-02 (Mon, 02 May 2022)

  Changed paths:
    A hw/arm/aspeed_ast10x0.c
    M hw/arm/meson.build
    M include/hw/arm/aspeed_soc.h

  Log Message:
  -----------
  aspeed/soc : Add AST1030 support

The embedded core of AST1030 SoC is ARM Coretex M4.
It is hard to be integrated in the common Aspeed Soc framework.
We introduce a new ast1030 class with instance_init and realize
handlers.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: rename aspeed_ast10xx.c to aspeed_ast10x0.c to match zephyr ]
Message-Id: <20220401083850.15266-8-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 66c895b8affc89f250ad69cbec4091e1e255f4ec
      
https://github.com/qemu/qemu/commit/66c895b8affc89f250ad69cbec4091e1e255f4ec
  Author: Jamin Lin <jamin_lin@aspeedtech.com>
  Date:   2022-05-02 (Mon, 02 May 2022)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: Add an AST1030 eval board

The image should be supplied with ELF binary.
$ qemu-system-arm -M ast1030-evb -kernel zephyr.elf -nographic

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220401083850.15266-9-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 438eff633a0cd0c6ca18b30ce31b727ff49c09a1
      
https://github.com/qemu/qemu/commit/438eff633a0cd0c6ca18b30ce31b727ff49c09a1
  Author: Jamin Lin <jamin_lin@aspeedtech.com>
  Date:   2022-05-02 (Mon, 02 May 2022)

  Changed paths:
    A tests/avocado/machine_aspeed.py

  Log Message:
  -----------
  test/avocado/machine_aspeed.py: Add ast1030 test case

Add test case to test "ast1030-evb" machine with zephyr os

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220401083850.15266-10-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 753abfc4a2c9bd9c73d028fb5dca24c8ef63f5ed
      
https://github.com/qemu/qemu/commit/753abfc4a2c9bd9c73d028fb5dca24c8ef63f5ed
  Author: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
  Date:   2022-05-02 (Mon, 02 May 2022)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  hw/arm/aspeed: fix AST2500/AST2600 EVB fmc model

Current fmc model of AST2500 EVB and AST2600 EVB can't emulate quad
mode properly so fix them using equivalent mx25l25635e and mx66u51235f
respectively.

These default settings still can be overridden using the 'fmc-model'
command line option.

Reported-by: Graeme Gregory <quic_ggregory@quicinc.com>
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220402184427.4010304-1-quic_jaehyoo@quicinc.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 1877069c9d2ad4d08d72aa41edff156c0dc65bf0
      
https://github.com/qemu/qemu/commit/1877069c9d2ad4d08d72aa41edff156c0dc65bf0
  Author: Steven Lee <steven_lee@aspeedtech.com>
  Date:   2022-05-02 (Mon, 02 May 2022)

  Changed paths:
    M hw/misc/aspeed_hace.c
    M include/hw/misc/aspeed_hace.h

  Log Message:
  -----------
  aspeed/hace: Support HMAC Key Buffer register.

Support HACE28: Hash HMAC Key Buffer Base Address Register.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220426021120.28255-2-steven_lee@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 5cd7d8564a8b563da724b9e6264c967f0a091afa
      
https://github.com/qemu/qemu/commit/5cd7d8564a8b563da724b9e6264c967f0a091afa
  Author: Steven Lee <steven_lee@aspeedtech.com>
  Date:   2022-05-02 (Mon, 02 May 2022)

  Changed paths:
    M hw/misc/aspeed_hace.c
    M include/hw/misc/aspeed_hace.h

  Log Message:
  -----------
  aspeed/hace: Support AST2600 HACE

The aspeed ast2600 accumulative mode is described in datasheet
ast2600v10.pdf section 25.6.4:
 1. Allocating and initiating accumulative hash digest write buffer
    with initial state.
    * Since QEMU crypto/hash api doesn't provide the API to set initial
      state of hash library, and the initial state is already set by
      crypto library (gcrypt/glib/...), so skip this step.
 2. Calculating accumulative hash digest.
    (a) When receiving the last accumulative data, software need to add
        padding message at the end of the accumulative data. Padding
        message described in specific of MD5, SHA-1, SHA224, SHA256,
        SHA512, SHA512/224, SHA512/256.
        * Since the crypto library (gcrypt/glib) already pad the
          padding message internally.
        * This patch is to remove the padding message which fed byguest
          machine driver.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220426021120.28255-3-steven_lee@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: e0c371a0d23bf2f6740af72cb19eeac53e1623c7
      
https://github.com/qemu/qemu/commit/e0c371a0d23bf2f6740af72cb19eeac53e1623c7
  Author: Steven Lee <steven_lee@aspeedtech.com>
  Date:   2022-05-02 (Mon, 02 May 2022)

  Changed paths:
    M tests/qtest/aspeed_hace-test.c

  Log Message:
  -----------
  tests/qtest: Add test for Aspeed HACE accumulative mode

This add two addition test cases for accumulative mode under sg enabled.

The input vector was manually craft with "abc" + bit 1 + padding zeros + L.
The padding length depends on algorithm, i.e. SHA512 (1024 bit),
SHA256 (512 bit).

The result was calculated by command line sha512sum/sha256sum utilities
without padding, i.e. only "abc" ascii text.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
[ clg: checkpatch fixes ]
Message-Id: <20220426021120.28255-4-steven_lee@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 2ec063788efd3a545c5aa2999159c9303bb476f3
      
https://github.com/qemu/qemu/commit/2ec063788efd3a545c5aa2999159c9303bb476f3
  Author: Peter Delevoryas <pdel@fb.com>
  Date:   2022-05-02 (Mon, 02 May 2022)

  Changed paths:
    M hw/gpio/aspeed_gpio.c
    A tests/qtest/aspeed_gpio-test.c
    M tests/qtest/meson.build

  Log Message:
  -----------
  hw/gpio/aspeed_gpio: Fix QOM pin property

I was setting gpioV4-7 to "1110" using the QOM pin property handler and
noticed that lowering gpioV7 was inadvertently lowering gpioV4-6 too.

    (qemu) qom-set /machine/soc/gpio gpioV4 true
    (qemu) qom-set /machine/soc/gpio gpioV5 true
    (qemu) qom-set /machine/soc/gpio gpioV6 true
    (qemu) qom-get /machine/soc/gpio gpioV4
    true
    (qemu) qom-set /machine/soc/gpio gpioV7 false
    (qemu) qom-get /machine/soc/gpio gpioV4
    false

An expression in aspeed_gpio_set_pin_level was using a logical NOT
operator instead of a bitwise NOT operator:

    value &= !pin_mask;

The original author probably intended to make a bitwise NOT expression
"~", but mistakenly used a logical NOT operator "!" instead. Some
programming languages like Rust use "!" for both purposes.

Fixes: 4b7f956862dc ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and
AST2500")
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20220502080827.244815-1-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: e056c52233910ef156e6d790ce41b33cd838bad6
      
https://github.com/qemu/qemu/commit/e056c52233910ef156e6d790ce41b33cd838bad6
  Author: Steven Lee <steven_lee@aspeedtech.com>
  Date:   2022-05-03 (Tue, 03 May 2022)

  Changed paths:
    M hw/misc/aspeed_hace.c
    M include/hw/misc/aspeed_hace.h

  Log Message:
  -----------
  aspeed/hace: Support AST1030 HACE

Per ast1030_v7.pdf, AST1030 HACE engine is identical to AST2600's HACE
engine.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 5f14cfe187e2fc3c71f4536b2021b8118d224239
      
https://github.com/qemu/qemu/commit/5f14cfe187e2fc3c71f4536b2021b8118d224239
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-05-03 (Tue, 03 May 2022)

  Changed paths:
    M hw/adc/aspeed_adc.c
    M hw/arm/aspeed.c
    A hw/arm/aspeed_ast10x0.c
    M hw/arm/aspeed_ast2600.c
    M hw/arm/meson.build
    M hw/gpio/aspeed_gpio.c
    M hw/misc/aspeed_hace.c
    M hw/misc/aspeed_sbc.c
    M hw/misc/aspeed_scu.c
    M hw/ssi/aspeed_smc.c
    M hw/timer/aspeed_timer.c
    M hw/watchdog/wdt_aspeed.c
    M include/hw/adc/aspeed_adc.h
    M include/hw/arm/aspeed_soc.h
    M include/hw/misc/aspeed_hace.h
    M include/hw/misc/aspeed_scu.h
    M include/hw/timer/aspeed_timer.h
    M include/hw/watchdog/wdt_aspeed.h
    A tests/avocado/machine_aspeed.py
    A tests/qtest/aspeed_gpio-test.c
    M tests/qtest/aspeed_hace-test.c
    M tests/qtest/meson.build

  Log Message:
  -----------
  Merge tag 'pull-aspeed-20220503' of https://github.com/legoater/qemu into 
staging

aspeed queue:

* New AST1030 SoC and eval board
* Accumulative mode support for HACE controller
* GPIO fix and unit test
* Clock modeling adjustments for the AST2600
* Dummy eMMC Boot Controller model
* Change of AST2500 EVB and AST2600 EVB flash model (for quad IO)

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# =+hIh
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 02 May 2022 10:50:39 PM PDT
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-aspeed-20220503' of https://github.com/legoater/qemu:
  aspeed/hace: Support AST1030 HACE
  hw/gpio/aspeed_gpio: Fix QOM pin property
  tests/qtest: Add test for Aspeed HACE accumulative mode
  aspeed/hace: Support AST2600 HACE
  aspeed/hace: Support HMAC Key Buffer register.
  hw/arm/aspeed: fix AST2500/AST2600 EVB fmc model
  test/avocado/machine_aspeed.py: Add ast1030 test case
  aspeed: Add an AST1030 eval board
  aspeed/soc : Add AST1030 support
  aspeed/scu: Add AST1030 support
  aspeed/timer: Add AST1030 support
  aspeed/wdt: Add AST1030 support
  aspeed/wdt: Fix ast2500/ast2600 default reload value
  aspeed/smc: Add AST1030 support
  aspeed/adc: Add AST1030 support
  aspeed: Add eMMC Boot Controller stub
  aspeed: sbc: Correct default reset values
  hw: aspeed_scu: Introduce clkin_25Mhz attribute
  hw: aspeed_scu: Add AST2600 apb_freq and hpll calculation function

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/f5643914a9e8...5f14cfe187e2
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