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[Qemu-commits] [qemu/qemu] 6d3b9c: hw/riscv: spike: Add '/chosen/stdout-
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 6d3b9c: hw/riscv: spike: Add '/chosen/stdout-path' in devi... |
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Date: |
Fri, 29 Apr 2022 14:52:02 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 6d3b9c024ce4e115f4dc24706d4c45bdc04ba093
https://github.com/qemu/qemu/commit/6d3b9c024ce4e115f4dc24706d4c45bdc04ba093
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M hw/riscv/spike.c
Log Message:
-----------
hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally
At present the adding '/chosen/stdout-path' property in device tree
is determined by whether a kernel command line is provided, which is
wrong. It should be added unconditionally.
Fixes: 8d8897accb1c ("hw/riscv: spike: Allow using binary firmware as bios")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421055629.1177285-1-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 58303fc0be8ccd7557414a920d4c666fce36eb41
https://github.com/qemu/qemu/commit/58303fc0be8ccd7557414a920d4c666fce36eb41
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M hw/riscv/microchip_pfsoc.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: Don't add empty bootargs to device tree
Commit 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
tried to avoid adding *NULL* bootargs to device tree, but unfortunately
the changes were entirely useless, due to MachineState::kernel_cmdline
can't be NULL at all as the default value is given as an empty string.
(see hw/core/machine.c::machine_initfn()).
Note the wording of *NULL* bootargs is wrong. It can't be NULL otherwise
a segfault had already been observed by dereferencing the NULL pointer.
It should be worded as *empty" bootargs.
Fixes: 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421055629.1177285-2-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9951ba948a359c595f6216dcf399cb6232426e98
https://github.com/qemu/qemu/commit/9951ba948a359c595f6216dcf399cb6232426e98
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
Allow user to set core's marchid, mvendorid, mipid CSRs through
-cpu command line option.
The default values of marchid and mipid are built with QEMU's version
numbers.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220422040436.2233-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: eef82872be58f4e0362319bfe4348bbe4ad71c5b
https://github.com/qemu/qemu/commit/eef82872be58f4e0362319bfe4348bbe4ad71c5b
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: rvk: add cfg properties for zbk* and zk*
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d8e81e3c18231e4dbab562f53e3e6cf7ad77735f
https://github.com/qemu/qemu/commit/d8e81e3c18231e4dbab562f53e3e6cf7ad77735f
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M target/riscv/bitmanip_helper.c
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: rvk: add support for zbkb extension
- reuse partial instructions of zbb extension, update extension check for them
- add brev8, pack, packh, packw, unzip, zip instructions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220423023510.30794-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5cc69ceb68c2bd00b3f62d7d65ec669a507b4f30
https://github.com/qemu/qemu/commit/5cc69ceb68c2bd00b3f62d7d65ec669a507b4f30
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
Log Message:
-----------
target/riscv: rvk: add support for zbkc extension
- reuse partial instructions of zbc extension, update extension check for them
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220423023510.30794-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0496389680a1d5e27e81fc0153b956a763defe4b
https://github.com/qemu/qemu/commit/0496389680a1d5e27e81fc0153b956a763defe4b
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M target/riscv/bitmanip_helper.c
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
Log Message:
-----------
target/riscv: rvk: add support for zbkx extension
- add xperm4 and xperm8 instructions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c29da5a7fe6a5d3e1719ce9a831076df2eff52d5
https://github.com/qemu/qemu/commit/c29da5a7fe6a5d3e1719ce9a831076df2eff52d5
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M crypto/meson.build
A crypto/sm4.c
A include/crypto/sm4.h
M target/arm/crypto_helper.c
Log Message:
-----------
crypto: move sm4_sbox from target/arm
- share it between target/arm and target/riscv
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220423023510.30794-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 68d19b58f42d2493a3ff1c6dfe02a99f9d4ecfb5
https://github.com/qemu/qemu/commit/68d19b58f42d2493a3ff1c6dfe02a99f9d4ecfb5
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
A target/riscv/crypto_helper.c
M target/riscv/helper.h
M target/riscv/insn32.decode
A target/riscv/insn_trans/trans_rvk.c.inc
M target/riscv/meson.build
M target/riscv/translate.c
Log Message:
-----------
target/riscv: rvk: add support for zknd/zkne extension in RV32
- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9e33e1753bc3a7c7cab9a293b242036344c43a02
https://github.com/qemu/qemu/commit/9e33e1753bc3a7c7cab9a293b242036344c43a02
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M target/riscv/crypto_helper.c
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvk.c.inc
Log Message:
-----------
target/riscv: rvk: add support for zkne/zknd extension in RV64
- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i
instructions
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-8-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 387e5d92713b7d85f1d077466ac0a21d7f985858
https://github.com/qemu/qemu/commit/387e5d92713b7d85f1d077466ac0a21d7f985858
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvk.c.inc
Log Message:
-----------
target/riscv: rvk: add support for sha256 related instructions in zknh
extension
- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-9-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e9a7ef5d5e3f6595d03495d8fe8f72f4086ba3c4
https://github.com/qemu/qemu/commit/e9a7ef5d5e3f6595d03495d8fe8f72f4086ba3c4
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvk.c.inc
Log Message:
-----------
target/riscv: rvk: add support for sha512 related instructions for RV32 in
zknh extension
- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and
sha512sig1h instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-10-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1f7f7b5ede6bcc68ff0587f085abb65018d32ebc
https://github.com/qemu/qemu/commit/1f7f7b5ede6bcc68ff0587f085abb65018d32ebc
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvk.c.inc
Log Message:
-----------
target/riscv: rvk: add support for sha512 related instructions for RV64 in
zknh extension
- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-11-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0976083d1be23d72b9a4857f6d8c3d86b5f11efa
https://github.com/qemu/qemu/commit/0976083d1be23d72b9a4857f6d8c3d86b5f11efa
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M target/riscv/crypto_helper.c
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvk.c.inc
Log Message:
-----------
target/riscv: rvk: add support for zksed/zksh extension
- add sm3p0, sm3p1, sm4ed and sm4ks instructions
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-12-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 77442380ecbe3b3c092c2a48dbfe8286336e7e78
https://github.com/qemu/qemu/commit/77442380ecbe3b3c092c2a48dbfe8286336e7e78
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M target/riscv/cpu_bits.h
M target/riscv/csr.c
M target/riscv/op_helper.c
M target/riscv/pmp.h
Log Message:
-----------
target/riscv: rvk: add CSR support for Zkr
- add SEED CSR which must be accessed with a read-write instruction:
A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI
with uimm=0 will raise an illegal instruction exception.
- add USEED, SSEED fields for MSECCFG CSR
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-13-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5748c886b19a9b467b667220a35c44d909a60bc3
https://github.com/qemu/qemu/commit/5748c886b19a9b467b667220a35c44d909a60bc3
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M disas/riscv.c
Log Message:
-----------
disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-14-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: cf7ed971ae6f4e3683340b890a2db664a88cd896
https://github.com/qemu/qemu/commit/cf7ed971ae6f4e3683340b890a2db664a88cd896
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: rvk: expose zbk* and zk* properties
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-15-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 457a86a0ebe6a5544aa4f2ee7a2af5c125b9fb1b
https://github.com/qemu/qemu/commit/457a86a0ebe6a5544aa4f2ee7a2af5c125b9fb1b
Author: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M target/riscv/monitor.c
Log Message:
-----------
target/riscv: Fix incorrect PTE merge in walk_pte
Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
case, walk_pte will erroneously merge them.
Enforce the split up, by tracking the virtual base address.
Let's say we have the mapping:
0x81200000 -> 0x89623000 (4K)
0x8120f000 -> 0x89624000 (4K)
Before, walk_pte would have shown:
vaddr paddr size attr
---------------- ---------------- ---------------- -------
0000000081200000 0000000089623000 0000000000002000 rwxu-ad
as it only checks for subsequent paddrs. With this patch, it becomes:
vaddr paddr size attr
---------------- ---------------- ---------------- -------
0000000081200000 0000000089623000 0000000000001000 rwxu-ad
000000008120f000 0000000089624000 0000000000001000 rwxu-ad
Signed-off-by: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423215907.673663-1-ralf.ramsauer@oth-regensburg.de>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a62c2c155ccf4f08e5b7f54bc18e822baf41ab05
https://github.com/qemu/qemu/commit/a62c2c155ccf4f08e5b7f54bc18e822baf41ab05
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: add scalar crypto related extenstion strings to isa_string
- add zbk* and zk* strings to isa_edata_arr
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220426095204.24142-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1c20d3ff6004b600336c52cbef9f134fad3ccd94
https://github.com/qemu/qemu/commit/1c20d3ff6004b600336c52cbef9f134fad3ccd94
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M hw/riscv/virt.c
M include/hw/riscv/virt.h
Log Message:
-----------
hw/riscv: virt: Add a machine done notifier
Move the binary and device tree loading code to the machine done
notifier. This allows us to prepare for editing the device tree as part
of the notifier.
This is based on similar code in the ARM virt machine.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220427234146.1130752-2-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d24a7bc24ec9201357f554f590d247582360e3cf
https://github.com/qemu/qemu/commit/d24a7bc24ec9201357f554f590d247582360e3cf
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M hw/arm/meson.build
R hw/arm/sysbus-fdt.c
M hw/arm/virt.c
M hw/arm/xlnx-versal-virt.c
M hw/core/meson.build
A hw/core/sysbus-fdt.c
R include/hw/arm/sysbus-fdt.h
A include/hw/core/sysbus-fdt.h
Log Message:
-----------
hw/core: Move the ARM sysbus-fdt to core
The ARM virt machine currently uses sysbus-fdt to create device tree
entries for dynamically created MMIO devices.
The RISC-V virt machine can also benefit from this, so move the code to
the core directory.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220427234146.1130752-3-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1832b7cb3f6450c2c98e5181c7688b8e753fe7fd
https://github.com/qemu/qemu/commit/1832b7cb3f6450c2c98e5181c7688b8e753fe7fd
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M hw/riscv/Kconfig
M hw/riscv/virt.c
M include/hw/riscv/virt.h
Log Message:
-----------
hw/riscv: virt: Create a platform bus
Create a platform bus to allow dynamic devices to be connected. This is
based on the ARM implementation.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220427234146.1130752-4-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3029fab643094d4972eeeed46e427194b5359087
https://github.com/qemu/qemu/commit/3029fab643094d4972eeeed46e427194b5359087
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: virt: Add support for generating platform FDT entries
Similar to the ARM virt machine add support for adding device tree
entries for dynamically created devices.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-Id: <20220427234146.1130752-5-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 58d5a5a78cdbd77062708edaa6416e0817d39fe4
https://github.com/qemu/qemu/commit/58d5a5a78cdbd77062708edaa6416e0817d39fe4
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: virt: Add device plug support
Add support for plugging in devices, this was tested with the TPM
device.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220427234146.1130752-6-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 325b7c4e7582c229d28c47123c3b986ed948eb84
https://github.com/qemu/qemu/commit/325b7c4e7582c229d28c47123c3b986ed948eb84
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M docs/system/riscv/virt.rst
M hw/riscv/Kconfig
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: Enable TPM backends
Imply the TPM sysbus devices. This allows users to add TPM devices to
the RISC-V virt board.
This was tested by first creating an emulated TPM device:
swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
--ctrl type=unixio,path=swtpm-sock
Then launching QEMU with:
-chardev socket,id=chrtpm,path=swtpm-sock \
-tpmdev emulator,id=tpm0,chardev=chrtpm \
-device tpm-tis-device,tpmdev=tpm0
The TPM device can be seen in the memory tree and the generated device
tree.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/942
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220427234146.1130752-7-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 731340813fdb4cb8339edb8630e3f923b7d987ec
https://github.com/qemu/qemu/commit/731340813fdb4cb8339edb8630e3f923b7d987ec
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-04-29 (Fri, 29 Apr 2022)
Changed paths:
M crypto/meson.build
A crypto/sm4.c
M disas/riscv.c
M docs/system/riscv/virt.rst
M hw/arm/meson.build
R hw/arm/sysbus-fdt.c
M hw/arm/virt.c
M hw/arm/xlnx-versal-virt.c
M hw/core/meson.build
A hw/core/sysbus-fdt.c
M hw/riscv/Kconfig
M hw/riscv/microchip_pfsoc.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
A include/crypto/sm4.h
R include/hw/arm/sysbus-fdt.h
A include/hw/core/sysbus-fdt.h
M include/hw/riscv/virt.h
M target/arm/crypto_helper.c
M target/riscv/bitmanip_helper.c
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
A target/riscv/crypto_helper.c
M target/riscv/csr.c
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
A target/riscv/insn_trans/trans_rvk.c.inc
M target/riscv/meson.build
M target/riscv/monitor.c
M target/riscv/op_helper.c
M target/riscv/pmp.h
M target/riscv/translate.c
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20220429' of github.com:alistair23/qemu into
staging
Second RISC-V PR for QEMU 7.1
* Improve device tree generation
* Support configuarable marchid, mvendorid, mipid CSR values
* Add support for the Zbkb, Zbkc, Zbkx, Zknd/Zkne, Zknh, Zksed/Zksh and Zkr
extensions
* Fix incorrect PTE merge in walk_pte
* Add TPM support to the virt board
# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmJraeUACgkQIeENKd+X
# cFRLjgf9GFmxPhOC8cb7wN6xsiJIiVmmcTGHKfUgFTAIR2KLOEm2fo28YNrgewok
# Hi7FBHLhYKEivz70GFVg7q6oJlqhYx8fL4AB0sodTetIcJGQPQgz8zN7ZD8utnzA
# d6n7ZruyW5IuUqCBUcsHNqBHxoYanR88rr6YpxU+nSz0WALYRgQliXm5zqK1rwNc
# v8HpLHyN7JUmAQmJ1U6Uc6IFi/cFn9e/Hs/uRMevKov2nCTxeeAq5G2r8JGKpx35
# VRid91dcWbGiRY1xHWqnl/0WZxl8Jp4av1e5NDbXfwYPvwiI2fza5KFasp2S38yR
# VvnUcI+p73qclCF7LkfL9c//xQT1iA==
# =Xkoz
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 28 Apr 2022 09:30:29 PM PDT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>"
[undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* tag 'pull-riscv-to-apply-20220429' of github.com:alistair23/qemu: (25 commits)
hw/riscv: Enable TPM backends
hw/riscv: virt: Add device plug support
hw/riscv: virt: Add support for generating platform FDT entries
hw/riscv: virt: Create a platform bus
hw/core: Move the ARM sysbus-fdt to core
hw/riscv: virt: Add a machine done notifier
target/riscv: add scalar crypto related extenstion strings to isa_string
target/riscv: Fix incorrect PTE merge in walk_pte
target/riscv: rvk: expose zbk* and zk* properties
disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
target/riscv: rvk: add CSR support for Zkr
target/riscv: rvk: add support for zksed/zksh extension
target/riscv: rvk: add support for sha512 related instructions for RV64 in
zknh extension
target/riscv: rvk: add support for sha512 related instructions for RV32 in
zknh extension
target/riscv: rvk: add support for sha256 related instructions in zknh
extension
target/riscv: rvk: add support for zkne/zknd extension in RV64
target/riscv: rvk: add support for zknd/zkne extension in RV32
crypto: move sm4_sbox from target/arm
target/riscv: rvk: add support for zbkx extension
target/riscv: rvk: add support for zbkc extension
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/f22833602095...731340813fdb