[Qemu-commits] [qemu/qemu] 2a1990: hw/intc/arm_gicv3

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[Qemu-commits] [qemu/qemu] 2a1990: hw/intc/arm_gicv3_its: Add missing bl

From:	Richard Henderson
Subject:	[Qemu-commits] [qemu/qemu] 2a1990: hw/intc/arm_gicv3_its: Add missing blank line
Date:	Fri, 22 Apr 2022 04:01:15 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 2a1990369719e3e202188236483bab0208a87d24
      
https://github.com/qemu/qemu/commit/2a1990369719e3e202188236483bab0208a87d24
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_its.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Add missing blank line

In commit b6f96009acc we split do_process_its_cmd() from
process_its_cmd(), but forgot the usual blank line between function
definitions.  Add it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-2-peter.maydell@linaro.org


  Commit: 89ac9d0cba3c5d86c4a19ba1cd139ad25d041826
      
https://github.com/qemu/qemu/commit/89ac9d0cba3c5d86c4a19ba1cd139ad25d041826
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_common.c

  Log Message:
  -----------
  hw/intc/arm_gicv3: Sanity-check num-cpu property

In the GICv3 code we implicitly rely on there being at least one CPU
and thus at least one redistributor and CPU interface.  Sanity-check
that the property the board code sets is not zero.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-3-peter.maydell@linaro.org


  Commit: 671927a1165fa1a1dc6ebb413f58615f62105d6d
      
https://github.com/qemu/qemu/commit/671927a1165fa1a1dc6ebb413f58615f62105d6d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_common.c

  Log Message:
  -----------
  hw/intc/arm_gicv3: Insist that redist region capacity matches CPU count

Boards using the GICv3 need to configure it with both the total
number of CPUs and also the sizes of all the memory regions which
contain redistributors (one redistributor per CPU).  At the moment
the GICv3 checks that the number of CPUs specified is not too many to
fit in the defined redistributor regions, but in fact the code
assumes that the two match exactly.  For instance when we set the
GICR_TYPER.Last bit on the final redistributor in each region, we
assume that we don't need to consider the possibility of a region
being only half full of redistributors or even completely empty.  We
also assume in gicv3_redist_read() and gicv3_redist_write() that we
can calculate the CPU index from the offset within the MemoryRegion
and that this will always be in range.

Fortunately all the board code sets the redistributor region sizes to
exactly match the CPU count, so this isn't a visible bug.  We could
in theory make the GIC code handle non-full redistributor regions, or
have it automatically reduce the provided region sizes to match the
CPU count, but the simplest thing is just to strengthen the error
check and insist that the CPU count and redistributor region size
settings match exactly, since all the board code does that anyway.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-4-peter.maydell@linaro.org


  Commit: 50a3a309e12789e28a3c4e260348ed7305c28b99
      
https://github.com/qemu/qemu/commit/50a3a309e12789e28a3c4e260348ed7305c28b99
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_dist.c
    M hw/intc/arm_gicv3_its.c
    M hw/intc/arm_gicv3_redist.c
    M hw/intc/gicv3_internal.h

  Log Message:
  -----------
  hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers

We use the common function gicv3_idreg() to supply the CoreSight ID
register values for the GICv3 for the copies of these ID registers in
the distributor, redistributor and ITS register frames.  This isn't
quite correct, because while most of the register values are the
same, the PIDR0 value should vary to indicate which of these three
frames it is.  (You can see this and also the correct values of these
PIDR0 registers by looking at the GIC-600 or GIC-700 TRMs, for
example.)

Make gicv3_idreg() take an extra argument for the PIDR0 value.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-5-peter.maydell@linaro.org


  Commit: 9acd2d3373b899b342bfaa84107c613a75b65735
      
https://github.com/qemu/qemu/commit/9acd2d3373b899b342bfaa84107c613a75b65735
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2

In a GICv3, it is impossible for the GIC to deliver a VIRQ or VFIQ to
the CPU unless the CPU has EL2, because VIRQ and VFIQ are only
configurable via EL2-only system registers.  Moreover, in our
implementation we were only calculating and updating the state of the
VIRQ and VFIQ lines in gicv3_cpuif_virt_irq_fiq_update() when those
EL2 system registers changed.  We were therefore able to assert in
arm_cpu_set_irq() that we didn't see a VIRQ or VFIQ line update if
EL2 wasn't present.

This assumption no longer holds with GICv4:
 * even if the CPU does not have EL2 the guest is able to cause the
   GIC to deliver a virtual LPI by programming the ITS (which is a
   silly thing for it to do, but possible)
 * because we now need to recalculate the state of the VIRQ and VFIQ
   lines in more cases than just "some EL2 GIC sysreg was written",
   we will see calls to arm_cpu_set_irq() for "VIRQ is 0, VFIQ is 0"
   even if the guest is not using the virtual LPI parts of the ITS

Remove the assertions, and instead simply ignore the state of the
VIRQ and VFIQ lines if the CPU does not have EL2.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-6-peter.maydell@linaro.org


  Commit: c3c9a09073d8549b431e813ba86bd6f01c0401c3
      
https://github.com/qemu/qemu/commit/c3c9a09073d8549b431e813ba86bd6f01c0401c3
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_its.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Factor out "is intid a valid LPI ID?"

In process_mapti() we check interrupt IDs to see whether they are
in the valid LPI range. Factor this out into its own utility
function, as we're going to want it elsewhere too for GICv4.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-7-peter.maydell@linaro.org


  Commit: 50d84584d3c77e3a9104826a53a691318aeaf038
      
https://github.com/qemu/qemu/commit/50d84584d3c77e3a9104826a53a691318aeaf038
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_its.c
    M hw/intc/gicv3_internal.h
    M include/hw/intc/arm_gicv3_its_common.h

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4

The GICv4 defines a new in-guest-memory table for the ITS: this is
the vPE table.  Implement the new GITS_BASER2 register which the
guest uses to tell the ITS where the vPE table is located, including
the decode of the register fields into the TableDesc structure which
we do for the GITS_BASER<n> when the guest enables the ITS.

We guard provision of the new register with the its_feature_virtual()
function, which does a check of the GITS_TYPER.Virtual bit which
indicates presence of ITS support for virtual LPIs.  Since this bit
is currently always zero, GICv4-specific features will not be
accessible to the guest yet.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-8-peter.maydell@linaro.org


  Commit: 9de53de60cb8638e9c2e02b25ec4445791672aeb
      
https://github.com/qemu/qemu/commit/9de53de60cb8638e9c2e02b25ec4445791672aeb
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_its.c
    M hw/intc/gicv3_internal.h
    M hw/intc/trace-events

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTI

Implement the GICv4 VMAPI and VMAPTI commands. These write
an interrupt translation table entry that maps (DeviceID,EventID)
to (vPEID,vINTID,doorbell). The only difference between VMAPI
and VMAPTI is that VMAPI assumes vINTID == EventID rather than
both being specified in the command packet.

(This code won't be reachable until we allow the GIC version to be
set to 4.  Support for reading this new virtual-interrupt DTE and
handling it correctly will be implemented in a later commit.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-9-peter.maydell@linaro.org


  Commit: 0cdf7a5dc8d4e49b19d91219dc3e3cc65d6d8c60
      
https://github.com/qemu/qemu/commit/0cdf7a5dc8d4e49b19d91219dc3e3cc65d6d8c60
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_its.c
    M hw/intc/gicv3_internal.h
    M hw/intc/trace-events

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Implement VMAPP

Implement the GICv4 VMAPP command, which writes an entry to the vPE
table.

For GICv4.1 this command has extra fields in the command packet
and additional behaviour. We define the 4.1-only fields with the
FIELD macro, but only implement the GICv4.0 version of the command.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-10-peter.maydell@linaro.org


  Commit: 93f4fdcd4d98c0de8e056e08016bce7d71a91100
      
https://github.com/qemu/qemu/commit/93f4fdcd4d98c0de8e056e08016bce7d71a91100
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_its.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Distinguish success and error cases of CMD_CONTINUE

In the ItsCmdResult enum, we currently distinguish only CMD_STALL
(failure, stall processing of the command queue) and CMD_CONTINUE
(keep processing the queue), and we use the latter both for "there
was a parameter error, go on to the next command" and "the command
succeeded, go on to the next command".  Sometimes we would like to
distinguish those two cases, so add CMD_CONTINUE_OK to the enum to
represent the success situation, and use it in the relevant places.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-11-peter.maydell@linaro.org


  Commit: f0175135e74bc979573f170e83abfc536aed03de
      
https://github.com/qemu/qemu/commit/f0175135e74bc979573f170e83abfc536aed03de
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_its.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid"

The operation of finding an interrupt table entry given a (DeviceID,
EventID) pair is necessary in multiple different ITS commands.  The
process requires first using the DeviceID as an index into the device
table to find the DTE, and then useng the EventID as an index into
the interrupt table specified by that DTE to find the ITE.  We also
need to handle all the possible error cases: indexes out of range,
table memory not readable, table entries not valid.

Factor this out into a separate lookup_ite() function which we
can then call from the places where we were previously open-coding
this sequence. We'll also need this for some of the new GICv4.0
commands.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-12-peter.maydell@linaro.org


  Commit: c411db7bf75d0a2ecd7249533c74babf2af51afe
      
https://github.com/qemu/qemu/commit/c411db7bf75d0a2ecd7249533c74babf2af51afe
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_its.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Factor out CTE lookup sequence

Factor out the sequence of looking up a CTE from an ICID including
the validity and error checks.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-13-peter.maydell@linaro.org


  Commit: 2d692e2b314e212664e9ce72787ce0ecea615c61
      
https://github.com/qemu/qemu/commit/2d692e2b314e212664e9ce72787ce0ecea615c61
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_its.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Split out process_its_cmd() physical interrupt code

Split the part of process_its_cmd() which is specific to physical
interrupts into its own function.  This is the part which starts by
taking the ICID and looking it up in the collection table.  The
handling of virtual interrupts is significantly different (involving
a lookup in the vPE table) so structuring the code with one
sub-function for the physical interrupt case and one for the virtual
interrupt case will be clearer than putting both cases in one large
function.

The code for handling the "remove mapping from ITE" for the DISCARD
command remains in process_its_cmd() because it is common to both
virtual and physical interrupts.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-14-peter.maydell@linaro.org


  Commit: 469cf23bf857412e45bb480eabd8f0cd890b41b1
      
https://github.com/qemu/qemu/commit/469cf23bf857412e45bb480eabd8f0cd890b41b1
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_its.c
    M hw/intc/arm_gicv3_redist.c
    M hw/intc/gicv3_internal.h
    M hw/intc/trace-events

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Handle virtual interrupts in process_its_cmd()

For GICv4, interrupt table entries read by process_its_cmd() may
indicate virtual LPIs which are to be directly injected into a VM.
Implement the ITS side of the code for handling this.  This is
similar to the existing handling of physical LPIs, but instead of
looking up a collection ID in a collection table, we look up a vPEID
in a vPE table.  As with the physical LPIs, we leave the rest of the
work to code in the redistributor device.

The redistributor half will be implemented in a later commit;
for now we just provide a stub function which does nothing.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-15-peter.maydell@linaro.org


  Commit: 89cc276011c892d3f93dac5ef5d14a5fa2c94266
      
https://github.com/qemu/qemu/commit/89cc276011c892d3f93dac5ef5d14a5fa2c94266
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_common.c
    M hw/intc/arm_gicv3_its.c
    M hw/intc/arm_gicv3_its_kvm.c
    M hw/intc/gicv3_internal.h
    M include/hw/intc/arm_gicv3_common.h

  Log Message:
  -----------
  hw/intc/arm_gicv3: Keep pointers to every connected ITS

The GICv4 ITS VMOVP command's semantics require it to perform the
operation on every ITS connected to the same GIC that the ITS that
received the command is attached to.  This means that the GIC object
needs to keep a pointer to every ITS that is connected to it
(previously it was sufficient for the ITS to have a pointer to its
GIC).

Add a glib ptrarray to the GICv3 object which holds pointers to every
connected ITS, and make the ITS add itself to the array for the GIC
it is connected to when it is realized.

Note that currently all QEMU machine types with an ITS have exactly
one ITS in the system, so typically the length of this ptrarray will
be 1.  Multiple ITSes are typically used to improve performance on
real hardware, so we wouldn't need to have more than one unless we
were modelling a real machine type that had multile ITSes.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-16-peter.maydell@linaro.org


  Commit: d66d6bfe4f43704197d6577b3a26f1168e6b0423
      
https://github.com/qemu/qemu/commit/d66d6bfe4f43704197d6577b3a26f1168e6b0423
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_its.c
    M hw/intc/gicv3_internal.h
    M hw/intc/trace-events

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Implement VMOVP

Implement the GICv4 VMOVP command, which updates an entry in the vPE
table to change its rdbase field. This command is unique in the ITS
command set because its effects must be propagated to all the other
ITSes connected to the same GIC as the ITS which executes the VMOVP
command.

The GICv4 spec allows two implementation choices for handling the
propagation to other ITSes:
 * If GITS_TYPER.VMOVP is 1, the guest only needs to issue the command
   on one ITS, and the implementation handles the propagation to
   all ITSes
 * If GITS_TYPER.VMOVP is 0, the guest must issue the command on
   every ITS, and arrange for the ITSes to synchronize the updates
   with each other by setting ITSList and Sequence Number fields
   in the command packets

We choose the GITS_TYPER.VMOVP = 1 approach, and synchronously
execute the update on every ITS.

For GICv4.1 this command has extra fields in the command packet and
additional behaviour.  We define the 4.1-only fields with the FIELD
macro, but only implement the GICv4.0 version of the command.

Note that we don't update the reported GITS_TYPER value here;
we'll do that later in a commit which updates all the reported
feature bit and ID register values for GICv4.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-17-peter.maydell@linaro.org


  Commit: b61823b5ea7c4b6b4189e0bf1ec0166eac8d3697
      
https://github.com/qemu/qemu/commit/b61823b5ea7c4b6b4189e0bf1ec0166eac8d3697
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_its.c
    M hw/intc/gicv3_internal.h
    M hw/intc/trace-events

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Implement VSYNC

The VSYNC command forces the ITS to synchronize all outstanding ITS
operations for the specified vPEID, so that subsequent writes to
GITS_TRANSLATER honour them.  The QEMU implementation is always in
sync, so for us this is a nop, like the existing SYNC command.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-18-peter.maydell@linaro.org


  Commit: c492a3ef61f9b0855bc4436a79d77c1d027c68da
      
https://github.com/qemu/qemu/commit/c492a3ef61f9b0855bc4436a79d77c1d027c68da
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_its.c
    M hw/intc/arm_gicv3_redist.c
    M hw/intc/gicv3_internal.h
    M hw/intc/trace-events

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Implement INV command properly

We were previously implementing INV (like INVALL) to just blow away
cached highest-priority-pending-LPI information on all connected
redistributors.  For GICv4.0, this isn't going to be sufficient,
because the LPI we are invalidating cached information for might be
either physical or virtual, and the required action is different for
those two cases.  So we need to do the full process of looking up the
ITE from the devid and eventid.  This also means we can do the error
checks that the spec lists for this command.

Split out INV handling into a process_inv() function like our other
command-processing functions.  For the moment, stick to handling only
physical LPIs; we will add the vLPI parts later.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-19-peter.maydell@linaro.org


  Commit: d1872d2ff3ed1c6a8d67f815219a43d182c826e6
      
https://github.com/qemu/qemu/commit/d1872d2ff3ed1c6a8d67f815219a43d182c826e6
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_its.c
    M hw/intc/arm_gicv3_redist.c
    M hw/intc/gicv3_internal.h

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Implement INV for virtual interrupts

Implement the ITS side of the handling of the INV command for
virtual interrupts; as usual this calls into a redistributor
function which we leave as a stub to fill in later.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-20-peter.maydell@linaro.org


  Commit: 864bcac12d292555e94689d08c207212aee52cde
      
https://github.com/qemu/qemu/commit/864bcac12d292555e94689d08c207212aee52cde
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_its.c
    M hw/intc/arm_gicv3_redist.c
    M hw/intc/gicv3_internal.h
    M hw/intc/trace-events

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Implement VMOVI

Implement the GICv4 VMOVI command, which moves the pending state
of a virtual interrupt from one redistributor to another. As with
MOVI, we handle the "parse and validate command arguments and
table lookups" part in the ITS source file, and pass the final
results to a function in the redistributor which will do the
actual operation. As with the "make a VLPI pending" change,
for the moment we leave that redistributor function as a stub,
to be implemented in a later commit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-21-peter.maydell@linaro.org


  Commit: 5c1383b0b371691afc67db9e88f32dc95d7ef8e2
      
https://github.com/qemu/qemu/commit/5c1383b0b371691afc67db9e88f32dc95d7ef8e2
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_its.c
    M hw/intc/arm_gicv3_redist.c
    M hw/intc/gicv3_internal.h
    M hw/intc/trace-events

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Implement VINVALL

The VINVALL command should cause any cached information in the
ITS or redistributor for the specified vCPU to be dropped or
otherwise made consistent with the in-memory LPI configuration
tables.

Here we implement the command and table parsing, leaving the
redistributor part as a stub for the moment, as usual.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-22-peter.maydell@linaro.org


  Commit: 6dafbf059061e9e3897210ab3b53cfbe799d458e
      
https://github.com/qemu/qemu/commit/6dafbf059061e9e3897210ab3b53cfbe799d458e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_common.c
    M hw/intc/arm_gicv3_redist.c
    M hw/intc/gicv3_internal.h
    M include/hw/intc/arm_gicv3_common.h

  Log Message:
  -----------
  hw/intc/arm_gicv3: Implement GICv4's new redistributor frame

The GICv4 extends the redistributor register map -- where GICv3
had two 64KB frames per CPU, GICv4 has four frames. Add support
for the extra frame by using a new gicv3_redist_size() function
in the places in the GIC implementation which currently use
a fixed constant size for the redistributor register block.
(Until we implement the extra registers they will RAZ/WI.)

Any board that wants to use a GICv4 will need to also adjust
to handle the different sized redistributor register block;
that will be done separately.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-23-peter.maydell@linaro.org


  Commit: f553c43a271b70a3330fdad9e7f3e7f95af75624
      
https://github.com/qemu/qemu/commit/f553c43a271b70a3330fdad9e7f3e7f95af75624
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_common.c
    M hw/intc/arm_gicv3_redist.c
    M hw/intc/gicv3_internal.h
    M include/hw/intc/arm_gicv3_common.h

  Log Message:
  -----------
  hw/intc/arm_gicv3: Implement new GICv4 redistributor registers

Implement the new GICv4 redistributor registers: GICR_VPROPBASER
and GICR_VPENDBASER; for the moment we implement these as simple
reads-as-written stubs, together with the necessary migration
and reset handling.

We don't put ID-register checks on the handling of these registers,
because they are all in the only-in-v4 extra register frames, so
they're not accessible in a GICv3.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-24-peter.maydell@linaro.org


  Commit: 81198f9a4a685e4bb2c968ec880ac3b7f87b57b3
      
https://github.com/qemu/qemu/commit/81198f9a4a685e4bb2c968ec880ac3b7f87b57b3
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_cpuif.c
    M hw/intc/gicv3_internal.h
    M hw/intc/trace-events

  Log Message:
  -----------
  hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from 
gicv3_cpuif_virt_update()

The function gicv3_cpuif_virt_update() currently sets all of vIRQ,
vFIQ and the maintenance interrupt.  This implies that it has to be
used quite carefully -- as the comment notes, setting the maintenance
interrupt will typically cause the GIC code to be re-entered
recursively.  For handling vLPIs, we need the redistributor to be
able to tell the cpuif to update the vIRQ and vFIQ lines when the
highest priority pending vLPI changes.  Since that change can't cause
the maintenance interrupt state to change, we can pull the "update
vIRQ/vFIQ" parts of gicv3_cpuif_virt_update() out into a separate
function, which the redistributor can then call without having to
worry about the reentrancy issue.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-25-peter.maydell@linaro.org


  Commit: d17b6d752f60e710348e81b48b86fe5f2e93b5f0
      
https://github.com/qemu/qemu/commit/d17b6d752f60e710348e81b48b86fe5f2e93b5f0
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_common.c
    M hw/intc/arm_gicv3_cpuif.c
    M hw/intc/arm_gicv3_redist.c
    M hw/intc/gicv3_internal.h
    M hw/intc/trace-events
    M include/hw/intc/arm_gicv3_common.h

  Log Message:
  -----------
  hw/intc/arm_gicv3_cpuif: Support vLPIs

The CPU interface changes to support vLPIs are fairly minor:
in the parts of the code that currently look at the list registers
to determine the highest priority pending virtual interrupt, we
must also look at the highest priority pending vLPI. To do this
we change hppvi_index() to check the vLPI and return a special-case
value if that is the right virtual interrupt to take. The callsites
(which handle HPPIR and IAR registers and the "raise vIRQ and vFIQ
lines" code) then have to handle this special-case value.

This commit includes two interfaces with the as-yet-unwritten
redistributor code:
 * the new GICv3CPUState::hppvlpi will be set by the redistributor
   (in the same way as the existing hpplpi does for physical LPIs)
 * when the CPU interface acknowledges a vLPI it needs to set it
   to non-pending; the new gicv3_redist_vlpi_pending() function
   (which matches the existing gicv3_redist_lpi_pending() used
   for physical LPIs) is a stub that will be filled in later

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-26-peter.maydell@linaro.org


  Commit: 5b47847a61e238c33e3fce560fe8a56b6f82d3eb
      
https://github.com/qemu/qemu/commit/5b47847a61e238c33e3fce560fe8a56b6f82d3eb
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_cpuif.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarily

The maintenance interrupt state depends only on:
 * ICH_HCR_EL2
 * ICH_LR<n>_EL2
 * ICH_VMCR_EL2 fields VENG0 and VENG1

Now we have a separate function that updates only the vIRQ and vFIQ
lines, use that in places that only change state that affects vIRQ
and vFIQ but not the maintenance interrupt.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-27-peter.maydell@linaro.org


  Commit: 9f59d2ead6e378c3a8598f40be01339caa5c7db0
      
https://github.com/qemu/qemu/commit/9f59d2ead6e378c3a8598f40be01339caa5c7db0
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_redist.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_redist: Factor out "update hpplpi for one LPI" logic

Currently the functions which update the highest priority pending LPI
information by looking at the LPI Pending and Configuration tables
are hard-coded to use the physical LPI tables addressed by
GICR_PENDBASER and GICR_PROPBASER.  To support virtual LPIs we will
need to do essentially the same job, but looking at the current
virtual LPI Pending and Configuration tables and updating cs->hppvlpi
instead of cs->hpplpi.

Factor out the common part of the gicv3_redist_check_lpi_priority()
function into a new update_for_one_lpi() function, which updates
a PendingIrq struct if the specified LPI is higher priority than
what is currently recorded there.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-28-peter.maydell@linaro.org


  Commit: 73645c778fb2562ae5d69eaefe532938176a1f64
      
https://github.com/qemu/qemu/commit/73645c778fb2562ae5d69eaefe532938176a1f64
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_redist.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logic

Factor out the common part of gicv3_redist_update_lpi_only() into
a new function update_for_all_lpis(), which does a full rescan
of an LPI Pending table and sets the specified PendingIrq struct
with the highest priority pending enabled LPI it finds.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-29-peter.maydell@linaro.org


  Commit: e4a61ac7f8d14e6b1a2556a81b0a1a9214f68996
      
https://github.com/qemu/qemu/commit/e4a61ac7f8d14e6b1a2556a81b0a1a9214f68996
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_redist.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writes

The guest uses GICR_VPENDBASER to tell the redistributor when it is
scheduling or descheduling a vCPU.  When it writes and changes the
VALID bit from 0 to 1, it is scheduling a vCPU, and we must update
our view of the current highest priority pending vLPI from the new
Pending and Configuration tables.  When it writes and changes the
VALID bit from 1 to 0, it is descheduling, which means that there is
no longer a highest priority pending vLPI.

The specification allows the implementation to use part of the vLPI
Pending table as an IMPDEF area where it can cache information when a
vCPU is descheduled, so that it can avoid having to do a full rescan
of the tables when the vCPU is scheduled again.  For now, we don't
take advantage of this, and simply do a complete rescan.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-30-peter.maydell@linaro.org


  Commit: 8f8932f30c902f8a7f43896e545d859300715dda
      
https://github.com/qemu/qemu/commit/8f8932f30c902f8a7f43896e545d859300715dda
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_redist.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" code

Factor out the code which sets a single bit in an LPI pending table.
We're going to need this for handling vLPI tables, not just the
physical LPI table.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-31-peter.maydell@linaro.org


  Commit: 4ea46597778550d162bae1278889cd31df855b17
      
https://github.com/qemu/qemu/commit/4ea46597778550d162bae1278889cd31df855b17
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_redist.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi()

Implement the function gicv3_redist_process_vlpi(), which was left as
just a stub earlier.  This function deals with being handed a VLPI by
the ITS.  It must set the bit in the pending table.  If the vCPU is
currently resident we must recalculate the highest priority pending
vLPI; otherwise we may need to ring a "doorbell" interrupt to let the
hypervisor know it might want to reschedule the vCPU.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-32-peter.maydell@linaro.org


  Commit: 85491ff8364ffbee8500d883553f7029a326f619
      
https://github.com/qemu/qemu/commit/85491ff8364ffbee8500d883553f7029a326f619
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_redist.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending()

Implement the function gicv3_redist_vlpi_pending(), which was
previously left as a stub.  This is the function that is called by
the CPU interface when it changes the state of a vLPI.  It's similar
to gicv3_redist_process_vlpi(), but we know that the vCPU is
definitely resident on the redistributor and the irq is in range, so
it is a bit simpler.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-33-peter.maydell@linaro.org


  Commit: e1ed8d6757b3e9f9c97d4af5e652b983e9d0a74c
      
https://github.com/qemu/qemu/commit/e1ed8d6757b3e9f9c97d4af5e652b983e9d0a74c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_redist.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handling

We can use our new set_pending_table_bit() utility function
in gicv3_redist_mov_lpi() to clear the bit in the source
pending table, rather than doing the "load, clear bit, store"
ourselves.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-34-peter.maydell@linaro.org


  Commit: cc8aa9821388f6f0dcacbe693fe520691600a10d
      
https://github.com/qemu/qemu/commit/cc8aa9821388f6f0dcacbe693fe520691600a10d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_redist.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi()

Implement the gicv3_redist_mov_vlpi() function (previously left as a
stub).  This function handles the work of a VMOVI command: it marks
the vLPI not-pending on the source and pending on the destination.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-35-peter.maydell@linaro.org


  Commit: 63edfbac027e1d12ceecd92983d4318ba54afcb1
      
https://github.com/qemu/qemu/commit/63edfbac027e1d12ceecd92983d4318ba54afcb1
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_redist.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall()

Implement the gicv3_redist_vinvall() function (previously left as a
stub).  This function handles the work of a VINVALL command: it must
invalidate any cached information associated with a specific vCPU.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-36-peter.maydell@linaro.org


  Commit: cb4095d2397aba51bc3267434bd523337447be4e
      
https://github.com/qemu/qemu/commit/cb4095d2397aba51bc3267434bd523337447be4e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_redist.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi()

Implement the function gicv3_redist_inv_vlpi(), which was previously
left as a stub.  This is the function that does the work of the INV
command for a virtual interrupt.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-37-peter.maydell@linaro.org


  Commit: ade21c6ceea0d63586ce392b4b5527800a0a8a97
      
https://github.com/qemu/qemu/commit/ade21c6ceea0d63586ce392b4b5527800a0a8a97
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_common.c
    M hw/intc/arm_gicv3_cpuif.c
    M hw/intc/arm_gicv3_dist.c
    M hw/intc/arm_gicv3_its.c
    M hw/intc/arm_gicv3_redist.c
    M hw/intc/gicv3_internal.h

  Log Message:
  -----------
  hw/intc/arm_gicv3: Update ID and feature registers for GICv4

Update the various GIC ID and feature registers for GICv4:
 * PIDR2 [7:4] is the GIC architecture revision
 * GICD_TYPER.DVIS is 1 to indicate direct vLPI injection support
 * GICR_TYPER.VLPIS is 1 to indicate redistributor support for vLPIs
 * GITS_TYPER.VIRTUAL is 1 to indicate vLPI support
 * GITS_TYPER.VMOVP is 1 to indicate that our VMOVP implementation
   handles cross-ITS synchronization for the guest
 * ICH_VTR_EL2.nV4 is 0 to indicate direct vLPI injection support

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-38-peter.maydell@linaro.org


  Commit: 526b33e42c6a48b41af0ddfb16256bfba20be041
      
https://github.com/qemu/qemu/commit/526b33e42c6a48b41af0ddfb16256bfba20be041
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/intc/arm_gicv3_common.c
    M hw/intc/arm_gicv3_kvm.c

  Log Message:
  -----------
  hw/intc/arm_gicv3: Allow 'revision' property to be set to 4

Now that we have implemented all the GICv4 requirements, relax the
error-checking on the GIC object's 'revision' property to allow a TCG
GIC to be a GICv4, whilst still constraining the KVM GIC to GICv3.

Our 'revision' property doesn't consider the possibility of wanting
to specify the minor version of the GIC -- for instance there is a
GICv3.1 which adds support for extended SPI and PPI ranges, among
other things, and also GICv4.1.  But since the QOM property is
internal to QEMU, not user-facing, we can cross that bridge when we
come to it. Within the GIC implementation itself code generally
checks against the appropriate ID register feature bits, and the
only use of s->revision is for setting those ID register bits.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-39-peter.maydell@linaro.org


  Commit: 7e3c2877dd5fc6a710160c3d583c0e1ff1b2f6d1
      
https://github.com/qemu/qemu/commit/7e3c2877dd5fc6a710160c3d583c0e1ff1b2f6d1
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Use VIRT_GIC_VERSION_* enum values in create_gic()

Everywhere we need to check which GIC version we're using, we look at
vms->gic_version and use the VIRT_GIC_VERSION_* enum values, except
in create_gic(), which copies vms->gic_version into a local 'int'
variable and makes direct comparisons against values 2 and 3.

For consistency, change this function to check the GIC version
the same way we do elsewhere. This includes not implicitly relying
on the enumeration type values happening to match the integer
'revision' values the GIC device object wants.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-40-peter.maydell@linaro.org


  Commit: e741a808fb1d641025c0a210c274ceda5d1c9f0c
      
https://github.com/qemu/qemu/commit/e741a808fb1d641025c0a210c274ceda5d1c9f0c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/arm/virt.c
    M include/hw/arm/virt.h

  Log Message:
  -----------
  hw/arm/virt: Abstract out calculation of redistributor region capacity

In several places in virt.c we calculate the number of redistributors that
fit in a region of our memory map, which is the size of the region
divided by the size of a single redistributor frame. For GICv4, the
redistributor frame is a different size from that for GICv3. Abstract
out the calculation of redistributor region capacity so that we have
one place we need to change to handle GICv4 rather than several.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-41-peter.maydell@linaro.org


  Commit: ad4659af7e86e93ba6c1b42aeee4681a870e2c94
      
https://github.com/qemu/qemu/commit/ad4659af7e86e93ba6c1b42aeee4681a870e2c94
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M docs/system/arm/virt.rst
    M hw/arm/virt.c
    M include/hw/arm/virt.h

  Log Message:
  -----------
  hw/arm/virt: Support TCG GICv4

Add support for the TCG GICv4 to the virt board. For the board,
the GICv4 is very similar to the GICv3, with the only difference
being the size of the redistributor frame. The changes here are thus:
 * calculating virt_redist_capacity correctly for GICv4
 * changing various places which were "if GICv3" to be "if not GICv2"
 * the commandline option handling

Note that using GICv4 reduces the maximum possible number of CPUs on
the virt board from 512 to 317, because we can now only fit half as
many redistributors into the redistributor regions we have defined.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-42-peter.maydell@linaro.org


  Commit: ad6a80b53d761df56bbacea5a6ffcf311ae9e17e
      
https://github.com/qemu/qemu/commit/ad6a80b53d761df56bbacea5a6ffcf311ae9e17e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Update ISAR fields for ARMv8.8

Update isar fields per ARM DDI0487 H.a.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 53c6b9208a222660febe842a0684163b9331c5a4
      
https://github.com/qemu/qemu/commit/53c6b9208a222660febe842a0684163b9331c5a4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Update SCR_EL3 bits to ARMv8.8

Update SCR_EL3 fields per ARM DDI0487 H.a.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c6874fb753870c16d9400fe5ae53e604b75f0430
      
https://github.com/qemu/qemu/commit/c6874fb753870c16d9400fe5ae53e604b75f0430
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Update SCTLR bits to ARMv9.2

Update SCTLR_ELx fields per ARM DDI0487 H.a.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 1c416e9e89d85bc4d7bdf791dff6d349709b0c42
      
https://github.com/qemu/qemu/commit/1c416e9e89d85bc4d7bdf791dff6d349709b0c42
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Change DisasContext.aarch64 to bool

Bool is a more appropriate type for this value.
Move the member down in the struct to keep the
bool type members together and remove a hole.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: feac9ed97042c14a1ce5664a2382e5330e396ae2
      
https://github.com/qemu/qemu/commit/feac9ed97042c14a1ce5664a2382e5330e396ae2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper-a64.c
    M target/arm/helper.c
    M target/arm/hvf/hvf.c

  Log Message:
  -----------
  target/arm: Change CPUArchState.aarch64 to bool

Bool is a more appropriate type for this value.
Adjust the assignments to use true/false.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f350479701ad619d98e2999404cd246f38b2000f
      
https://github.com/qemu/qemu/commit/f350479701ad619d98e2999404cd246f38b2000f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M target/arm/translate-a32.h
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Extend store_cpu_offset to take field size

Currently we assume all fields are 32-bit.
Prepare for fields of a single byte, using sizeof_field().

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: use sizeof_field() instead of raw sizeof()]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a84e8e20fa7928b4b99f23584a4d35935e626992
      
https://github.com/qemu/qemu/commit/a84e8e20fa7928b4b99f23584a4d35935e626992
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Change DisasContext.thumb to bool

Bool is a more appropriate type for this value.
Move the member down in the struct to keep the
bool type members together and remove a hole.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 97d46d80e7d61ed8166fe89132572602997288d4
      
https://github.com/qemu/qemu/commit/97d46d80e7d61ed8166fe89132572602997288d4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M linux-user/arm/cpu_loop.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/m_helper.c

  Log Message:
  -----------
  target/arm: Change CPUArchState.thumb to bool

Bool is a more appropriate type for this value.
Adjust the assignments to use true/false.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b1cc0b46292d04a13d5a04f7f2dbf3023a08c6ab
      
https://github.com/qemu/qemu/commit/b1cc0b46292d04a13d5a04f7f2dbf3023a08c6ab
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/op_helper.c

  Log Message:
  -----------
  target/arm: Remove fpexc32_access

This function is incorrect in that it does not properly consider
CPTR_EL2.FPEN.  We've already got another mechanism for raising
an FPU access trap: ARM_CP_FPU, so use that instead.

Remove CP_ACCESS_TRAP_FP_EL{2,3}, which becomes unused.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 838bb102e0235b94f9c61f587a23f6c38e28a0b1
      
https://github.com/qemu/qemu/commit/838bb102e0235b94f9c61f587a23f6c38e28a0b1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Split out set_btype_raw

Common code for reset_btype and set_btype.
Use tcg_constant_i32.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2ec0baeab3001d1973166febded4c476003b0b2d
      
https://github.com/qemu/qemu/commit/2ec0baeab3001d1973166febded4c476003b0b2d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Split out gen_rebuild_hflags

For aa32, the function has a parameter to use the new el.
For aa64, that never happens.
Use tcg_constant_i32 while we're at it.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ec2897c39dc6e3f6d10d239975d1880277b1a6ff
      
https://github.com/qemu/qemu/commit/ec2897c39dc6e3f6d10d239975d1880277b1a6ff
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Simplify GEN_SHIFT in translate.c

Instead of computing

    tmp1 = shift & 0xff;
    dest = (tmp1 > 0x1f ? 0 : value) << (tmp1 & 0x1f)

use

    tmpd = value << (shift & 0x1f);
    dest = shift & 0xe0 ? 0 : tmpd;

which has a flatter dependency tree.
Use tcg_constant_i32 while we're at it.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e473cbd16853aecafa48577544821b1e76117610
      
https://github.com/qemu/qemu/commit/e473cbd16853aecafa48577544821b1e76117610
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Simplify gen_sar

Use tcg_gen_umin_i32 instead of tcg_gen_movcond_i32.
Use tcg_constant_i32 while we're at it.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: fbcc64e2fef0b3cf4e4f1017e6357900d3b66b42
      
https://github.com/qemu/qemu/commit/fbcc64e2fef0b3cf4e4f1017e6357900d3b66b42
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Simplify aa32 DISAS_WFI

The length of the previous insn may be computed from
the difference of start and end addresses.
Use tcg_constant_i32 while we're at it.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 04c9f543a554e26f4085919750baf24e2f7adfd2
      
https://github.com/qemu/qemu/commit/04c9f543a554e26f4085919750baf24e2f7adfd2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M target/arm/translate-m-nocp.c

  Log Message:
  -----------
  target/arm: Use tcg_constant in translate-m-nocp.c

Use tcg_constant_{i32,i64} as appropriate throughout.
This fixes a bug in trans_VSCCLRM() where we were leaking a TCGv.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7d38e4b5f5ace696456ca71b10b808b6652d8c0f
      
https://github.com/qemu/qemu/commit/7d38e4b5f5ace696456ca71b10b808b6652d8c0f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M target/arm/translate-neon.c

  Log Message:
  -----------
  target/arm: Use tcg_constant in translate-neon.c

Use tcg_constant_{i32,i64} as appropriate throughout.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3d99ab92dd45fccff296a429e2b18e0131ce4071
      
https://github.com/qemu/qemu/commit/3d99ab92dd45fccff296a429e2b18e0131ce4071
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Use smin/smax for do_sat_addsub_32

The operation we're performing with the movcond
is either min/max depending on cond -- simplify.
Use tcg_constant_i64 while we're at it.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 37c5b6385998a30f778f301de3295c62dd18a732
      
https://github.com/qemu/qemu/commit/37c5b6385998a30f778f301de3295c62dd18a732
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M target/arm/translate-vfp.c

  Log Message:
  -----------
  target/arm: Use tcg_constant in translate-vfp.c

Use tcg_constant_{i32,i64} as appropriate throughout.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 802e5c9bc8cd82354cb7072fb17f0c8c5b445cf1
      
https://github.com/qemu/qemu/commit/802e5c9bc8cd82354cb7072fb17f0c8c5b445cf1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Use tcg_constant_i32 in translate.h

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9792130613191c1e0c34109918c5e07b9f1429a5
      
https://github.com/qemu/qemu/commit/9792130613191c1e0c34109918c5e07b9f1429a5
  Author: Xiang Chen <chenxiang66@hisilicon.com>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M hw/arm/smmuv3.c

  Log Message:
  -----------
  hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in 
smmuv3_translate()

It always calls the IOMMU MR translate() callback with flag=IOMMU_NONE in
memory_region_iommu_replay(). Currently, smmuv3_translate() return an
IOMMUTLBEntry with perm set to IOMMU_NONE even if the translation success,
whereas it is expected to return the actual permission set in the table
entry.
So pass the actual perm to returned IOMMUTLBEntry in the table entry.

Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1650094695-121918-1-git-send-email-chenxiang66@hisilicon.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 51cb4ec7488f39cb5d0acc3b7f02dd663ab0fae4
      
https://github.com/qemu/qemu/commit/51cb4ec7488f39cb5d0acc3b7f02dd663ab0fae4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-22 (Fri, 22 Apr 2022)

  Changed paths:
    M docs/system/arm/virt.rst
    M hw/arm/smmuv3.c
    M hw/arm/virt.c
    M hw/intc/arm_gicv3_common.c
    M hw/intc/arm_gicv3_cpuif.c
    M hw/intc/arm_gicv3_dist.c
    M hw/intc/arm_gicv3_its.c
    M hw/intc/arm_gicv3_its_kvm.c
    M hw/intc/arm_gicv3_kvm.c
    M hw/intc/arm_gicv3_redist.c
    M hw/intc/gicv3_internal.h
    M hw/intc/trace-events
    M include/hw/arm/virt.h
    M include/hw/intc/arm_gicv3_common.h
    M include/hw/intc/arm_gicv3_its_common.h
    M linux-user/arm/cpu_loop.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper-a64.c
    M target/arm/helper.c
    M target/arm/hvf/hvf.c
    M target/arm/m_helper.c
    M target/arm/op_helper.c
    M target/arm/translate-a32.h
    M target/arm/translate-a64.c
    M target/arm/translate-m-nocp.c
    M target/arm/translate-neon.c
    M target/arm/translate-sve.c
    M target/arm/translate-vfp.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20220422' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Implement GICv4 emulation
 * Some cleanup patches in target/arm
 * hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in 
smmuv3_translate()

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# gpg: Signature made Fri 22 Apr 2022 03:03:24 AM PDT
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# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[full]

* tag 'pull-target-arm-20220422' of 
https://git.linaro.org/people/pmaydell/qemu-arm: (61 commits)
  hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in 
smmuv3_translate()
  target/arm: Use tcg_constant_i32 in translate.h
  target/arm: Use tcg_constant in translate-vfp.c
  target/arm: Use smin/smax for do_sat_addsub_32
  target/arm: Use tcg_constant in translate-neon.c
  target/arm: Use tcg_constant in translate-m-nocp.c
  target/arm: Simplify aa32 DISAS_WFI
  target/arm: Simplify gen_sar
  target/arm: Simplify GEN_SHIFT in translate.c
  target/arm: Split out gen_rebuild_hflags
  target/arm: Split out set_btype_raw
  target/arm: Remove fpexc32_access
  target/arm: Change CPUArchState.thumb to bool
  target/arm: Change DisasContext.thumb to bool
  target/arm: Extend store_cpu_offset to take field size
  target/arm: Change CPUArchState.aarch64 to bool
  target/arm: Change DisasContext.aarch64 to bool
  target/arm: Update SCTLR bits to ARMv9.2
  target/arm: Update SCR_EL3 bits to ARMv8.8
  target/arm: Update ISAR fields for ARMv8.8
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/10cd282ee44e...51cb4ec7488f
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