[Qemu-commits] [qemu/qemu] 434163: target/rx: Put tb_flags into DisasContext

[Richard Henderson]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 4341631e4d94e63c85de7215a6228fbf62293ec4
      
https://github.com/qemu/qemu/commit/4341631e4d94e63c85de7215a6228fbf62293ec4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-21 (Thu, 21 Apr 2022)

  Changed paths:
    M target/rx/translate.c

  Log Message:
  -----------
  target/rx: Put tb_flags into DisasContext

Copy tb->flags into ctx->tb_flags; we'll want to modify
this value throughout the tb in future.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-Id: <20220417165130.695085-2-richard.henderson@linaro.org>


  Commit: 3626a3fe37e993a86dc7cc4a0d3fb0d6a92c667d
      
https://github.com/qemu/qemu/commit/3626a3fe37e993a86dc7cc4a0d3fb0d6a92c667d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-21 (Thu, 21 Apr 2022)

  Changed paths:
    M target/rx/cpu.h
    M target/rx/translate.c

  Log Message:
  -----------
  target/rx: Store PSW.U in tb->flags

With this, we don't need movcond to determine
which stack pointer is current.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-Id: <20220417165130.695085-3-richard.henderson@linaro.org>


  Commit: d3562fe2588d3e0a15f3785d86792800d717984c
      
https://github.com/qemu/qemu/commit/d3562fe2588d3e0a15f3785d86792800d717984c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-21 (Thu, 21 Apr 2022)

  Changed paths:
    M target/rx/translate.c

  Log Message:
  -----------
  target/rx: Move DISAS_UPDATE check for write to PSW

Have one check in move_to_cr instead of one in each
function that calls move_to_cr.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-Id: <20220417165130.695085-4-richard.henderson@linaro.org>


  Commit: 3c69336a8773ec9dde145d40f3e715b9395e0aa0
      
https://github.com/qemu/qemu/commit/3c69336a8773ec9dde145d40f3e715b9395e0aa0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-21 (Thu, 21 Apr 2022)

  Changed paths:
    M target/rx/translate.c

  Log Message:
  -----------
  target/rx: Swap stack pointers on clrpsw/setpsw instruction

We properly perform this swap in helper_set_psw for MVTC,
but we missed doing so for the CLRPSW/SETPSW of the U bit.

Reported-by: Tomoaki Kawada <i@yvt.jp>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-Id: <20220417165130.695085-5-richard.henderson@linaro.org>


  Commit: bcc6f33b671d223a1d7b81491d45c58b35ed6e3e
      
https://github.com/qemu/qemu/commit/bcc6f33b671d223a1d7b81491d45c58b35ed6e3e
  Author: Yoshinori Sato <ysato@users.sourceforge.jp>
  Date:   2022-04-21 (Thu, 21 Apr 2022)

  Changed paths:
    M hw/rx/rx-gdbsim.c

  Log Message:
  -----------
  hw/rx: rx-gdbsim DTB load address aligned of 16byte.

Linux kernel required alined address of DTB.
But missing align in dtb load function.
Fixed to load to the correct address.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220207132758.84403-1-ysato@users.sourceforge.jp>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 335cd065977bda4e2b6290f9aecad320a9391bfe
      
https://github.com/qemu/qemu/commit/335cd065977bda4e2b6290f9aecad320a9391bfe
  Author: Tomoaki Kawada <i@yvt.jp>
  Date:   2022-04-21 (Thu, 21 Apr 2022)

  Changed paths:
    M target/rx/op_helper.c

  Log Message:
  -----------
  target/rx: set PSW.I when executing wait instruction

This patch fixes the implementation of the wait instruction to
implicitly update PSW.I as required by the ISA specification.

Signed-off-by: Tomoaki Kawada <i@yvt.jp>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220417045937.2128699-1-i@yvt.jp>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 724eaecec6d22cf3842f896684bdc5b79492f093
      
https://github.com/qemu/qemu/commit/724eaecec6d22cf3842f896684bdc5b79492f093
  Author: Tomoaki Kawada <i@yvt.jp>
  Date:   2022-04-21 (Thu, 21 Apr 2022)

  Changed paths:
    M target/rx/translate.c

  Log Message:
  -----------
  target/rx: update PC correctly in wait instruction

`cpu_pc` at this point does not necessary point to the current
instruction (i.e., the wait instruction being translated), so it's
incorrect to calculate the new value of `cpu_pc` based on this. It must
be updated with `ctx->base.pc_next`, which contains the correct address
of the next instruction.

This change fixes the wait instruction skipping the subsequent branch
when used in an idle loop like this:

    0:  wait
        bra.b 0b
        brk   // should be unreachable

Signed-off-by: Tomoaki Kawada <i@yvt.jp>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220417060224.2131788-1-i@yvt.jp>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4ba2565831688a83f9b7465d228cdef19aea412c
      
https://github.com/qemu/qemu/commit/4ba2565831688a83f9b7465d228cdef19aea412c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-21 (Thu, 21 Apr 2022)

  Changed paths:
    M hw/rx/rx-gdbsim.c
    M target/rx/cpu.h
    M target/rx/op_helper.c
    M target/rx/translate.c

  Log Message:
  -----------
  Merge tag 'pull-rx-20220421' of https://gitlab.com/rth7680/qemu into staging

Fix usp/isp swapping upon clrpsw/setpsw.
Fix psw.i/pc upon wait.
Align dtb in ram.

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[ultimate]

* tag 'pull-rx-20220421' of https://gitlab.com/rth7680/qemu:
  target/rx: update PC correctly in wait instruction
  target/rx: set PSW.I when executing wait instruction
  hw/rx: rx-gdbsim DTB load address aligned of 16byte.
  target/rx: Swap stack pointers on clrpsw/setpsw instruction
  target/rx: Move DISAS_UPDATE check for write to PSW
  target/rx: Store PSW.U in tb->flags
  target/rx: Put tb_flags into DisasContext

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/da5006445a92...4ba256583168