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[Qemu-commits] [qemu/qemu] 78255c: hw/arm/virt: Check for attempt to use
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 78255c: hw/arm/virt: Check for attempt to use TrustZone wi... |
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Date: |
Thu, 21 Apr 2022 09:24:15 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 78255ce392dc8596f9886476ad1e5c3c67f1c10a
https://github.com/qemu/qemu/commit/78255ce392dc8596f9886476ad1e5c3c67f1c10a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF
It's not possible to provide the guest with the Security extensions
(TrustZone) when using KVM or HVF, because the hardware
virtualization extensions don't permit running EL3 guest code.
However, we weren't checking for this combination, with the result
that QEMU would assert if you tried it:
$ qemu-system-aarch64 -enable-kvm -machine virt,secure=on -cpu host -display
none
Unexpected error in object_property_find_err() at ../../qom/object.c:1304:
qemu-system-aarch64: Property 'host-arm-cpu.secure-memory' not found
Aborted
Check for this combination of options and report an error, in the
same way we already do for attempts to give a KVM or HVF guest the
Virtualization or MTE extensions. Now we will report:
qemu-system-aarch64: mach-virt: KVM does not support providing Security
extensions (TrustZone) to the guest CPU
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/961
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404155301.566542-1-peter.maydell@linaro.org
Commit: 09fc50cdce522cfed21bfd2a08b575c9f1a3c30b
https://github.com/qemu/qemu/commit/09fc50cdce522cfed21bfd2a08b575c9f1a3c30b
Author: Edgar E. Iglesias <edgar.iglesias@amd.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/timer/cadence_ttc.c
A include/hw/timer/cadence_ttc.h
Log Message:
-----------
timer: cadence_ttc: Break out header file to allow embedding
Break out header file to allow embedding of the the TTC.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20220331222017.2914409-2-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 51af6231ad344c64069faad630d0889b9723ed3a
https://github.com/qemu/qemu/commit/51af6231ad344c64069faad630d0889b9723ed3a
Author: Edgar E. Iglesias <edgar.iglesias@amd.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/xlnx-zynqmp.c
M include/hw/arm/xlnx-zynqmp.h
Log Message:
-----------
hw/arm/xlnx-zynqmp: Connect 4 TTC timers
Connect the 4 TTC timers on the ZynqMP.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20220331222017.2914409-3-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8779d00c4e337a9e0d85c9abf456e3c713fad808
https://github.com/qemu/qemu/commit/8779d00c4e337a9e0d85c9abf456e3c713fad808
Author: Edgar E. Iglesias <edgar.iglesias@amd.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/xlnx-versal.c
M include/hw/arm/xlnx-versal.h
Log Message:
-----------
hw/arm: versal: Create an APU CPU Cluster
Create an APU CPU Cluster. This is in preparation to add the RPU.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20220406174303.2022038-2-edgar.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 67a645a35110f300144ae844cbf839762abcd98d
https://github.com/qemu/qemu/commit/67a645a35110f300144ae844cbf839762abcd98d
Author: Edgar E. Iglesias <edgar.iglesias@amd.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/xlnx-versal-virt.c
M hw/arm/xlnx-versal.c
M include/hw/arm/xlnx-versal.h
Log Message:
-----------
hw/arm: versal: Add the Cortex-R5Fs
Add the Cortex-R5Fs of the Versal RPU (Real-time Processing Unit)
subsystem.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20220406174303.2022038-3-edgar.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 369e5cb0c948b65e0845ca3394e25d757dd93206
https://github.com/qemu/qemu/commit/369e5cb0c948b65e0845ca3394e25d757dd93206
Author: Edgar E. Iglesias <edgar.iglesias@amd.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/misc/meson.build
A hw/misc/xlnx-versal-crl.c
A include/hw/misc/xlnx-versal-crl.h
Log Message:
-----------
hw/misc: Add a model of the Xilinx Versal CRL
Add a model of the Xilinx Versal CRL.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Frederic Konrad <fkonrad@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20220406174303.2022038-4-edgar.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d6ccfc7e6734383926fccfdb92df238761cb9423
https://github.com/qemu/qemu/commit/d6ccfc7e6734383926fccfdb92df238761cb9423
Author: Edgar E. Iglesias <edgar.iglesias@amd.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/xlnx-versal.c
M include/hw/arm/xlnx-versal.h
Log Message:
-----------
hw/arm: versal: Connect the CRL
Connect the CRL (Clock Reset LPD) to the Versal SoC.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Frederic Konrad <fkonrad@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20220406174303.2022038-5-edgar.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2bd84b6818c790508a65ec34e268295c3cb9315f
https://github.com/qemu/qemu/commit/2bd84b6818c790508a65ec34e268295c3cb9315f
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/exynos4210.c
M include/hw/arm/exynos4210.h
Log Message:
-----------
hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device
The Exynos4210 SoC device currently uses a custom device
"exynos4210.irq_gate" to model the OR gate that feeds each CPU's IRQ
line. We have a standard TYPE_OR_IRQ device for this now, so use
that instead.
(This is a migration compatibility break, but that is OK for this
machine type.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-2-peter.maydell@linaro.org
Commit: 019eafddd085352b1e0c758ffb8ef532bedb8512
https://github.com/qemu/qemu/commit/019eafddd085352b1e0c758ffb8ef532bedb8512
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/intc/exynos4210_gic.c
Log Message:
-----------
hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE
Now we have removed the only use of TYPE_EXYNOS4210_IRQ_GATE we can
delete the device entirely.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20220404154658.565020-3-peter.maydell@linaro.org
Commit: 5b2417288e9bdd437685725cd432692ed8f104e4
https://github.com/qemu/qemu/commit/5b2417288e9bdd437685725cd432692ed8f104e4
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/exynos4210.c
M include/hw/arm/exynos4210.h
Log Message:
-----------
hw/arm/exynos4210: Put a9mpcore device into state struct
The exynos4210 SoC mostly creates its child devices as if it were
board code. This includes the a9mpcore object. Switch that to a
new-style "embedded in the state struct" creation, because in the
next commit we're going to want to refer to the object again further
down in the exynos4210_realize() function.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-4-peter.maydell@linaro.org
Commit: c9d4940a9be2065d9d124f9963cbacea881b892c
https://github.com/qemu/qemu/commit/c9d4940a9be2065d9d124f9963cbacea881b892c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/exynos4210.c
M include/hw/arm/exynos4210.h
Log Message:
-----------
hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct
The only time we use the int_gic_irq[] array in the Exynos4210Irq
struct is in the exynos4210_realize() function: we initialize it with
the GPIO inputs of the a9mpcore device, and then a bit later on we
connect those to the outputs of the internal combiner. Now that the
a9mpcore object is easily accessible as s->a9mpcore we can make the
connection directly from one device to the other without going via
this array.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-5-peter.maydell@linaro.org
Commit: 771dee52c09ec40791a3e8651c395e6aa097c664
https://github.com/qemu/qemu/commit/771dee52c09ec40791a3e8651c395e6aa097c664
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/exynos4210.c
M hw/intc/exynos4210_gic.c
M include/hw/arm/exynos4210.h
Log Message:
-----------
hw/arm/exynos4210: Coalesce board_irqs and irq_table
The exynos4210 code currently has two very similar arrays of IRQs:
* board_irqs is a field of the Exynos4210Irq struct which is filled
in by exynos4210_init_board_irqs() with the appropriate qemu_irqs
for each IRQ the board/SoC can assert
* irq_table is a set of qemu_irqs pointed to from the
Exynos4210State struct. It's allocated in exynos4210_init_irq,
and the only behaviour these irqs have is that they pass on the
level to the equivalent board_irqs[] irq
The extra indirection through irq_table is unnecessary, so coalesce
these into a single irq_table[] array as a direct field in
Exynos4210State which exynos4210_init_board_irqs() fills in.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-6-peter.maydell@linaro.org
Commit: 44068eabe0826c24096ddc2431ae9a03a7321a83
https://github.com/qemu/qemu/commit/44068eabe0826c24096ddc2431ae9a03a7321a83
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/intc/exynos4210_gic.c
Log Message:
-----------
hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[]
Fix a missing set of spaces around '-' in the definition of
combiner_grp_to_gic_id[]. We're about to move this code, so
fix the style issue first to keep checkpatch happy with the
code-motion patch.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-7-peter.maydell@linaro.org
Commit: 93afe073df30944191a1fe2a7fd4f0456e231720
https://github.com/qemu/qemu/commit/93afe073df30944191a1fe2a7fd4f0456e231720
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/exynos4210.c
M hw/intc/exynos4210_gic.c
M include/hw/arm/exynos4210.h
Log Message:
-----------
hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c
The function exynos4210_init_board_irqs() currently lives in
exynos4210_gic.c, but it isn't really part of the exynos4210.gic
device -- it is a function that implements (some of) the wiring up of
interrupts between the SoC's GIC and combiner components. This means
it fits better in exynos4210.c, which is the SoC-level code. Move it
there. Similarly, exynos4210_git_irq() is used almost only in the
SoC-level code, so move it too.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-8-peter.maydell@linaro.org
Commit: 78cb12a92c5466b792224e1f4c3e061d233d383b
https://github.com/qemu/qemu/commit/78cb12a92c5466b792224e1f4c3e061d233d383b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M MAINTAINERS
M hw/arm/exynos4210.c
M hw/intc/exynos4210_gic.c
M include/hw/arm/exynos4210.h
A include/hw/intc/exynos4210_gic.h
Log Message:
-----------
hw/arm/exynos4210: Put external GIC into state struct
Switch the creation of the external GIC to the new-style "embedded in
state struct" approach, so we can easily refer to the object
elsewhere during realize.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-9-peter.maydell@linaro.org
Commit: 38c2b905d3beb27a056f7f53bcf7d9bce487e89d
https://github.com/qemu/qemu/commit/38c2b905d3beb27a056f7f53bcf7d9bce487e89d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/exynos4210.c
M include/hw/arm/exynos4210.h
Log Message:
-----------
hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct
The only time we use the ext_gic_irq[] array in the Exynos4210Irq
struct is during realize of the SoC -- we initialize it with the
input IRQs of the external GIC device, and then connect those to
outputs of other devices further on in realize (including in the
exynos4210_init_board_irqs() function). Now that the ext_gic object
is easily accessible as s->ext_gic we can make the connections
directly from one device to the other without going via this array.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-10-peter.maydell@linaro.org
Commit: 03a46e00813ae8bd0243457b12d48fd8d2d4d350
https://github.com/qemu/qemu/commit/03a46e00813ae8bd0243457b12d48fd8d2d4d350
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/exynos4210.c
M hw/intc/exynos4210_combiner.c
M include/hw/arm/exynos4210.h
Log Message:
-----------
hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.c
The function exynos4210_combiner_get_gpioin() currently lives in
exynos4210_combiner.c, but it isn't really part of the combiner
device itself -- it is a function that implements the wiring up of
some interrupt sources to multiple combiner inputs. Move it to live
with the other SoC-level code in exynos4210.c, along with a few
macros previously defined in exynos4210.h which are now used only
in exynos4210.c.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-11-peter.maydell@linaro.org
Commit: b17b54a63d1071b862361d31c7d20ad7a620c182
https://github.com/qemu/qemu/commit/b17b54a63d1071b862361d31c7d20ad7a620c182
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M include/hw/arm/exynos4210.h
Log Message:
-----------
hw/arm/exynos4210: Delete unused macro definitions
Delete a couple of #defines which are never used.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-12-peter.maydell@linaro.org
Commit: 7582d930dad3331bfdd7a4e1fe5d2080051d10d9
https://github.com/qemu/qemu/commit/7582d930dad3331bfdd7a4e1fe5d2080051d10d9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/exynos4210.c
M include/hw/arm/exynos4210.h
Log Message:
-----------
hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs()
In exynos4210_init_board_irqs(), use the TYPE_SPLIT_IRQ device
instead of qemu_irq_split().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-13-peter.maydell@linaro.org
Commit: 0dee4daca37e1547b4b2a24d5a2318d5e5a5af89
https://github.com/qemu/qemu/commit/0dee4daca37e1547b4b2a24d5a2318d5e5a5af89
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/exynos4210.c
Log Message:
-----------
hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ lines
In exynos4210_init_board_irqs(), the loop that handles IRQ lines that
are in a range that applies to the internal combiner only creates a
splitter for those interrupts which go to both the internal combiner
and to the external GIC, but it does nothing at all for the
interrupts which don't go to the external GIC, leaving the
irq_table[] array element empty for those. (This will result in
those interrupts simply being lost, not in a QEMU crash.)
I don't have a reliable datasheet for this SoC, but since we do wire
up one interrupt line in this category (the HDMI I2C device on
interrupt 16,1), this seems like it must be a bug in the existing
QEMU code. Fill in the irq_table[] entries where we're not splitting
the IRQ to both the internal combiner and the external GIC with the
IRQ line of the internal combiner. (That is, these IRQ lines go to
just one device, not multiple.)
This bug didn't have any visible guest effects because the only
implemented device that was affected was the HDMI I2C controller,
and we never connect any I2C devices to that bus.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-14-peter.maydell@linaro.org
Commit: 1c6f3feeb3ceec6f5359515f931b3ab7b2c17457
https://github.com/qemu/qemu/commit/1c6f3feeb3ceec6f5359515f931b3ab7b2c17457
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/exynos4210.c
Log Message:
-----------
hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners
Currently for the interrupts MCT_G0 and MCT_G1 which are
the only ones in the input range of the external combiner
and which are also wired to the external GIC, we connect
them only to the internal combiner and the external GIC.
This seems likely to be a bug, as all other interrupts
which are in the input range of both combiners are
connected to both combiners. (The fact that the code in
exynos4210_combiner_get_gpioin() is also trying to wire
up these inputs on both combiners also suggests this.)
Wire these interrupts up to both combiners, like the rest.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-15-peter.maydell@linaro.org
Commit: 76124b4cb23f9efdd0746e057eeb64c9d48bbead
https://github.com/qemu/qemu/commit/76124b4cb23f9efdd0746e057eeb64c9d48bbead
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/exynos4210.c
M include/hw/arm/exynos4210.h
Log Message:
-----------
hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs
The combiner_grp_to_gic_id[] array includes the EXT_GIC_ID_MCT_G0
and EXT_GIC_ID_MCT_G1 multiple times. This means that we will
connect multiple IRQs up to the same external GIC input, which
is not permitted. We do the same thing in the code in
exynos4210_init_board_irqs() because the conditionals selecting
an irq_id in the first loop match multiple interrupt IDs.
Overall we do this for interrupt IDs
(1, 4), (12, 4), (35, 4), (51, 4), (53, 4) for EXT_GIC_ID_MCT_G0
and
(1, 5), (12, 5), (35, 5), (51, 5), (53, 5) for EXT_GIC_ID_MCT_G1
These correspond to the cases for the multi-core timer that we are
wiring up to multiple inputs on the combiner in
exynos4210_combiner_get_gpioin(). That code already deals with all
these interrupt IDs being the same input source, so we don't need to
connect the external GIC interrupt for any of them except the first
(1, 4) and (1, 5). Remove the array entries and conditionals which
were incorrectly causing us to wire up extra lines.
This bug didn't cause any visible effects, because we only connect
up a device to the "primary" ID values (1, 4) and (1, 5), so the
extra lines would never be set to a level.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-16-peter.maydell@linaro.org
Commit: 76621953c9966bab33ea99a39e47130169bec389
https://github.com/qemu/qemu/commit/76621953c9966bab33ea99a39e47130169bec389
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/exynos4210.c
M include/hw/arm/exynos4210.h
Log Message:
-----------
hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs()
At this point, the function exynos4210_init_board_irqs() splits input
IRQ lines to connect them to the input combiner, output combiner and
external GIC. The function exynos4210_combiner_get_gpioin() splits
some of the combiner input lines further to connect them to multiple
different inputs on the combiner.
Because (unlike qemu_irq_split()) the TYPE_SPLIT_IRQ device has a
configurable number of outputs, we can do all this in one place, by
making exynos4210_init_board_irqs() add extra outputs to the splitter
device when it must be connected to more than one input on each
combiner.
We do this with a new data structure, the combinermap, which is an
array each of whose elements is a list of the interrupt IDs on the
combiner which must be tied together. As we loop through each
interrupt ID, if we find that it is the first one in one of these
lists, we configure the splitter device with eonugh extra outputs and
wire them up to the other interrupt IDs in the list.
Conveniently, for all the cases where this is necessary, the
lowest-numbered interrupt ID in each group is in the range of the
external combiner, so we only need to code for this in the first of
the two loops in exynos4210_init_board_irqs().
The old code in exynos4210_combiner_get_gpioin() which is being
deleted here had several problems which don't exist in the new code
in its handling of the multi-core timer interrupts:
(1) the case labels specified bits 4 ... 8, but bit '8' doesn't
exist; these should have been 4 ... 7
(2) it used the input irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]
multiple times as the input of several different splitters,
which isn't allowed
(3) in an apparent cut-and-paste error, the cases for all the
multi-core timer inputs used "bit + 4" even though the
bit range for the case was (intended to be) 4 ... 7, which
meant it was looking at non-existent bits 8 ... 11.
None of these exist in the new code.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-17-peter.maydell@linaro.org
Commit: cebef07df5c0cfb284f7e5e69cde1ae509fb6ada
https://github.com/qemu/qemu/commit/cebef07df5c0cfb284f7e5e69cde1ae509fb6ada
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/exynos4210.c
M hw/intc/exynos4210_combiner.c
M include/hw/arm/exynos4210.h
A include/hw/intc/exynos4210_combiner.h
Log Message:
-----------
hw/arm/exynos4210: Put combiners into state struct
Switch the creation of the combiner devices to the new-style
"embedded in state struct" approach, so we can easily refer
to the object elsewhere during realize.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-18-peter.maydell@linaro.org
Commit: f37fc537fc1f129ca94ec5e29f4c98f3724d7929
https://github.com/qemu/qemu/commit/f37fc537fc1f129ca94ec5e29f4c98f3724d7929
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/exynos4210.c
M include/hw/arm/exynos4210.h
Log Message:
-----------
hw/arm/exynos4210: Drop Exynos4210Irq struct
The only time we use the int_combiner_irq[] and ext_combiner_irq[]
arrays in the Exynos4210Irq struct is during realize of the SoC -- we
initialize them with the input IRQs of the combiner devices, and then
connect those to outputs of other devices in
exynos4210_init_board_irqs(). Now that the combiner objects are
easily accessible as s->int_combiner and s->ext_combiner we can make
the connections directly from one device to the other without going
via these arrays.
Since these are the only two remaining elements of Exynos4210Irq,
we can remove that struct entirely.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-19-peter.maydell@linaro.org
Commit: d5c3eb50afac631d41daec7c09a959fa06304fce
https://github.com/qemu/qemu/commit/d5c3eb50afac631d41daec7c09a959fa06304fce
Author: Zongyuan Li <zongyuan.li@smartx.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/realview.c
Log Message:
-----------
hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220324181557.203805-2-zongyuan.li@smartx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d0a030d80165d0b20b0687dab8f99056eee68352
https://github.com/qemu/qemu/commit/d0a030d80165d0b20b0687dab8f99056eee68352
Author: Zongyuan Li <zongyuan.li@smartx.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/stellaris.c
Log Message:
-----------
hw/arm/stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220324181557.203805-3-zongyuan.li@smartx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0ebfc997d29c3789b9bd41fe53fc198c2fd550da
https://github.com/qemu/qemu/commit/0ebfc997d29c3789b9bd41fe53fc198c2fd550da
Author: Zongyuan Li <zongyuan.li@smartx.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/core/irq.c
M include/hw/irq.h
Log Message:
-----------
hw/core/irq: remove unused 'qemu_irq_split' function
Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220324181557.203805-5-zongyuan.li@smartx.com
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/811
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 011301736bd238ed91864a4c305616a78f9056ed
https://github.com/qemu/qemu/commit/011301736bd238ed91864a4c305616a78f9056ed
Author: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M docs/system/arm/virt.rst
Log Message:
-----------
hw/arm/virt: impact of gic-version on max CPUs
Describe that the gic-version influences the maximum number of CPUs.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Message-id: 20220413231456.35811-1-heinrich.schuchardt@canonical.com
[PMM: minor punctuation tweaks]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c3e9e73a8323cc61386c3067715ba4e44ea95a0f
https://github.com/qemu/qemu/commit/c3e9e73a8323cc61386c3067715ba4e44ea95a0f
Author: Hao Wu <wuhaotsh@google.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M include/hw/misc/npcm7xx_gcr.h
Log Message:
-----------
hw/misc: Add PWRON STRAP bit fields in GCR module
Similar to the Aspeed code in include/misc/aspeed_scu.h, we define
the PWRON STRAP fields in their corresponding module for NPCM7XX.
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Message-id: 20220411165842.3912945-2-wuhaotsh@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5b415dd61bdbf61fb4be0e9f1a7172b8bce682c6
https://github.com/qemu/qemu/commit/5b415dd61bdbf61fb4be0e9f1a7172b8bce682c6
Author: Hao Wu <wuhaotsh@google.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/arm/npcm7xx_boards.c
Log Message:
-----------
hw/arm: Use bit fields for NPCM7XX PWRON STRAPs
This patch uses the defined fields to describe PWRON STRAPs for
better readability.
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Message-id: 20220411165842.3912945-3-wuhaotsh@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 401d46789410e88e9e90d76a11f46e8e9f358d55
https://github.com/qemu/qemu/commit/401d46789410e88e9e90d76a11f46e8e9f358d55
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M MAINTAINERS
M docs/system/arm/virt.rst
M hw/arm/exynos4210.c
M hw/arm/npcm7xx_boards.c
M hw/arm/realview.c
M hw/arm/stellaris.c
M hw/arm/virt.c
M hw/arm/xlnx-versal-virt.c
M hw/arm/xlnx-versal.c
M hw/arm/xlnx-zynqmp.c
M hw/core/irq.c
M hw/intc/exynos4210_combiner.c
M hw/intc/exynos4210_gic.c
M hw/misc/meson.build
A hw/misc/xlnx-versal-crl.c
M hw/timer/cadence_ttc.c
M include/hw/arm/exynos4210.h
M include/hw/arm/xlnx-versal.h
M include/hw/arm/xlnx-zynqmp.h
A include/hw/intc/exynos4210_combiner.h
A include/hw/intc/exynos4210_gic.h
M include/hw/irq.h
M include/hw/misc/npcm7xx_gcr.h
A include/hw/misc/xlnx-versal-crl.h
A include/hw/timer/cadence_ttc.h
Log Message:
-----------
Merge tag 'pull-target-arm-20220421' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF
* versal: Add the Cortex-R5s in the Real-Time Processing Unit (RPU) subsystem
* versal: model enough of the Clock/Reset Low-power domain (CRL) to allow
control of the Cortex-R5s
* xlnx-zynqmp: Connect 4 TTC timers
* exynos4210: Refactor GIC/combiner code to stop using qemu_split_irq
* realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
* stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
* hw/core/irq: remove unused 'qemu_irq_split' function
* npcm7xx: use symbolic constants for PWRON STRAP bit fields
* virt: document impact of gic-version on max CPUs
# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmJhPSUZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3hAsD/4qzZK6LFL4kFH6E4z3tWIn
# ErHrfPGUt/SEfHLP+stQP/loFgkR1SNzcrIZ/HiDCB/W+IqQKuP+tHin2lMhO1tR
# KM6suUO1In2hoxfzimVta4F4GVN8ifY69qUYhaRxcBYSUpRXDNFJGsRIeT5JeUMd
# SArZUifRs7JUo25rIkg5Y+YZE37dmiA5gcuswtoLPa/UlDVqRxihLnItySmeutsc
# /Y8d/iym/ydlhvtL1OUt1KKYeg4ykrPzJCfvopsT2xgkwwB0PYci8//fa5IrRVlp
# Uw6yDssZrDIcXfVz88rdriILaszicCv8lOhTH6I74oXCatiyvi4BEzW8uGqVS8wt
# ff+AaKvGqb5t4GKKhCdpL2NzDwKBGWZHuruACs9IfvMkz62HE12Vr99qAKdQ3s93
# QnFIyUKg90mGkvKy8336zX3hnWjPH8wTASOXbNrgnt6GVLkqwy9ibug5kS+n77eJ
# BnkE5p3OfMVJ5a4o+iZbbDJKfzhNUHDSMIBbG1jRNzax1RgxOBtHFSqP5jmbpm+S
# agyr8h+Md0Tx1dwZKxdCGyvcbSZiG2WxRnci3dyT4MqYY1t1GEpOfcs1EN+CYKwG
# iuezZzJopjOFGaXQaB3OvbvCKxuroHKG61SmDmx+5OkfAxhrqe4ulwYij4jhsyhH
# t8zGzDOKLakv3li90xCX/w==
# =Rke9
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 21 Apr 2022 04:16:53 AM PDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
* tag 'pull-target-arm-20220421' of
https://git.linaro.org/people/pmaydell/qemu-arm: (31 commits)
hw/arm: Use bit fields for NPCM7XX PWRON STRAPs
hw/misc: Add PWRON STRAP bit fields in GCR module
hw/arm/virt: impact of gic-version on max CPUs
hw/core/irq: remove unused 'qemu_irq_split' function
hw/arm/stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
hw/arm/exynos4210: Drop Exynos4210Irq struct
hw/arm/exynos4210: Put combiners into state struct
hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs()
hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs
hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners
hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ lines
hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs()
hw/arm/exynos4210: Delete unused macro definitions
hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.c
hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct
hw/arm/exynos4210: Put external GIC into state struct
hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c
hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[]
hw/arm/exynos4210: Coalesce board_irqs and irq_table
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/b1efff6bf031...401d46789410