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[Qemu-commits] [qemu/qemu] 7a11bd: hw/ssi: Add Ibex SPI device model
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 7a11bd: hw/ssi: Add Ibex SPI device model |
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Date: |
Thu, 21 Apr 2022 07:00:12 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 7a11bd1a84c050643384a5abc59eda6093ba30c5
https://github.com/qemu/qemu/commit/7a11bd1a84c050643384a5abc59eda6093ba30c5
Author: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
A hw/ssi/ibex_spi_host.c
M hw/ssi/meson.build
M hw/ssi/trace-events
A include/hw/ssi/ibex_spi_host.h
Log Message:
-----------
hw/ssi: Add Ibex SPI device model
Adds the SPI_HOST device model for ibex. The device specification is as per
[1]. The model has been tested on opentitan with spi_host unit tests
written for TockOS.
[1] https://docs.opentitan.org/hw/ip/spi_host/doc/
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220303045426.511588-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a1591ef1e379172de48cbc5b1958f3690ac741b5
https://github.com/qemu/qemu/commit/a1591ef1e379172de48cbc5b1958f3690ac741b5
Author: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/riscv/opentitan.c
M include/hw/riscv/opentitan.h
Log Message:
-----------
riscv: opentitan: Connect opentitan SPI Host
Connect spi host[1/0] to opentitan.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220303045426.511588-2-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 21ea4aab7562b9d6cb4ba411e18b16e2e52185af
https://github.com/qemu/qemu/commit/21ea4aab7562b9d6cb4ba411e18b16e2e52185af
Author: Atish Patra <atishp@rivosinc.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: Define simpler privileged spec version numbering
Currently, the privileged specification version are defined in
a complex manner for no benefit.
Simplify it by changing it to a simple enum based on.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220303185440.512391-2-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5e8e8089fd2fbb14f6ba34222cdf0d9ee0392e3a
https://github.com/qemu/qemu/commit/5e8e8089fd2fbb14f6ba34222cdf0d9ee0392e3a
Author: Atish Patra <atishp@rivosinc.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: Add the privileged spec version 1.12.0
Add the definition for ratified privileged specification version v1.12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220303185440.512391-3-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b6cf78609292fd3d72bf8f056c338520eab30532
https://github.com/qemu/qemu/commit/b6cf78609292fd3d72bf8f056c338520eab30532
Author: Atish Patra <atishp@rivosinc.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/cpu.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Introduce privilege version field in the CSR ops.
To allow/disallow the CSR access based on the privilege spec, a new field
in the csr_ops is introduced. It also adds the privileged specification
version (v1.12) for the CSRs introduced in the v1.12. This includes the
new ratified extensions such as Vector, Hypervisor and secconfig CSR.
However, it doesn't enforce the privilege version in this commit.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220303185440.512391-4-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 849798c8d687d2fbe6aae08a85de576164fd3b7d
https://github.com/qemu/qemu/commit/849798c8d687d2fbe6aae08a85de576164fd3b7d
Author: Atish Patra <atishp@rivosinc.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/cpu_bits.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Add support for mconfigptr
RISC-V privileged specification v1.12 introduced a mconfigptr
which will hold the physical address of a configuration data
structure. As Qemu doesn't have a configuration data structure,
is read as zero which is valid as per the priv spec.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220303185440.512391-5-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f46dff68ffc63e9f20d324a0704ae2496b209347
https://github.com/qemu/qemu/commit/f46dff68ffc63e9f20d324a0704ae2496b209347
Author: Atish Patra <atishp@rivosinc.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/csr.c
M target/riscv/machine.c
Log Message:
-----------
target/riscv: Add *envcfg* CSRs support
The RISC-V privileged specification v1.12 defines few execution
environment configuration CSRs that can be used enable/disable
extensions per privilege levels.
Add the basic support for these CSRs.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220303185440.512391-6-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 54ee15ff75c4d4fda5cca67582b91706130afa16
https://github.com/qemu/qemu/commit/54ee15ff75c4d4fda5cca67582b91706130afa16
Author: Atish Patra <atishp@rivosinc.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Enable privileged spec version 1.12
Virt machine uses privileged specification version 1.12 now.
All other machine continue to use the default one defined for that
machine unless changed to 1.12 by the user explicitly.
This commit enforces the privilege version for csrs introduced in
v1.12 or after.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220303185440.512391-7-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1f7c961d487bb2bfec37de12d428a122d1a5e848
https://github.com/qemu/qemu/commit/1f7c961d487bb2bfec37de12d428a122d1a5e848
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: cpu: Fixup indentation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220317061817.3856850-2-alistair.francis@opensource.wdc.com>
Commit: 8184bcf513783c08495775a3c8ab9e0291f3beb0
https://github.com/qemu/qemu/commit/8184bcf513783c08495775a3c8ab9e0291f3beb0
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Allow software access to MIP SEIP
The RISC-V specification states that:
"Supervisor-level external interrupts are made pending based on the
logical-OR of the software-writable SEIP bit and the signal from the
external interrupt controller."
We currently only allow either the interrupt controller or software to
set the bit, which is incorrect.
This patch removes the miclaim mask when writing MIP to allow M-mode
software to inject interrupts, even with an interrupt controller.
We then also need to keep track of which source is setting MIP_SEIP. The
final value is a OR of both, so we add two bools and use that to keep
track of the current state. This way either source can change without
losing the correct value.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/904
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220317061817.3856850-3-alistair.francis@opensource.wdc.com>
Commit: 3a35f7e06d4dffbcfde3b90ac2a52a5b86352416
https://github.com/qemu/qemu/commit/3a35f7e06d4dffbcfde3b90ac2a52a5b86352416
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/cpu.h
A target/riscv/debug.c
A target/riscv/debug.h
M target/riscv/meson.build
Log Message:
-----------
target/riscv: Add initial support for the Sdtrig extension
This adds initial support for the Sdtrig extension via the Trigger
Module, as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 triggers implemented is 2, which is the number that we can
find in the SiFive U54/U74 cores.
[1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220315065529.62198-2-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 24fd8e0ef691813dfe4bd89a1dcc946e86139c41
https://github.com/qemu/qemu/commit/24fd8e0ef691813dfe4bd89a1dcc946e86139c41
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: optimize condition assign for scale < 0
for some cases, scale is always equal or less than 0, since lmul is not larger
than 3
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220325085902.29500-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2af67e000f3ce3b2ec4249fb0b7544829cf21d66
https://github.com/qemu/qemu/commit/2af67e000f3ce3b2ec4249fb0b7544829cf21d66
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/helper.h
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: optimize helper for vmv<nr>r.v
LEN is not used for GEN_VEXT_VMV_WHOLE macro, so vmv<nr>r.v can share
the same helper
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220325085902.29500-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: dda0f0403a92a824698b71c819f85e972c8f567b
https://github.com/qemu/qemu/commit/dda0f0403a92a824698b71c819f85e972c8f567b
Author: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: misa to ISA string conversion fix
Some bits in RISC-V `misa' CSR should not be reflected in the ISA
string. For instance, `S' and `U' (represents existence of supervisor
and user mode, respectively) in `misa' CSR must not be copied since
neither `S' nor `U' are valid single-letter extensions.
This commit also removes all reserved/dropped single-letter "extensions"
from the list.
- "B": Not going to be a single-letter extension (misa.B is reserved).
- "J": Not going to be a single-letter extension (misa.J is reserved).
- "K": Not going to be a single-letter extension (misa.K is reserved).
- "L": Dropped.
- "N": Dropped.
- "T": Dropped.
It also clarifies that the variable `riscv_single_letter_exts' is a
single-letter extension order list.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id:
<4a4c11213a161a7eedabe46abe58b351bb0e2ef2.1648473008.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2c9763529b62a5e0979e2a650601f3975c7d97f4
https://github.com/qemu/qemu/commit/2c9763529b62a5e0979e2a650601f3975c7d97f4
Author: Atish Patra <atishp@rivosinc.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Add isa extenstion strings to the device tree
The Linux kernel parses the ISA extensions from "riscv,isa" DT
property. It used to parse only the single letter base extensions
until now. A generic ISA extension parsing framework was proposed[1]
recently that can parse multi-letter ISA extensions as well.
Generate the extended ISA string by appending the available ISA extensions
to the "riscv,isa" string if it is enabled so that kernel can process it.
[1] https://lkml.org/lkml/2022/2/15/263
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Suggested-by: Heiko Stubner <heiko@sntech.de>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220329195657.1725425-1-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fcd6be0db563e42af6ce3222e22e7840afb6a891
https://github.com/qemu/qemu/commit/fcd6be0db563e42af6ce3222e22e7840afb6a891
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
The spec for vmv<nf>r.v says: 'the instructions operate as if EEW=SEW,
EMUL = NREG, effective length evl= EMUL * VLEN/SEW.'
So the start byte for vstart != 0 should take sew into account
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220330021316.18223-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ecfe00ec9cb468f351549f3a469484c0a3a427fd
https://github.com/qemu/qemu/commit/ecfe00ec9cb468f351549f3a469484c0a3a427fd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Use cpu_loop_exit_restore directly from mmu faults
The riscv_raise_exception function stores its argument into
exception_index and then exits to the main loop. When we
have already set exception_index, we can just exit directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220401125948.79292-2-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: db44d454a69b91b78169e40a05468e07007105d4
https://github.com/qemu/qemu/commit/db44d454a69b91b78169e40a05468e07007105d4
Author: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: virt: Exit if the user provided -bios in combination with KVM
The -bios option is silently ignored if used in combination with -enable-kvm.
The reason is that the machine starts in S-Mode, and the bios typically runs in
M-Mode.
Better exit in that case to not confuse the user.
Signed-off-by: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Message-Id: <20220401121842.2791796-1-ralf.ramsauer@oth-regensburg.de>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 91eedfb9639515504e0b41bdef1a6578dbb3f2a2
https://github.com/qemu/qemu/commit/91eedfb9639515504e0b41bdef1a6578dbb3f2a2
Author: Nicolas Pitre <nico@fluxnic.net>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv/pmp: fix NAPOT range computation overflow
There is an overflow with the current code where a pmpaddr value of
0x1fffffff is decoded as sa=0 and ea=0 whereas it should be sa=0 and
ea=0xffffffff.
Fix that by simplifying the computation. There is in fact no need for
ctz64() nor special case for -1 to achieve proper results.
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <rq81o86n-17ps-92no-p65o-79o88476266@syhkavp.arg>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: be940cc39ae8be9bfe49135957c8c0e0204f4049
https://github.com/qemu/qemu/commit/be940cc39ae8be9bfe49135957c8c0e0204f4049
Author: Niklas Cassel <niklas.cassel@wdc.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled
The device tree property "mmu-type" is currently exported as either
"riscv,sv32" or "riscv,sv48".
However, the riscv cpu device tree binding [1] has a specific value
"riscv,none" for a HART without a MMU.
Set the device tree property "mmu-type" to "riscv,none" when the CPU mmu
option is disabled using rv32,mmu=off or rv64,mmu=off.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/cpus.yaml?h=v5.17
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220414155510.1364147-1-niklas.cassel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 096f53634f986d06cae26a90dcd916c70b4f21e6
https://github.com/qemu/qemu/commit/096f53634f986d06cae26a90dcd916c70b4f21e6
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/intc/riscv_aclint.c
Log Message:
-----------
hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT
If device's MemoryRegion doesn't have .impl.[min|max]_access_size
declaration, the default access_size_min would be 1 byte and
access_size_max would be 4 bytes (see: softmmu/memory.c).
This will cause a 64-bit memory access to ACLINT to be splitted into
two 32-bit memory accesses.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Message-Id: <20220420080901.14655-2-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8f32c8dfec12ee1e2274b2480f8fb1c14ae31401
https://github.com/qemu/qemu/commit/8f32c8dfec12ee1e2274b2480f8fb1c14ae31401
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/intc/riscv_aclint.c
Log Message:
-----------
hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT
RISC-V privilege spec defines that:
* In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part
of the register.
* For RV64, naturally aligned 64-bit memory accesses to the mtime and
mtimecmp registers are additionally supported and are atomic.
It's possible to perform both 32/64-bit read/write accesses to both
mtimecmp and mtime registers.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Message-Id: <20220420080901.14655-3-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8f19f79dc6dc87b2a939cecb3e9442fc817dcddf
https://github.com/qemu/qemu/commit/8f19f79dc6dc87b2a939cecb3e9442fc817dcddf
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/intc/riscv_aclint.c
M include/hw/intc/riscv_aclint.h
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
Log Message:
-----------
hw/intc: Make RISC-V ACLINT mtime MMIO register writable
RISC-V privilege spec defines that mtime is exposed as a memory-mapped
machine-mode read-write register. However, as QEMU uses host monotonic
timer as timer source, this makes mtime to be read-only in RISC-V
ACLINT.
This patch makes mtime to be writable by recording the time delta value
between the mtime value to be written and the timer value at the time
mtime is written. Time delta value is then added back whenever the timer
value is retrieved.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220420080901.14655-4-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9fdd835482e3a2a5f1fa5e66126b9a9fecfef561
https://github.com/qemu/qemu/commit/9fdd835482e3a2a5f1fa5e66126b9a9fecfef561
Author: Jim Shu <jim.shu@sifive.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/intc/riscv_aclint.c
Log Message:
-----------
hw/intc: riscv_aclint: Add reset function of ACLINT devices
This commit implements reset function of all ACLINT devices.
ACLINT device reset will clear MTIME and MSIP register to 0.
Depend on RISC-V ACLINT spec v1.0-rc4:
https://github.com/riscv/riscv-aclint/blob/v1.0-rc4/riscv-aclint.adoc
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220420080901.14655-5-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 606c5a31c15c838b8d4ee9eefdb01ad3a2da4171
https://github.com/qemu/qemu/commit/606c5a31c15c838b8d4ee9eefdb01ad3a2da4171
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/debug.c
M target/riscv/debug.h
Log Message:
-----------
target/riscv: debug: Implement debug related TCGCPUOps
Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint}
TCGCPUOps and hook them into riscv_tcg_ops.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421003324.1134983-2-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f4dadc5b7235fa534c7d7d1738e3b94100f3c091
https://github.com/qemu/qemu/commit/f4dadc5b7235fa534c7d7d1738e3b94100f3c091
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: cpu: Add a config option for native debug
Add a config option to enable support for native M-mode debug.
This is disabled by default and can be enabled with 'debug=true'.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421003324.1134983-3-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3742d9dfaf1b0cd628ad8f7de107b0f1a065703f
https://github.com/qemu/qemu/commit/3742d9dfaf1b0cd628ad8f7de107b0f1a065703f
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/csr.c
M target/riscv/debug.c
M target/riscv/debug.h
Log Message:
-----------
target/riscv: csr: Hook debug CSR read/write
This adds debug CSR read/write support to the RISC-V CSR RW table.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421003324.1134983-4-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 058cce47ef7940001309a573515f24f6b4c6cf7f
https://github.com/qemu/qemu/commit/058cce47ef7940001309a573515f24f6b4c6cf7f
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/machine.c
Log Message:
-----------
target/riscv: machine: Add debug state description
Add a subsection to machine.c to migrate debug CSR state.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421003324.1134983-5-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f50ffc309fa3b4caad540c8d671f85dd9601312c
https://github.com/qemu/qemu/commit/f50ffc309fa3b4caad540c8d671f85dd9601312c
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: cpu: Enable native debug feature
Turn on native debug feature by default for all CPUs.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421003324.1134983-6-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 6d09cd8c5ea665b6cfe4363346a040eba2ad5463
https://github.com/qemu/qemu/commit/6d09cd8c5ea665b6cfe4363346a040eba2ad5463
Author: Bin Meng <bin.meng@windriver.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M include/hw/core/tcg-cpu-ops.h
Log Message:
-----------
hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
This is now used by RISC-V as well. Update the comments.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421003324.1134983-7-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e63e7b6cca93242a4d037610caba5626c980b990
https://github.com/qemu/qemu/commit/e63e7b6cca93242a4d037610caba5626c980b990
Author: Dylan Jhong <dylan@andestech.com>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/riscv/boot.c
M include/hw/riscv/boot.h
Log Message:
-----------
hw/riscv: boot: Support 64bit fdt address.
The current riscv_load_fdt() forces fdt_load_addr to be placed at a dram
address within 3GB,
but not all platforms have dram_base within 3GB.
This patch adds an exception for dram base not within 3GB,
which will place fdt at dram_end align 16MB.
riscv_setup_rom_reset_vec() also needs to be modified
Signed-off-by: Dylan Jhong <dylan@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220419115945.37945-1-dylan@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 91636947da10c147cbc80dac4ce4585894522392
https://github.com/qemu/qemu/commit/91636947da10c147cbc80dac4ce4585894522392
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-04-21 (Thu, 21 Apr 2022)
Changed paths:
M hw/intc/riscv_aclint.c
M hw/riscv/boot.c
M hw/riscv/opentitan.c
M hw/riscv/virt.c
A hw/ssi/ibex_spi_host.c
M hw/ssi/meson.build
M hw/ssi/trace-events
M include/hw/core/tcg-cpu-ops.h
M include/hw/intc/riscv_aclint.h
M include/hw/riscv/boot.h
M include/hw/riscv/opentitan.h
A include/hw/ssi/ibex_spi_host.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
A target/riscv/debug.c
A target/riscv/debug.h
M target/riscv/helper.h
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/machine.c
M target/riscv/meson.build
M target/riscv/pmp.c
M target/riscv/vector_helper.c
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20220421' of
https://github.com/alistair23/qemu into staging
First RISC-V PR for QEMU 7.1
* Add support for Ibex SPI to OpenTitan
* Add support for privileged spec version 1.12.0
* Use privileged spec version 1.12.0 for virt machine by default
* Allow software access to MIP SEIP
* Add initial support for the Sdtrig extension
* Optimisations for vector extensions
* Improvements to the misa ISA string
* Add isa extenstion strings to the device tree
* Don't allow `-bios` options with KVM machines
* Fix NAPOT range computation overflow
* Fix DT property mmu-type when CPU mmu option is disabled
* Make RISC-V ACLINT mtime MMIO register writable
* Add and enable native debug feature
* Support 64bit fdt address.
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# =sihI
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 20 Apr 2022 11:35:47 PM PDT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>"
[undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* tag 'pull-riscv-to-apply-20220421' of https://github.com/alistair23/qemu: (31
commits)
hw/riscv: boot: Support 64bit fdt address.
hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
target/riscv: cpu: Enable native debug feature
target/riscv: machine: Add debug state description
target/riscv: csr: Hook debug CSR read/write
target/riscv: cpu: Add a config option for native debug
target/riscv: debug: Implement debug related TCGCPUOps
hw/intc: riscv_aclint: Add reset function of ACLINT devices
hw/intc: Make RISC-V ACLINT mtime MMIO register writable
hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT
hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT
hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled
target/riscv/pmp: fix NAPOT range computation overflow
hw/riscv: virt: Exit if the user provided -bios in combination with KVM
target/riscv: Use cpu_loop_exit_restore directly from mmu faults
target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
target/riscv: Add isa extenstion strings to the device tree
target/riscv: misa to ISA string conversion fix
target/riscv: optimize helper for vmv<nr>r.v
target/riscv: optimize condition assign for scale < 0
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/b1efff6bf031...91636947da10
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