[Qemu-commits] [qemu/qemu] ef95a2: hw/ppc: free env->tb_env in spapr_unrealize_vcpu()

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: ef95a244949a15b831876fe2d4e1320784729819
      
https://github.com/qemu/qemu/commit/ef95a244949a15b831876fe2d4e1320784729819
  Author: Daniel Henrique Barboza <danielhb413@gmail.com>
  Date:   2022-04-04 (Mon, 04 Apr 2022)

  Changed paths:
    M hw/ppc/ppc.c
    M hw/ppc/spapr_cpu_core.c
    M include/hw/ppc/ppc.h

  Log Message:
  -----------
  hw/ppc: free env->tb_env in spapr_unrealize_vcpu()

The timebase is allocated during spapr_realize_vcpu() and it's not
freed. This results in memory leaks when doing vcpu unplugs:

==636935==
==636935== 144 (96 direct, 48 indirect) bytes in 1 blocks are definitely lost 
in loss record 6
,461 of 8,135
==636935==    at 0x4897468: calloc (vg_replace_malloc.c:760)
==636935==    by 0x5077213: g_malloc0 (in /usr/lib64/libglib-2.0.so.0.6400.4)
==636935==    by 0x507757F: g_malloc0_n (in /usr/lib64/libglib-2.0.so.0.6400.4)
==636935==    by 0x93C3FB: cpu_ppc_tb_init (ppc.c:1066)
==636935==    by 0x97BC2B: spapr_realize_vcpu (spapr_cpu_core.c:268)
==636935==    by 0x97C01F: spapr_cpu_core_realize (spapr_cpu_core.c:337)
==636935==    by 0xD4626F: device_set_realized (qdev.c:531)
==636935==    by 0xD55273: property_set_bool (object.c:2273)
==636935==    by 0xD523DF: object_property_set (object.c:1408)
==636935==    by 0xD588B7: object_property_set_qobject (qom-qobject.c:28)
==636935==    by 0xD52897: object_property_set_bool (object.c:1477)
==636935==    by 0xD4579B: qdev_realize (qdev.c:333)
==636935==

This patch adds a cpu_ppc_tb_free() helper in hw/ppc/ppc.c to allow us
to free the timebase. This leak is then solved by calling
cpu_ppc_tb_free() in spapr_unrealize_vcpu().

Fixes: 6f4b5c3ec590 ("spapr: CPU hot unplug support")
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220329124545.529145-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 7e5157696b97a5431ef8786e01bffe989c05493b
      
https://github.com/qemu/qemu/commit/7e5157696b97a5431ef8786e01bffe989c05493b
  Author: Frederic Barrat <fbarrat@linux.ibm.com>
  Date:   2022-04-04 (Mon, 04 Apr 2022)

  Changed paths:
    M include/hw/pci-host/pnv_phb4.h

  Log Message:
  -----------
  ppc/pnv: Fix number of registers in the PCIe controller on POWER9

The spec defines 3 registers, even though only index 0 and 2 are valid
on POWER9. The same model is used on POWER10. Register 1 is defined
there but we currently don't use it in skiboot. So we can keep
reporting an error on write.

Reported by Coverity (CID 1487176).

Fixes: 4f9924c4d4cf ("ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge")
Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220401091925.770803-1-fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 0798da8df9fd917515c957ae918d6d979cf5f3fb
      
https://github.com/qemu/qemu/commit/0798da8df9fd917515c957ae918d6d979cf5f3fb
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-04-04 (Mon, 04 Apr 2022)

  Changed paths:
    M linux-user/ppc/signal.c

  Log Message:
  -----------
  linux-user/ppc: Narrow type of ccr in save_user_regs

Coverity warns that we shift a 32-bit value by N, and then
accumulate it into a 64-bit type (target_ulong on ppc64).

The ccr is always 8 * 4-bit fields, and thus is always a
32-bit quantity; narrow the type to avoid the warning.

Fixes: Coverity CID 1487223
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220401191643.330393-1-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 20661b75ea6093f5e59079d00a778a972d6732c5
      
https://github.com/qemu/qemu/commit/20661b75ea6093f5e59079d00a778a972d6732c5
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-04-04 (Mon, 04 Apr 2022)

  Changed paths:
    M hw/ppc/ppc.c
    M hw/ppc/spapr_cpu_core.c
    M include/hw/pci-host/pnv_phb4.h
    M include/hw/ppc/ppc.h
    M linux-user/ppc/signal.c

  Log Message:
  -----------
  Merge tag 'pull-ppc-20220404' of https://github.com/legoater/qemu into staging

ppc-7.0 queue:

* Coverity fixes
* Fix for a memory leak issue

# gpg: Signature made Mon 04 Apr 2022 09:45:51 BST
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-ppc-20220404' of https://github.com/legoater/qemu:
  linux-user/ppc: Narrow type of ccr in save_user_regs
  ppc/pnv: Fix number of registers in the PCIe controller on POWER9
  hw/ppc: free env->tb_env in spapr_unrealize_vcpu()

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/bc6ec396d471...20661b75ea60