[Qemu-commits] [qemu/qemu] b17ab4: target/arm: Fix sve2 ldnt1 and stnt1

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[Qemu-commits] [qemu/qemu] b17ab4: target/arm: Fix sve2 ldnt1 and stnt1

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] b17ab4: target/arm: Fix sve2 ldnt1 and stnt1
Date:	Sat, 19 Mar 2022 03:09:37 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: b17ab4705c78484d1bdd86cd9c1f7d42338cc1f1
      
https://github.com/qemu/qemu/commit/b17ab4705c78484d1bdd86cd9c1f7d42338cc1f1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M target/arm/sve.decode
    M target/arm/translate-sve.c
    M tests/tcg/aarch64/Makefile.target
    A tests/tcg/aarch64/test-826.c
    M tests/tcg/configure.sh

  Log Message:
  -----------
  target/arm: Fix sve2 ldnt1 and stnt1

For both ldnt1 and stnt1, the meaning of the Rn and Rm are different
from ld1 and st1: the vector and integer registers are reversed, and
the integer register 31 refers to XZR instead of SP.

Secondly, the 64-bit version of ldnt1 was being interpreted as
32-bit unpacked unscaled offset instead of 64-bit unscaled offset,
which discarded the upper 32 bits of the address coming from
the vector argument.

Thirdly, validate that the memory element size is in range for the
vector element size for ldnt1.  For ld1, we do this via independent
decode patterns, but for ldnt1 we need to do it manually.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/826
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220308031655.240710-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c179d3be7bd03edb717c4b953faa285513b6301f
      
https://github.com/qemu/qemu/commit/c179d3be7bd03edb717c4b953faa285513b6301f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M target/arm/pauth_helper.c

  Log Message:
  -----------
  target/arm: Fix pauth_check_trap vs SEL2

When arm_is_el2_enabled was introduced, we missed
updating pauth_check_trap.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/788
Fixes: e6ef0169264b ("target/arm: use arm_is_el2_enabled() where applicable")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220315021205.342768-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 39a1fd25287f5dece59fdf4752491faf59310296
      
https://github.com/qemu/qemu/commit/39a1fd25287f5dece59fdf4752491faf59310296
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Fix handling of LPAE block descriptors

LPAE descriptors come in three forms:

 * table descriptors, giving the address of the next level page table
 * page descriptors, which occur only at level 3 and describe the
   mapping of one page (which might be 4K, 16K or 64K)
 * block descriptors, which occur at higher page table levels, and
   describe the mapping of huge pages

QEMU's page-table-walk code treats block and page entries
identically, simply ORing in a number of bits from the input virtual
address that depends on the level of the page table that we stopped
at; we depend on the previous masking of descaddr with descaddrmask
to have already cleared out the low bits of the descriptor word.

This is not quite right: the address field in a block descriptor is
smaller, and so there are bits which are valid address bits in a page
descriptor or a table descriptor but which are not supposed to be
part of the address in a block descriptor, and descaddrmask does not
clear them.  We previously mostly got away with this because those
descriptor bits are RES0; however with FEAT_BBM (part of Armv8.4)
block descriptor bit 16 is defined to be the nT bit.  No emulated
QEMU CPU has FEAT_BBM yet, but if the host CPU has it then we might
see it when using KVM or hvf.

Explicitly zero out all the descaddr bits we're about to OR vaddr
bits into.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/790
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220304165628.2345765-1-peter.maydell@linaro.org


  Commit: 9a09273f3324c37f05e9af505cb788a6d1f546c4
      
https://github.com/qemu/qemu/commit/9a09273f3324c37f05e9af505cb788a6d1f546c4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M hw/dma/xlnx_csu_dma.c

  Log Message:
  -----------
  hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size

In commit 00f05c02f9e7342f we gave the TYPE_XLNX_CSU_DMA object its
own class struct, but forgot to update the TypeInfo::class_size
accordingly.  This meant that not enough memory was allocated for the
class struct, and the initialization of xcdc->read in the class init
function wrote off the end of the memory. Add the missing line.

Found by running 'check-qtest-aarch64' with a clang
address-sanitizer build, which complains:

==2542634==ERROR: AddressSanitizer: heap-buffer-overflow on address 
0x61000000ab00 at pc 0x559a20aebc29 bp 0x7fff97df74d0 sp 0x7fff97df74c8
WRITE of size 8 at 0x61000000ab00 thread T0
    #0 0x559a20aebc28 in xlnx_csu_dma_class_init 
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../hw/dma/xlnx_csu_dma.c:722:16
    #1 0x559a21bf297c in type_initialize 
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:365:9
    #2 0x559a21bf3442 in object_class_foreach_tramp 
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1070:5
    #3 0x7f09bcb641b7 in g_hash_table_foreach 
(/usr/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x401b7)
    #4 0x559a21bf3c27 in object_class_foreach 
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1092:5
    #5 0x559a21bf3c27 in object_class_get_list 
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1149:5
    #6 0x559a2081a2fd in select_machine 
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/vl.c:1661:24
    #7 0x559a2081a2fd in qemu_create_machine 
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/vl.c:2146:35
    #8 0x559a2081a2fd in qemu_init 
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/vl.c:3706:5
    #9 0x559a20720ed5 in main 
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/main.c:49:5
    #10 0x7f09baec00b2 in __libc_start_main 
/build/glibc-sMfBJT/glibc-2.31/csu/../csu/libc-start.c:308:16
    #11 0x559a2067673d in _start 
(/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/qemu-system-aarch64+0xf4b73d)

0x61000000ab00 is located 0 bytes to the right of 192-byte region 
[0x61000000aa40,0x61000000ab00)
allocated by thread T0 here:
    #0 0x559a206eeff2 in calloc 
(/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/qemu-system-aarch64+0xfc3ff2)
    #1 0x7f09bcb7bef0 in g_malloc0 
(/usr/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x57ef0)
    #2 0x559a21bf3442 in object_class_foreach_tramp 
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1070:5

Fixes: 00f05c02f9e7342f ("hw/dma/xlnx_csu_dma: Support starting a read transfer 
through a class method")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220308150207.2546272-1-peter.maydell@linaro.org


  Commit: 75f7ba165cea75594eb6bd5210119abe0d4c198a
      
https://github.com/qemu/qemu/commit/75f7ba165cea75594eb6bd5210119abe0d4c198a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M hw/misc/npcm7xx_clk.c

  Log Message:
  -----------
  hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init()

In npcm7xx_clk_sel_init() we allocate a string with g_strdup_printf().
Use g_autofree so we free it rather than leaking it.

(Detected with the clang leak sanitizer.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220308170302.2582820-1-peter.maydell@linaro.org


  Commit: e422d92a23c543e9649feba227eec58a5aaba483
      
https://github.com/qemu/qemu/commit/e422d92a23c543e9649feba227eec58a5aaba483
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M scripts/nsis.py

  Log Message:
  -----------
  nsis installer: List emulators in alphabetical order

We currently list the emulators in the Windows installer's dialog
in an essentially random order (it's whatever glob.glob() returns
them to, which is filesystem-implementation-dependent). Add a
call to sorted() so they appear in alphabetical order.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: John Snow <jsnow@redhat.com>
Message-id: 20220305105743.2384766-2-peter.maydell@linaro.org


  Commit: 6b98e86e8773dbbcf34275b066e8fd63cb4c2f15
      
https://github.com/qemu/qemu/commit/6b98e86e8773dbbcf34275b066e8fd63cb4c2f15
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M qemu.nsi

  Log Message:
  -----------
  nsis installer: Suppress "ANSI targets are deprecated" warning

When we build our Windows installer, it emits the warning:

   warning 7998: ANSI targets are deprecated

Fix this by making our installer a Unicode installer instead.  These
won't work on Win95/98/ME, but we already do not support those.

See
https://nsis.sourceforge.io/Docs/Chapter4.html#aunicodetarget
for the documentation of the Unicode directive.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Message-id: 20220305105743.2384766-3-peter.maydell@linaro.org


  Commit: c08796378d59210499441628a8596467dde87b86
      
https://github.com/qemu/qemu/commit/c08796378d59210499441628a8596467dde87b86
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M qemu.nsi
    M scripts/nsis.py

  Log Message:
  -----------
  nsis installer: Fix mouse-over descriptions for emulators

We use the nsis.py script to write out an installer script Section
for each emulator executable, so the exact set of Sections depends on
which executables were built.  However the part of qemu.nsi which
specifies mouse-over descriptions for each Section still has a
hard-coded and very outdated list (with just i386 and alpha).  This
causes two problems.  Firstly, if you build the installer for a
configuration where you didn't build the i386 binaries you get
warnings like this:
  warning 6000: unknown variable/constant "{Section_i386}" detected, ignoring 
(macro:_==:1)
  warning 6000: unknown variable/constant "{Section_i386w}" detected, ignoring 
(macro:_==:1)
(this happens in our gitlab CI jobs, for instance).
Secondly, most of the emulators in the generated installer don't have
any mouseover text.

Make nsis.py generate a second output file which has the necessary
MUI_DESCRIPTION_TEXT lines for each Section it creates, so we can
include that at the right point in qemu.nsi to set the mouse-over
text.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: John Snow <jsnow@redhat.com>
Message-id: 20220305105743.2384766-4-peter.maydell@linaro.org


  Commit: 16d91e06b37fca0772866e12d4e146a519841b0f
      
https://github.com/qemu/qemu/commit/16d91e06b37fca0772866e12d4e146a519841b0f
  Author: Eric Auger <eric.auger@redhat.com>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M hw/intc/Kconfig
    M hw/intc/meson.build

  Log Message:
  -----------
  hw/intc: Rename CONFIG_ARM_GIC_TCG into CONFIG_ARM_GICV3_TCG

CONFIG_ARM_GIC_TCG actually guards the compilation of TCG GICv3
specific files. So let's rename it into CONFIG_ARM_GICV3_TCG

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20220308182452.223473-2-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 299b4a3ecf1c7dcc57e55150d4cb234340749854
      
https://github.com/qemu/qemu/commit/299b4a3ecf1c7dcc57e55150d4cb234340749854
  Author: Eric Auger <eric.auger@redhat.com>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset

In TCG mode, if gic-version=max we always select GICv3 even if
CONFIG_ARM_GICV3_TCG is unset. We shall rather select GICv2.
This also brings the benefit of fixing qos tests errors for tests
using gic-version=max with CONFIG_ARM_GICV3_TCG unset.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20220308182452.223473-3-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8cc2246caa6c3eb56b250293aea212cf91c38490
      
https://github.com/qemu/qemu/commit/8cc2246caa6c3eb56b250293aea212cf91c38490
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/m_helper.c

  Log Message:
  -----------
  target/arm: Log M-profile vector table accesses

Currently the CPU_LOG_INT logging misses some useful information
about loads from the vector table.  Add logging where we load vector
table entries.  This is particularly helpful for cases where the user
has accidentally not put a vector table in their image at all, which
can result in confusing guest crashes at startup.

Here's an example of the new logging for a case where
the vector table contains garbage:

Loaded reset SP 0x0 PC 0x0 from vector table
Loaded reset SP 0xd008f8df PC 0xf000bf00 from vector table
Taking exception 3 [Prefetch Abort] on CPU 0
...with CFSR.IACCVIOL
...BusFault with BFSR.STKERR
...taking pending nonsecure exception 3
...loading from element 3 of non-secure vector table at 0xc
...loaded new PC 0x20000558
----------------
IN:
0x20000558:  08000079  stmdaeq  r0, {r0, r3, r4, r5, r6}

(The double reset logging is the result of our long-standing
"CPUs all get reset twice" weirdness; it looks a bit ugly
but it'll go away if we ever fix that :-))

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20220315204306.2797684-2-peter.maydell@linaro.org


  Commit: 654abaa783bcd668aab5e0455170af7c65f86a32
      
https://github.com/qemu/qemu/commit/654abaa783bcd668aab5e0455170af7c65f86a32
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M target/arm/m_helper.c

  Log Message:
  -----------
  target/arm: Log fault address for M-profile faults

For M-profile, the fault address is not always exposed to the guest
in a fault register (for instance the BFAR bus fault address register
is only updated for bus faults on data accesses, not instruction
accesses).  Currently we log the address only if we're putting it
into a particular guest-visible register.  Since we always have it,
log it generically, to make logs of i-side faults a bit clearer.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20220315204306.2797684-3-peter.maydell@linaro.org


  Commit: c28d4b8656c836b5b166b35e4c48ff26d9405b59
      
https://github.com/qemu/qemu/commit/c28d4b8656c836b5b166b35e4c48ff26d9405b59
  Author: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  hw/arm/xlnx-zynqmp: Add an unimplemented SERDES area

Add an unimplemented SERDES (Serializer/Deserializer) area.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20220316164645.2303510-2-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 4a7319b750d2a465c9697fb0c72584c5d4e9073a
      
https://github.com/qemu/qemu/commit/4a7319b750d2a465c9697fb0c72584c5d4e9073a
  Author: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Make rvbar settable after realize

Make the rvbar property settable after realize. This is done
in preparation to model the ZynqMP's runtime configurable rvbar.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20220316164645.2303510-3-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 152f0bf0c90130cbe4aeaa1c74f586fb9606647c
      
https://github.com/qemu/qemu/commit/152f0bf0c90130cbe4aeaa1c74f586fb9606647c
  Author: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M hw/misc/meson.build
    A hw/misc/xlnx-zynqmp-crf.c
    A include/hw/misc/xlnx-zynqmp-crf.h

  Log Message:
  -----------
  hw/misc: Add a model of the Xilinx ZynqMP CRF

Add a model of the Xilinx ZynqMP CRF. At the moment this
is mostly a stub model.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20220316164645.2303510-4-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 63320bcaed89642044500ec017c0acb592220831
      
https://github.com/qemu/qemu/commit/63320bcaed89642044500ec017c0acb592220831
  Author: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF

Connect the ZynqMP CRF - Clock Reset FPD device.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20220316164645.2303510-5-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b4ecda2dd79b3ee8747d5dc935c28738ab9297a9
      
https://github.com/qemu/qemu/commit/b4ecda2dd79b3ee8747d5dc935c28738ab9297a9
  Author: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M hw/misc/meson.build
    A hw/misc/xlnx-zynqmp-apu-ctrl.c
    A include/hw/misc/xlnx-zynqmp-apu-ctrl.h

  Log Message:
  -----------
  hw/misc: Add a model of the Xilinx ZynqMP APU Control

Add a model of the Xilinx ZynqMP APU Control.

Reviewed-by: Luc Michel <luc@lmichel.fr>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20220316164645.2303510-6-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: eb7a38ba664c8ab7f216fa701a0bea897d433763
      
https://github.com/qemu/qemu/commit/eb7a38ba664c8ab7f216fa701a0bea897d433763
  Author: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control

Connect the ZynqMP APU Control device.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20220316164645.2303510-7-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8900c204df0e521361e2bd31131d5f9089d08000
      
https://github.com/qemu/qemu/commit/8900c204df0e521361e2bd31131d5f9089d08000
  Author: Andrew Deason <adeason@sinenomine.net>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M include/qemu/osdep.h
    M meson.build
    M util/osdep.c

  Log Message:
  -----------
  util/osdep: Avoid madvise proto on modern Solaris

On older Solaris releases (before Solaris 11), we didn't get a
prototype for madvise, and so util/osdep.c provides its own prototype.
Some time between the public Solaris 11.4 release and Solaris 11.4.42
CBE, we started getting an madvise prototype that looks like this:

    extern int madvise(void *, size_t, int);

which conflicts with the prototype in util/osdeps.c. Instead of always
declaring this prototype, check if we're missing the madvise()
prototype, and only declare it ourselves if the prototype is missing.
Move the prototype to include/qemu/osdep.h, the normal place to handle
platform-specific header quirks.

The 'missing_madvise_proto' meson check contains an obviously wrong
prototype for madvise. So if that code compiles and links, we must be
missing the actual prototype for madvise.

Signed-off-by: Andrew Deason <adeason@sinenomine.net>
Message-id: 20220316035227.3702-2-adeason@sinenomine.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9c2d83f5a0ef558f8882998af6cb800101243655
      
https://github.com/qemu/qemu/commit/9c2d83f5a0ef558f8882998af6cb800101243655
  Author: Andrew Deason <adeason@sinenomine.net>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M hw/i386/acpi-build.c

  Log Message:
  -----------
  hw/i386/acpi-build: Avoid 'sun' identifier

On Solaris, 'sun' is #define'd to 1, which causes errors if a variable
is named 'sun'. Slightly change the name of the var for the Slot User
Number so we can build on Solaris.

Reviewed-by: Ani Sinha <ani@anisinha.ca>
Signed-off-by: Andrew Deason <adeason@sinenomine.net>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-id: 20220316035227.3702-3-adeason@sinenomine.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 79d54c9eac04c554e3c081589542f801ace71797
      
https://github.com/qemu/qemu/commit/79d54c9eac04c554e3c081589542f801ace71797
  Author: Andrew Deason <adeason@sinenomine.net>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M util/osdep.c

  Log Message:
  -----------
  util/osdep: Remove some early cruft

The include for statvfs.h has not been needed since all statvfs calls
were removed in commit 4a1418e07bdc ("Unbreak large mem support by
removing kqemu").

The comment mentioning CONFIG_BSD hasn't made sense since an include
for config-host.h was removed in commit aafd75841001 ("util: Clean up
includes").

Remove this cruft.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrew Deason <adeason@sinenomine.net>
Message-id: 20220316035227.3702-4-adeason@sinenomine.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a09863610aefe17390612b7d78d3fba20e43b53e
      
https://github.com/qemu/qemu/commit/a09863610aefe17390612b7d78d3fba20e43b53e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M hw/arm/virt.c
    M hw/arm/xlnx-zynqmp.c
    M hw/dma/xlnx_csu_dma.c
    M hw/i386/acpi-build.c
    M hw/intc/Kconfig
    M hw/intc/meson.build
    M hw/misc/meson.build
    M hw/misc/npcm7xx_clk.c
    A hw/misc/xlnx-zynqmp-apu-ctrl.c
    A hw/misc/xlnx-zynqmp-crf.c
    M include/hw/arm/xlnx-zynqmp.h
    A include/hw/misc/xlnx-zynqmp-apu-ctrl.h
    A include/hw/misc/xlnx-zynqmp-crf.h
    M include/qemu/osdep.h
    M meson.build
    M qemu.nsi
    M scripts/nsis.py
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/m_helper.c
    M target/arm/pauth_helper.c
    M target/arm/sve.decode
    M target/arm/translate-sve.c
    M tests/tcg/aarch64/Makefile.target
    A tests/tcg/aarch64/test-826.c
    M tests/tcg/configure.sh
    M util/osdep.c

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20220318' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Fix sve2 ldnt1 and stnt1
 * Fix pauth_check_trap vs SEL2
 * Fix handling of LPAE block descriptors
 * hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size
 * hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init()
 * nsis installer: List emulators in alphabetical order
 * nsis installer: Suppress "ANSI targets are deprecated" warning
 * nsis installer: Fix mouse-over descriptions for emulators
 * hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset
 * Improve M-profile vector table access logging
 * Xilinx ZynqMP: model CRF and APU control
 * Fix compile issues on modern Solaris

# gpg: Signature made Fri 18 Mar 2022 13:18:20 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20220318' of 
https://git.linaro.org/people/pmaydell/qemu-arm: (21 commits)
  util/osdep: Remove some early cruft
  hw/i386/acpi-build: Avoid 'sun' identifier
  util/osdep: Avoid madvise proto on modern Solaris
  hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control
  hw/misc: Add a model of the Xilinx ZynqMP APU Control
  hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF
  hw/misc: Add a model of the Xilinx ZynqMP CRF
  target/arm: Make rvbar settable after realize
  hw/arm/xlnx-zynqmp: Add an unimplemented SERDES area
  target/arm: Log fault address for M-profile faults
  target/arm: Log M-profile vector table accesses
  hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset
  hw/intc: Rename CONFIG_ARM_GIC_TCG into CONFIG_ARM_GICV3_TCG
  nsis installer: Fix mouse-over descriptions for emulators
  nsis installer: Suppress "ANSI targets are deprecated" warning
  nsis installer: List emulators in alphabetical order
  hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init()
  hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size
  target/arm: Fix handling of LPAE block descriptors
  target/arm: Fix pauth_check_trap vs SEL2
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/1d60bb4b1460...a09863610aef
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