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[Qemu-commits] [qemu/qemu] a66669: tcg/s390x: Fix tcg_out_dupi_vec vs VG
From: |
Peter Maydell |
Subject: |
[Qemu-commits] [qemu/qemu] a66669: tcg/s390x: Fix tcg_out_dupi_vec vs VGM |
Date: |
Mon, 14 Mar 2022 11:28:20 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: a66669c942077d53414ae0894e9fba3ddc18f58d
https://github.com/qemu/qemu/commit/a66669c942077d53414ae0894e9fba3ddc18f58d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-14 (Mon, 14 Mar 2022)
Changed paths:
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Fix tcg_out_dupi_vec vs VGM
The immediate operands to VGM were in the wrong order,
producing an inverse mask.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6e5f9fb7993aa3de5295ae2dbada39258ed333ac
https://github.com/qemu/qemu/commit/6e5f9fb7993aa3de5295ae2dbada39258ed333ac
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-14 (Mon, 14 Mar 2022)
Changed paths:
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Fix INDEX_op_bitsel_vec vs VSEL
The operands are output in the wrong order: the tcg selector
argument is first, whereas the s390x selector argument is last.
Tested-by: Thomas Huth <thuth@redhat.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/898
Fixes: 9bca986df88 ("tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6e591a8569b24309f0b602042cce630524c03c0e
https://github.com/qemu/qemu/commit/6e591a8569b24309f0b602042cce630524c03c0e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-14 (Mon, 14 Mar 2022)
Changed paths:
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Fix tcg_out_dup_vec vs general registers
We copied the data from the general register input to the
vector register output, but have not yet replicated it.
We intended to fall through into the vector-vector case,
but failed to redirect the input register.
This is caught by an assertion failure in tcg_out_insn_VRIc,
which diagnosed the incorrect register class.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 76cff100beeae8d3676bb658cccd45ef5ced8aa9
https://github.com/qemu/qemu/commit/76cff100beeae8d3676bb658cccd45ef5ced8aa9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-14 (Mon, 14 Mar 2022)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1
The LDRD (register) instruction is UNPREDICTABLE if the Rm register
is the same as either Rt or Rt+1 (the two registers being loaded to).
We weren't making sure we avoided this, with the result that on some
host CPUs like the Cortex-A7 we would get a SIGILL because the CPU
chooses to UNDEF for this particular UNPREDICTABLE case.
Since we've already checked that datalo is aligned, we can simplify
the test vs the Rm operand by aligning it before comparison. Check
for the two orderings before falling back to two ldr instructions.
We don't bother to do anything similar for tcg_out_ldrd_rwb(),
because it is only used in tcg_out_tlb_read() with a fixed set of
registers which don't overlap.
There is no equivalent UNPREDICTABLE case for STRD.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/896
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6f4fe14b46f0a161f94e3f6e98690ac38184b0be
https://github.com/qemu/qemu/commit/6f4fe14b46f0a161f94e3f6e98690ac38184b0be
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-03-14 (Mon, 14 Mar 2022)
Changed paths:
M tcg/arm/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
Merge tag 'pull-tcg-20220314' of https://gitlab.com/rth7680/qemu into staging
Fixes for s390x host vectors
Fix for arm ldrd unpredictable case
# gpg: Signature made Mon 14 Mar 2022 17:32:44 GMT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20220314' of https://gitlab.com/rth7680/qemu:
tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1
tcg/s390x: Fix tcg_out_dup_vec vs general registers
tcg/s390x: Fix INDEX_op_bitsel_vec vs VSEL
tcg/s390x: Fix tcg_out_dupi_vec vs VGM
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/352998df1c53...6f4fe14b46f0
- [Qemu-commits] [qemu/qemu] a66669: tcg/s390x: Fix tcg_out_dupi_vec vs VGM,
Peter Maydell <=