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[Qemu-commits] [qemu/qemu] 2c7059: whpx: Fixed reporting of the CPU cont

From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 2c7059: whpx: Fixed reporting of the CPU context to GDB fo...
Date: Thu, 10 Mar 2022 01:28:33 -0800 
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 2c7059fde813e5462d43ea278bf1b4bbeefb66a0
      
https://github.com/qemu/qemu/commit/2c7059fde813e5462d43ea278bf1b4bbeefb66a0
  Author: Ivan Shcherbakov <ivan@sysprogs.com>
  Date:   2022-03-01 (Tue, 01 Mar 2022)

  Changed paths:
    M target/i386/whpx/whpx-all.c

  Log Message:
  -----------
  whpx: Fixed reporting of the CPU context to GDB for 64-bit

Make sure that pausing the VM while in 64-bit mode will set the
HF_CS64_MASK flag in env->hflags (see x86_update_hflags() in
target/i386/cpu.c).

Without it, the code in gdbstub.c would only use the 32-bit register values
when debugging 64-bit targets, making debugging effectively impossible.

Signed-off-by: Ivan Shcherbakov <ivan@sysprogs.com>
Message-Id: <00f701d82874$68b02000$3a106000$@sysprogs.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: 0ea2a9ad210148f2a8797772bc172936872fe246
      
https://github.com/qemu/qemu/commit/0ea2a9ad210148f2a8797772bc172936872fe246
  Author: Ivan Shcherbakov <ivan@sysprogs.com>
  Date:   2022-03-01 (Tue, 01 Mar 2022)

  Changed paths:
    M target/i386/whpx/whpx-all.c

  Log Message:
  -----------
  whpx: Fixed incorrect CR8/TPR synchronization

This fixes the following error triggered when stopping and resuming a 64-bit
Linux kernel via gdb:

qemu-system-x86_64.exe: WHPX: Failed to set virtual processor context, 
hr=c0350005

The previous logic for synchronizing the values did not take into account
that the lower 4 bits of the CR8 register, containing the priority level,
mapped to bits 7:4 of the APIC.TPR register (see section 10.8.6.1 of
Volume 3 of Intel 64 and IA-32 Architectures Software Developer's Manual).
The caused WHvSetVirtualProcessorRegisters() to fail with an error,
effectively preventing GDB from changing the guest context.

Signed-off-by: Ivan Shcherbakov <ivan@sysprogs.com>
Message-Id: <010b01d82874$bb4ef160$31ecd420$@sysprogs.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: 9f5deb3c6011950145d23f7e18d76e34ffef7d3a
      
https://github.com/qemu/qemu/commit/9f5deb3c6011950145d23f7e18d76e34ffef7d3a
  Author: Vitaly Kuznetsov <vkuznets@redhat.com>
  Date:   2022-03-01 (Tue, 01 Mar 2022)

  Changed paths:
    M scripts/kvm/vmxcap

  Log Message:
  -----------
  vmxcap: Add 5-level EPT bit

5-level EPT is present in Icelake Server CPUs and is supported by QEMU
('vmx-page-walk-5').

Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Message-Id: <20220221145316.576138-2-vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: 41422372fe7ef1208da60d5734d9db8060c0d815
      
https://github.com/qemu/qemu/commit/41422372fe7ef1208da60d5734d9db8060c0d815
  Author: Marc-André Lureau <marcandre.lureau@redhat.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M meson.build

  Log Message:
  -----------
  meson: fix generic location of vss headers

This is a left-over, despite requesting the change before the merge.

Fixes: commit 8821a389 ("configure, meson: replace VSS SDK checks and options 
with --enable-vss-sdk")
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20220222194008.610377-2-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: b5216e6b9c9400b93032e7cd96e3ef6060f9024a
      
https://github.com/qemu/qemu/commit/b5216e6b9c9400b93032e7cd96e3ef6060f9024a
  Author: Marc-André Lureau <marcandre.lureau@redhat.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M meson.build
    M qga/vss-win32/install.cpp
    M qga/vss-win32/provider.cpp
    M qga/vss-win32/vss-common.h

  Log Message:
  -----------
  qga/vss-win32: check old VSS SDK headers

The VssCoordinator & VssAdmin interfaces have been moved to vsadmin.h in
the Windows SDK.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20220222194008.610377-3-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: ae2434bfa40b86e002e1be8b78e2d670989bd40c
      
https://github.com/qemu/qemu/commit/ae2434bfa40b86e002e1be8b78e2d670989bd40c
  Author: Marc-André Lureau <marcandre.lureau@redhat.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M qga/meson.build

  Log Message:
  -----------
  qga/vss: update informative message about MinGW

The headers are now all available in MinGW master branch.
(commit 13390dbbf885f and earlier) aiming for 10.0.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20220222194008.610377-4-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: 8ba67932b9cb7c1149e710d43db0e3bc48ea7c42
      
https://github.com/qemu/qemu/commit/8ba67932b9cb7c1149e710d43db0e3bc48ea7c42
  Author: Paolo Bonzini <pbonzini@redhat.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M scripts/meson-buildoptions.sh

  Log Message:
  -----------
  update meson-buildoptions.sh

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: af4cb5b0c99c39a9affd8fab170e594c71a8fc8e
      
https://github.com/qemu/qemu/commit/af4cb5b0c99c39a9affd8fab170e594c71a8fc8e
  Author: Longpeng(Mike) <longpeng2@huawei.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M include/sysemu/kvm.h

  Log Message:
  -----------
  kvm-irqchip: introduce new API to support route change

Paolo suggested adding the new API to support route changes [1]. We should 
invoke
kvm_irqchip_begin_route_changes() before changing the routes, increasing the
KVMRouteChange.changes if the routes are changed, and commit the changes at 
last.

[1] https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg02898.html

Signed-off-by: Longpeng <longpeng2@huawei.com>
Message-Id: <20220222141116.2091-2-longpeng2@huawei.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: b9e0617a09b96904ae14974f4e70eb032acfe42f
      
https://github.com/qemu/qemu/commit/b9e0617a09b96904ae14974f4e70eb032acfe42f
  Author: Longpeng(Mike) <longpeng2@huawei.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M accel/kvm/kvm-all.c
    M accel/stubs/kvm-stub.c
    M hw/misc/ivshmem.c
    M hw/vfio/pci.c
    M hw/virtio/virtio-pci.c
    M include/sysemu/kvm.h
    M target/i386/kvm/kvm.c

  Log Message:
  -----------
  kvm/msi: do explicit commit when adding msi routes

We invoke the kvm_irqchip_commit_routes() for each addition to MSI route
table, which is not efficient if we are adding lots of routes in some cases.

This patch lets callers invoke the kvm_irqchip_commit_routes(), so the
callers can decide how to optimize.

[1] https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg00967.html

Signed-off-by: Longpeng <longpeng2@huawei.com>
Message-Id: <20220222141116.2091-3-longpeng2@huawei.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: 551da65b5ab4dd07fe32644fe6fc30bea2ef912b
      
https://github.com/qemu/qemu/commit/551da65b5ab4dd07fe32644fe6fc30bea2ef912b
  Author: Paolo Bonzini <pbonzini@redhat.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M target/i386/tcg/sysemu/excp_helper.c

  Log Message:
  -----------
  target/i386: only include bits in pg_mode if they are not ignored

LA57/PKE/PKS is only relevant in 64-bit mode, and NXE is only relevant if
PAE is in use.  Since there is code that checks PG_MODE_LA57 to determine
the canonicality of addresses, make sure that the bit is not set by
mistake in 32-bit mode.  While it would not be a problem because 32-bit
addresses by definition fit in both 48-bit and 57-bit address spaces,
it is nicer if get_pg_mode() actually returns whether a feature is enabled,
and it allows a few simplifications in the page table walker.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: 9e685c6c574a9e1f1e3affbb900f7c38fb4bff6e
      
https://github.com/qemu/qemu/commit/9e685c6c574a9e1f1e3affbb900f7c38fb4bff6e
  Author: Gareth Webb <gareth.webb@umbralsoftware.co.uk>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M target/i386/tcg/seg_helper.c
    M target/i386/tcg/sysemu/excp_helper.c

  Log Message:
  -----------
  target/i386: Throw a #SS when loading a non-canonical IST

Loading a non-canonical address into rsp when handling an interrupt or
performing a far call should raise a #SS not a #GP.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/870
Signed-off-by: Gareth Webb <gareth.webb@umbralsoftware.co.uk>
Message-Id: <164529651121.25406.15337137068584246397-0@git.sr.ht>
[Move get_pg_mode to seg_helper.c for user-mode emulators. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: 6b9d93e016bb744b92ac12aeaa781083cc2df6d3
      
https://github.com/qemu/qemu/commit/6b9d93e016bb744b92ac12aeaa781083cc2df6d3
  Author: Paolo Bonzini <pbonzini@redhat.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M linux-headers/asm-x86/kvm.h
    M linux-headers/linux/kvm.h

  Log Message:
  -----------
  linux-headers: include missing changes from 5.17

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: 4e5ff5030b4402f6e7d5b5bebb60819725c662a2
      
https://github.com/qemu/qemu/commit/4e5ff5030b4402f6e7d5b5bebb60819725c662a2
  Author: Jing Liu <jing2.liu@intel.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M target/i386/cpu.c
    M target/i386/cpu.h
    M target/i386/kvm/kvm-cpu.c

  Log Message:
  -----------
  x86: Fix the 64-byte boundary enumeration for extended state

The extended state subleaves (EAX=0Dh, ECX=n, n>1).ECX[1]
indicate whether the extended state component locates
on the next 64-byte boundary following the preceding state
component when the compacted format of an XSAVE area is
used.

Right now, they are all zero because no supported component
needed the bit to be set, but the upcoming AMX feature will
use it.  Fix the subleaves value according to KVM's supported
cpuid.

Signed-off-by: Jing Liu <jing2.liu@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20220217060434.52460-2-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: 9c37cd5f945b02af234d5cbe4324672455637997
      
https://github.com/qemu/qemu/commit/9c37cd5f945b02af234d5cbe4324672455637997
  Author: Jing Liu <jing2.liu@intel.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M target/i386/cpu.c
    M target/i386/cpu.h

  Log Message:
  -----------
  x86: Add AMX XTILECFG and XTILEDATA components

The AMX TILECFG register and the TMMx tile data registers are
saved/restored via XSAVE, respectively in state component 17
(64 bytes) and state component 18 (8192 bytes).

Add AMX feature bits to x86_ext_save_areas array to set
up AMX components. Add structs that define the layout of
AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the
structs sizes.

Signed-off-by: Jing Liu <jing2.liu@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20220217060434.52460-3-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: d37adda192317d97bdde3c2c5c32e519c7df6c51
      
https://github.com/qemu/qemu/commit/d37adda192317d97bdde3c2c5c32e519c7df6c51
  Author: Yang Zhong <yang.zhong@intel.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M target/i386/cpu.c
    M target/i386/cpu.h
    M target/i386/kvm/kvm-cpu.c
    M target/i386/kvm/kvm.c
    M target/i386/kvm/kvm_i386.h

  Log Message:
  -----------
  x86: Grant AMX permission for guest

Kernel allocates 4K xstate buffer by default. For XSAVE features
which require large state component (e.g. AMX), Linux kernel
dynamically expands the xstate buffer only after the process has
acquired the necessary permissions. Those are called dynamically-
enabled XSAVE features (or dynamic xfeatures).

There are separate permissions for native tasks and guests.

Qemu should request the guest permissions for dynamic xfeatures
which will be exposed to the guest. This only needs to be done
once before the first vcpu is created.

KVM implemented one new ARCH_GET_XCOMP_SUPP system attribute API to
get host side supported_xcr0 and Qemu can decide if it can request
dynamically enabled XSAVE features permission.
https://lore.kernel.org/all/20220126152210.3044876-1-pbonzini@redhat.com/

Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Signed-off-by: Jing Liu <jing2.liu@intel.com>
Message-Id: <20220217060434.52460-4-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: ee1a4bfdd34a2bb12052fbbd0c4786c498e0034d
      
https://github.com/qemu/qemu/commit/ee1a4bfdd34a2bb12052fbbd0c4786c498e0034d
  Author: Jing Liu <jing2.liu@intel.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M target/i386/cpu.c
    M target/i386/cpu.h

  Log Message:
  -----------
  x86: Add XFD faulting bit for state components

Intel introduces XFD faulting mechanism for extended
XSAVE features to dynamically enable the features in
runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set
as 1, it indicates support for XFD faulting of this
state component.

Signed-off-by: Jing Liu <jing2.liu@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20220217060434.52460-5-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: f931881489aa08e11d6354dd418659b62ca6f1c5
      
https://github.com/qemu/qemu/commit/f931881489aa08e11d6354dd418659b62ca6f1c5
  Author: Jing Liu <jing2.liu@intel.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M target/i386/cpu.c
    M target/i386/kvm/kvm.c

  Log Message:
  -----------
  x86: Add AMX CPUIDs enumeration

Add AMX primary feature bits XFD and AMX_TILE to
enumerate the CPU's AMX capability. Meanwhile, add
AMX TILE and TMUL CPUID leaf and subleaves which
exist when AMX TILE is present to provide the maximum
capability of TILE and TMUL.

Signed-off-by: Jing Liu <jing2.liu@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20220217060434.52460-6-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: 3be96463cacf9fb26e389a11e4eee77823063b8b
      
https://github.com/qemu/qemu/commit/3be96463cacf9fb26e389a11e4eee77823063b8b
  Author: Jing Liu <jing2.liu@intel.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M target/i386/cpu.h
    M target/i386/kvm/kvm.c
    M target/i386/xsave_helper.c

  Log Message:
  -----------
  x86: add support for KVM_CAP_XSAVE2 and AMX state migration

When dynamic xfeatures (e.g. AMX) are used by the guest, the xsave
area would be larger than 4KB. KVM_GET_XSAVE2 and KVM_SET_XSAVE
under KVM_CAP_XSAVE2 works with a xsave buffer larger than 4KB.
Always use the new ioctls under KVM_CAP_XSAVE2 when KVM supports it.

Signed-off-by: Jing Liu <jing2.liu@intel.com>
Signed-off-by: Zeng Guang <guang.zeng@intel.com>
Signed-off-by: Wei Wang <wei.w.wang@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20220217060434.52460-7-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: f655d8aa04fa0361499753d0e005fac5630e488a
      
https://github.com/qemu/qemu/commit/f655d8aa04fa0361499753d0e005fac5630e488a
  Author: Zeng Guang <guang.zeng@intel.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M target/i386/cpu.h
    M target/i386/kvm/kvm.c
    M target/i386/machine.c

  Log Message:
  -----------
  x86: Support XFD and AMX xsave data migration

XFD(eXtended Feature Disable) allows to enable a
feature on xsave state while preventing specific
user threads from using the feature.

Support save and restore XFD MSRs if CPUID.D.1.EAX[4]
enumerate to be valid. Likewise migrate the MSRs and
related xsave state necessarily.

Signed-off-by: Zeng Guang <guang.zeng@intel.com>
Signed-off-by: Wei Wang <wei.w.wang@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20220217060434.52460-8-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: 7952149a4e6f56770ed9c4419a268c697565a533
      
https://github.com/qemu/qemu/commit/7952149a4e6f56770ed9c4419a268c697565a533
  Author: Vitaly Kuznetsov <vkuznets@redhat.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: Add Icelake-Server-v6 CPU model with 5-level EPT support

Windows 11 with WSL2 enabled (Hyper-V) fails to boot with Icelake-Server
{-v5} CPU model but boots well with '-cpu host'. Apparently, it expects
5-level paging and 5-level EPT support to come in pair but QEMU's
Icelake-Server CPU model lacks the later. Introduce 'Icelake-Server-v6'
CPU model with 'vmx-page-walk-5' enabled by default.

Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Message-Id: <20220221145316.576138-1-vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: e4723d8eb5d6fbe39dec3b2d058b95ca98201fc0
      
https://github.com/qemu/qemu/commit/e4723d8eb5d6fbe39dec3b2d058b95ca98201fc0
  Author: Maxim Levitsky <mlevitsk@redhat.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  KVM: SVM: always set MSR_AMD64_TSC_RATIO to default value

Even when the feature is not supported in guest CPUID,
still set the msr to the default value which will
be the only value KVM will accept in this case

Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
Message-Id: <20220223115824.319821-1-mlevitsk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: d722beb6ac1d457bfa3d7dd5bce7bcea5ea45540
      
https://github.com/qemu/qemu/commit/d722beb6ac1d457bfa3d7dd5bce7bcea5ea45540
  Author: Paolo Bonzini <pbonzini@redhat.com>
  Date:   2022-03-08 (Tue, 08 Mar 2022)

  Changed paths:
    M .gitlab-ci.d/buildtest.yml

  Log Message:
  -----------
  gitlab-ci: do not run tests with address sanitizer

This is flaky and sometimes fails or hangs unexplicably.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: 521526a9c900e96ed80c0154ae6956e222d59112
      
https://github.com/qemu/qemu/commit/521526a9c900e96ed80c0154ae6956e222d59112
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-10 (Thu, 10 Mar 2022)

  Changed paths:
    M .gitlab-ci.d/buildtest.yml
    M accel/kvm/kvm-all.c
    M accel/stubs/kvm-stub.c
    M hw/misc/ivshmem.c
    M hw/vfio/pci.c
    M hw/virtio/virtio-pci.c
    M include/sysemu/kvm.h
    M linux-headers/asm-x86/kvm.h
    M linux-headers/linux/kvm.h
    M meson.build
    M qga/meson.build
    M qga/vss-win32/install.cpp
    M qga/vss-win32/provider.cpp
    M qga/vss-win32/vss-common.h
    M scripts/kvm/vmxcap
    M scripts/meson-buildoptions.sh
    M target/i386/cpu.c
    M target/i386/cpu.h
    M target/i386/kvm/kvm-cpu.c
    M target/i386/kvm/kvm.c
    M target/i386/kvm/kvm_i386.h
    M target/i386/machine.c
    M target/i386/tcg/seg_helper.c
    M target/i386/tcg/sysemu/excp_helper.c
    M target/i386/whpx/whpx-all.c
    M target/i386/xsave_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into 
staging

* whpx fixes in preparation for GDB support (Ivan)
* VSS header fixes (Marc-André)
* 5-level EPT support (Vitaly)
* AMX support (Jing Liu & Yang Zhong)
* Bundle changes to MSI routes (Longpeng)
* More precise emulation of #SS (Gareth)
* Disable ASAN testing

# gpg: Signature made Tue 08 Mar 2022 11:34:15 GMT
# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini-gitlab/tags/for-upstream: (22 commits)
  gitlab-ci: do not run tests with address sanitizer
  KVM: SVM: always set MSR_AMD64_TSC_RATIO to default value
  i386: Add Icelake-Server-v6 CPU model with 5-level EPT support
  x86: Support XFD and AMX xsave data migration
  x86: add support for KVM_CAP_XSAVE2 and AMX state migration
  x86: Add AMX CPUIDs enumeration
  x86: Add XFD faulting bit for state components
  x86: Grant AMX permission for guest
  x86: Add AMX XTILECFG and XTILEDATA components
  x86: Fix the 64-byte boundary enumeration for extended state
  linux-headers: include missing changes from 5.17
  target/i386: Throw a #SS when loading a non-canonical IST
  target/i386: only include bits in pg_mode if they are not ignored
  kvm/msi: do explicit commit when adding msi routes
  kvm-irqchip: introduce new API to support route change
  update meson-buildoptions.sh
  qga/vss: update informative message about MinGW
  qga/vss-win32: check old VSS SDK headers
  meson: fix generic location of vss headers
  vmxcap: Add 5-level EPT bit
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

# Conflicts:
#       accel/stubs/kvm-stub.c


Compare: https://github.com/qemu/qemu/compare/2048c4eba2b4...521526a9c900
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