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[Qemu-commits] [qemu/qemu] 1c6c3b: util: Make qemu_oom_check() a static


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 1c6c3b: util: Make qemu_oom_check() a static function
Date: Tue, 08 Mar 2022 09:09:06 -0800

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 1c6c3b764d992ecd9cb44f8646d74935269d20a6
      
https://github.com/qemu/qemu/commit/1c6c3b764d992ecd9cb44f8646d74935269d20a6
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M include/qemu-common.h
    M util/oslib-posix.c
    M util/oslib-win32.c

  Log Message:
  -----------
  util: Make qemu_oom_check() a static function

The qemu_oom_check() function, which we define in both oslib-posix.c
and oslib-win32.c, is now used only locally in that file; make it
static.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220226180723.1706285-3-peter.maydell@linaro.org


  Commit: ac8057a11b81195f22602e2f0fa720baed79a41e
      
https://github.com/qemu/qemu/commit/ac8057a11b81195f22602e2f0fa720baed79a41e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    A util/memalign.c
    M util/meson.build
    M util/oslib-posix.c
    M util/oslib-win32.c

  Log Message:
  -----------
  util: Unify implementations of qemu_memalign()

We implement qemu_memalign() in both oslib-posix.c and oslib-win32.c,
but the two versions are essentially the same: they call
qemu_try_memalign(), and abort() after printing an error message if
it fails.  The only difference is that the win32 version prints the
GetLastError() value whereas the POSIX version prints
strerror(errno).  However, this is a bug in the win32 version: in
commit dfbd0b873a85021 in 2020 we changed the implementation of
qemu_try_memalign() from using VirtualAlloc() (which sets the
GetLastError() value) to using _aligned_malloc() (which sets errno),
but didn't update the error message to match.

Replace the two separate functions with a single version in a
new memalign.c file, which drops the unnecessary extra qemu_oom_check()
function and instead prints a more useful message including the
requested size and alignment as well as the errno string.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220226180723.1706285-4-peter.maydell@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: bc0fecc1c2f2c70780e38b3f821dc5b89eed0716
      
https://github.com/qemu/qemu/commit/bc0fecc1c2f2c70780e38b3f821dc5b89eed0716
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M util/oslib-posix.c
    M util/oslib-win32.c

  Log Message:
  -----------
  util: Return valid allocation for qemu_try_memalign() with zero size

Currently qemu_try_memalign()'s behaviour if asked to allocate
0 bytes is rather variable:
 * on Windows, we will assert
 * on POSIX platforms, we get the underlying behaviour of
   the posix_memalign() or equivalent function, which may be
   either "return a valid non-NULL pointer" or "return NULL"

Explictly check for 0 byte allocations, so we get consistent
behaviour across platforms.  We handle them by incrementing the size
so that we return a valid non-NULL pointer that can later be passed
to qemu_vfree().  This is permitted behaviour for the
posix_memalign() API and is the most usual way that underlying
malloc() etc implementations handle a zero-sized allocation request,
because it won't trip up calling code that assumes NULL means an
error.  (This includes our own qemu_memalign(), which will abort on
NULL.)

This change is a preparation for sharing the qemu_try_memalign() code
between Windows and POSIX.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 8698343b867224c1742d75dfdc276061c5839dc8
      
https://github.com/qemu/qemu/commit/8698343b867224c1742d75dfdc276061c5839dc8
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M meson.build

  Log Message:
  -----------
  meson.build: Don't misdetect posix_memalign() on Windows

Currently we incorrectly think that posix_memalign() exists on
Windows.  This is because of a combination of:

 * the msys2/mingw toolchain/libc claim to have a
   __builtin_posix_memalign when there isn't a builtin of that name
 * meson will assume that if you have a __builtin_foo that
   counts for has_function('foo')

Specifying a specific include file via prefix: causes meson to not
treat builtins as sufficient and actually look for the function
itself; see this meson pull request which added that as the official
way to get the right answer:
  https://github.com/mesonbuild/meson/pull/1150

Currently this misdectection doesn't cause problems because we only
use CONFIG_POSIX_MEMALIGN in oslib-posix.c; however that will change
in a following commit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220226180723.1706285-6-peter.maydell@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 5c8c714a0a78dfd0bb7b04e796b96eb5d41f1292
      
https://github.com/qemu/qemu/commit/5c8c714a0a78dfd0bb7b04e796b96eb5d41f1292
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M meson.build
    M util/memalign.c
    M util/oslib-posix.c
    M util/oslib-win32.c

  Log Message:
  -----------
  util: Share qemu_try_memalign() implementation between POSIX and Windows

The qemu_try_memalign() functions for POSIX and Windows used to be
significantly different, but these days they are identical except for
the actual allocation function called, and the POSIX version already
has to have ifdeffery for different allocation functions.

Move to a single implementation in memalign.c, which uses the Windows
_aligned_malloc if we detect that function in meson.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220226180723.1706285-7-peter.maydell@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 88454f844efe26ea8ac7f394a72b1e6620dccf7e
      
https://github.com/qemu/qemu/commit/88454f844efe26ea8ac7f394a72b1e6620dccf7e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M meson.build
    M util/memalign.c

  Log Message:
  -----------
  util: Use meson checks for valloc() and memalign() presence

Instead of assuming that all CONFIG_BSD have valloc() and anything
else is memalign(), explicitly check for those functions in
meson.build and use the "is the function present" define.  Tests for
specific functionality are better than which-OS checks; this also
lets us give a helpful error message if somehow there's no usable
function present.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220226180723.1706285-8-peter.maydell@linaro.org


  Commit: 1a11265d7e854203652606b671a0e02ba100a249
      
https://github.com/qemu/qemu/commit/1a11265d7e854203652606b671a0e02ba100a249
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M util/memalign.c
    M util/oslib-posix.c
    M util/oslib-win32.c

  Log Message:
  -----------
  util: Put qemu_vfree() in memalign.c

qemu_vfree() is the companion free function to qemu_memalign(); put
it in memalign.c so the allocation and free functions are together.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220226180723.1706285-9-peter.maydell@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 5df022cf2e5e24910a7d579d5780ae78bc24f247
      
https://github.com/qemu/qemu/commit/5df022cf2e5e24910a7d579d5780ae78bc24f247
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M block/blkverify.c
    M block/block-copy.c
    M block/commit.c
    M block/crypto.c
    M block/dmg.c
    M block/export/fuse.c
    M block/file-posix.c
    M block/io.c
    M block/mirror.c
    M block/nvme.c
    M block/parallels-ext.c
    M block/parallels.c
    M block/qcow.c
    M block/qcow2-cache.c
    M block/qcow2-cluster.c
    M block/qcow2-refcount.c
    M block/qcow2-snapshot.c
    M block/qcow2.c
    M block/qed-l2-cache.c
    M block/qed-table.c
    M block/qed.c
    M block/quorum.c
    M block/raw-format.c
    M block/vdi.c
    M block/vhdx-log.c
    M block/vhdx.c
    M block/vmdk.c
    M block/vpc.c
    M block/win32-aio.c
    M hw/block/dataplane/xen-block.c
    M hw/block/fdc.c
    M hw/ide/core.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_softmmu.c
    M hw/scsi/scsi-disk.c
    M hw/tpm/tpm_ppi.c
    A include/qemu/memalign.h
    M include/qemu/osdep.h
    M nbd/server.c
    M net/l2tpv3.c
    M plugins/loader.c
    M qemu-img.c
    M qemu-io-cmds.c
    M qom/object.c
    M softmmu/physmem.c
    M target/i386/hvf/hvf.c
    M target/i386/kvm/kvm.c
    M tcg/region.c
    M tests/bench/atomic_add-bench.c
    M tests/bench/qht-bench.c
    M util/atomic64.c
    M util/memalign.c
    M util/qht.c

  Log Message:
  -----------
  osdep: Move memalign-related functions to their own header

Move the various memalign-related functions out of osdep.h and into
their own header, which we include only where they are used.
While we're doing this, add some brief documentation comments.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220226180723.1706285-10-peter.maydell@linaro.org


  Commit: c64ee036ac215f970a76e8c51cb1cfaaef70feb5
      
https://github.com/qemu/qemu/commit/c64ee036ac215f970a76e8c51cb1cfaaef70feb5
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M target/arm/translate-neon.c

  Log Message:
  -----------
  target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero

For VLD1/VST1 (single element to one lane) we are only accessing one
register, and so the 'stride' is meaningless.  The bits that would
specify stride (insn bit [4] for size=1, bit [6] for size=2) are
specified to be zero in the encoding (which would correspond to a
stride of 1 for VLD2/VLD3/VLD4 etc), and we must UNDEF if they are
not.

We failed to make this check, which meant that we would incorrectly
handle some instruction patterns as loads or stores instead of
UNDEFing them. Enforce that stride == 1 for the nregs == 1 case.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/890
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220303113741.2156877-2-peter.maydell@linaro.org


  Commit: 41c5a0f791ef4d9377ec5b952931a1c75df7a815
      
https://github.com/qemu/qemu/commit/41c5a0f791ef4d9377ec5b952931a1c75df7a815
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M target/arm/translate-neon.c

  Log Message:
  -----------
  target/arm/translate-neon: Simplify align field check for VLD3

For VLD3 (single 3-element structure to one lane), there is no
alignment specification and the alignment bits in the instruction
must be zero.  This is bit [4] for the size=0 and size=1 cases, and
bits [5:4] for the size=2 case.  We do this check correctly in
VLDST_single(), but we write it a bit oddly: in the 'case 3' code we
check for bit 0 of a->align (bit [4] of the insn), and then we fall
through to the 'case 2' code which checks bit 1 of a->align (bit [5]
of the insn) in the size 2 case.  Replace this with just checking "is
a->align non-zero" for VLD3, which lets us drop the fall-through and
put the cases in this switch in numerical order.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220303113741.2156877-3-peter.maydell@linaro.org


  Commit: e40509801d4f0b17fac641a07696ecb41421b3dc
      
https://github.com/qemu/qemu/commit/e40509801d4f0b17fac641a07696ecb41421b3dc
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M hw/intc/arm_gicv3_its.c
    M hw/intc/trace-events

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Add trace events for commands

When debugging code that's using the ITS, it's helpful to
see tracing of the ITS commands that the guest executes. Add
suitable trace events.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220303202341.2232284-2-peter.maydell@linaro.org


  Commit: 930f40e90bbc9f8f3818219cc8a17c3afe84d719
      
https://github.com/qemu/qemu/commit/930f40e90bbc9f8f3818219cc8a17c3afe84d719
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M hw/intc/arm_gicv3_its.c
    M hw/intc/trace-events

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Add trace events for table reads and writes

For debugging guest use of the ITS, it can be helpful to trace
when the ITS reads and writes the in-memory tables.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220303202341.2232284-3-peter.maydell@linaro.org


  Commit: 31164ebf08d87b59c570af5b2c80e91940a70968
      
https://github.com/qemu/qemu/commit/31164ebf08d87b59c570af5b2c80e91940a70968
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M hw/intc/arm_gicv3.c

  Log Message:
  -----------
  hw/intc/arm_gicv3: Specify valid and impl in MemoryRegionOps

The GICv3 has some registers that support byte accesses, and some
that support 8-byte accesses.  Our TCG implementation implements all
of this, switching on the 'size' argument and handling the registers
that must support reads of that size while logging an error for
attempted accesses to registers that do not support that size access.
However we forgot to tell the core memory subsystem about this by
specifying the .impl and .valid fields in the MemoryRegionOps struct,
so the core was happily simulating 8 byte accesses by combining two 4
byte accesses.  This doesn't have much guest-visible effect, since
there aren't many 8 byte registers and they all support being written
in two 4 byte parts.

Set the .impl and .valid fields to say that all sizes from 1 to 8
bytes are both valid and implemented by the device.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220303202341.2232284-4-peter.maydell@linaro.org


  Commit: b45f91e1a70e70f482ed75b50e24850591db2e5e
      
https://github.com/qemu/qemu/commit/b45f91e1a70e70f482ed75b50e24850591db2e5e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M hw/intc/arm_gicv3_dist.c
    M hw/intc/arm_gicv3_its.c

  Log Message:
  -----------
  hw/intc/arm_gicv3: Fix missing spaces in error log messages

We forgot a space in some log messages, so the output ended
up looking like
gicv3_dist_write: invalid guest write at offset 0000000000008000size 8

with a missing space before "size". Add the missing spaces.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220303202341.2232284-5-peter.maydell@linaro.org


  Commit: cf734c2a0f6a61dd22639416a5295d0e0fd8a7cd
      
https://github.com/qemu/qemu/commit/cf734c2a0f6a61dd22639416a5295d0e0fd8a7cd
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M hw/intc/arm_gicv3_cpuif.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace event

The trace_gicv3_icv_hppir_read trace event takes an integer value
which it uses to form the register name, which should be either
ICV_HPPIR0 or ICV_HPPIR1.  We were passing in the 'grp' variable for
this, but that is either GICV3_G0 or GICV3_G1NS, which happen to be 0
and 2, which meant that tracing for the ICV_HPPIR1 register was
incorrectly printed as ICV_HPPIR2.

Use the same approach we do for all the other similar trace events,
and pass in 'ri->crm == 8 ?  0 : 1', deriving the index value
directly from the ARMCPRegInfo struct.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220303202341.2232284-6-peter.maydell@linaro.org


  Commit: 99eb313ddbbcf73c1adcdadceba1423b691c6d05
      
https://github.com/qemu/qemu/commit/99eb313ddbbcf73c1adcdadceba1423b691c6d05
  Author: Akihiko Odaki <akihiko.odaki@gmail.com>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M ui/cocoa.m

  Log Message:
  -----------
  ui/cocoa: Use the standard about panel

This provides standard look and feel for the about panel and reduces
code.

Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Message-id: 20220227042241.1543-1-akihiko.odaki@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 69b2265d5fe8e0f401d75e175e0a243a7d505e53
      
https://github.com/qemu/qemu/commit/69b2265d5fe8e0f401d75e175e0a243a7d505e53
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M tests/avocado/boot_linux.py

  Log Message:
  -----------
  target/arm: Provide cpu property for controling FEAT_LPA2

There is a Linux kernel bug present until v5.12 that prevents
booting with FEAT_LPA2 enabled.  As a workaround for TCG, allow
the feature to be disabled from -cpu max.

Since this kernel bug is present in the Fedora 31 image that
we test in avocado, disable lpa2 on the command-line.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0942820408dc788560f6968e9b5f011803b846c2
      
https://github.com/qemu/qemu/commit/0942820408dc788560f6968e9b5f011803b846c2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M hw/arm/virt.c
    M include/hw/arm/virt.h

  Log Message:
  -----------
  hw/arm/virt: Disable LPA2 for -machine virt-6.2

There is a Linux kernel bug present until v5.12 that prevents
booting with FEAT_LPA2 enabled.  As a workaround for TCG,
disable this feature for machine versions prior to 7.0.

Cc: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9740b907a5363c06ecf61e08b21966a81eb0dab4
      
https://github.com/qemu/qemu/commit/9740b907a5363c06ecf61e08b21966a81eb0dab4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-08 (Tue, 08 Mar 2022)

  Changed paths:
    M block/blkverify.c
    M block/block-copy.c
    M block/commit.c
    M block/crypto.c
    M block/dmg.c
    M block/export/fuse.c
    M block/file-posix.c
    M block/io.c
    M block/mirror.c
    M block/nvme.c
    M block/parallels-ext.c
    M block/parallels.c
    M block/qcow.c
    M block/qcow2-cache.c
    M block/qcow2-cluster.c
    M block/qcow2-refcount.c
    M block/qcow2-snapshot.c
    M block/qcow2.c
    M block/qed-l2-cache.c
    M block/qed-table.c
    M block/qed.c
    M block/quorum.c
    M block/raw-format.c
    M block/vdi.c
    M block/vhdx-log.c
    M block/vhdx.c
    M block/vmdk.c
    M block/vpc.c
    M block/win32-aio.c
    M hw/arm/virt.c
    M hw/block/dataplane/xen-block.c
    M hw/block/fdc.c
    M hw/ide/core.c
    M hw/intc/arm_gicv3.c
    M hw/intc/arm_gicv3_cpuif.c
    M hw/intc/arm_gicv3_dist.c
    M hw/intc/arm_gicv3_its.c
    M hw/intc/trace-events
    M hw/ppc/spapr.c
    M hw/ppc/spapr_softmmu.c
    M hw/scsi/scsi-disk.c
    M hw/tpm/tpm_ppi.c
    M include/hw/arm/virt.h
    M include/qemu-common.h
    A include/qemu/memalign.h
    M include/qemu/osdep.h
    M meson.build
    M nbd/server.c
    M net/l2tpv3.c
    M plugins/loader.c
    M qemu-img.c
    M qemu-io-cmds.c
    M qom/object.c
    M softmmu/physmem.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/translate-neon.c
    M target/i386/hvf/hvf.c
    M target/i386/kvm/kvm.c
    M tcg/region.c
    M tests/avocado/boot_linux.py
    M tests/bench/atomic_add-bench.c
    M tests/bench/qht-bench.c
    M ui/cocoa.m
    M util/atomic64.c
    A util/memalign.c
    M util/meson.build
    M util/oslib-posix.c
    M util/oslib-win32.c
    M util/qht.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220307' 
into staging

target-arm queue:
 * cleanups of qemu_oom_check() and qemu_memalign()
 * target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero
 * target/arm/translate-neon: Simplify align field check for VLD3
 * GICv3 ITS: add more trace events
 * GICv3 ITS: implement 8-byte accesses properly
 * GICv3: fix minor issues with some trace/log messages
 * ui/cocoa: Use the standard about panel
 * target/arm: Provide cpu property for controling FEAT_LPA2
 * hw/arm/virt: Disable LPA2 for -machine virt-6.2

# gpg: Signature made Mon 07 Mar 2022 16:46:06 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20220307:
  hw/arm/virt: Disable LPA2 for -machine virt-6.2
  target/arm: Provide cpu property for controling FEAT_LPA2
  ui/cocoa: Use the standard about panel
  hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace event
  hw/intc/arm_gicv3: Fix missing spaces in error log messages
  hw/intc/arm_gicv3: Specify valid and impl in MemoryRegionOps
  hw/intc/arm_gicv3_its: Add trace events for table reads and writes
  hw/intc/arm_gicv3_its: Add trace events for commands
  target/arm/translate-neon: Simplify align field check for VLD3
  target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero
  osdep: Move memalign-related functions to their own header
  util: Put qemu_vfree() in memalign.c
  util: Use meson checks for valloc() and memalign() presence
  util: Share qemu_try_memalign() implementation between POSIX and Windows
  meson.build: Don't misdetect posix_memalign() on Windows
  util: Return valid allocation for qemu_try_memalign() with zero size
  util: Unify implementations of qemu_memalign()
  util: Make qemu_oom_check() a static function

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/33d102e92e41...9740b907a536



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