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[Qemu-commits] [qemu/qemu] 3e0204: whpx: Fixed reporting of the CPU cont
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 3e0204: whpx: Fixed reporting of the CPU context to GDB fo... |
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Date: |
Sun, 06 Mar 2022 04:03:23 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 3e0204044db34760573e7220adf5737b0078b200
https://github.com/qemu/qemu/commit/3e0204044db34760573e7220adf5737b0078b200
Author: Ivan Shcherbakov <ivan@sysprogs.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M target/i386/whpx/whpx-all.c
Log Message:
-----------
whpx: Fixed reporting of the CPU context to GDB for 64-bit
Make sure that pausing the VM while in 64-bit mode will set the
HF_CS64_MASK flag in env->hflags (see x86_update_hflags() in
target/i386/cpu.c).
Without it, the code in gdbstub.c would only use the 32-bit register values
when debugging 64-bit targets, making debugging effectively impossible.
Signed-off-by: Ivan Shcherbakov <ivan@sysprogs.com>
Message-Id: <00f701d82874$68b02000$3a106000$@sysprogs.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 241a50e6f5f9af20303bc4253759497dd3ebc337
https://github.com/qemu/qemu/commit/241a50e6f5f9af20303bc4253759497dd3ebc337
Author: Ivan Shcherbakov <ivan@sysprogs.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M target/i386/whpx/whpx-all.c
Log Message:
-----------
whpx: Fixed incorrect CR8/TPR synchronization
This fixes the following error triggered when stopping and resuming a 64-bit
Linux kernel via gdb:
qemu-system-x86_64.exe: WHPX: Failed to set virtual processor context,
hr=c0350005
The previous logic for synchronizing the values did not take into account
that the lower 4 bits of the CR8 register, containing the priority level,
mapped to bits 7:4 of the APIC.TPR register (see section 10.8.6.1 of
Volume 3 of Intel 64 and IA-32 Architectures Software Developer's Manual).
The caused WHvSetVirtualProcessorRegisters() to fail with an error,
effectively preventing GDB from changing the guest context.
Signed-off-by: Ivan Shcherbakov <ivan@sysprogs.com>
Message-Id: <010b01d82874$bb4ef160$31ecd420$@sysprogs.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: a9fda1f9867df9caf97fad846605ad25251596ed
https://github.com/qemu/qemu/commit/a9fda1f9867df9caf97fad846605ad25251596ed
Author: Vitaly Kuznetsov <vkuznets@redhat.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
i386: Add Icelake-Server-v6 CPU model with 5-level EPT support
Windows 11 with WSL2 enabled (Hyper-V) fails to boot with Icelake-Server
{-v5} CPU model but boots well with '-cpu host'. Apparently, it expects
5-level paging and 5-level EPT support to come in pair but QEMU's
Icelake-Server CPU model lacks the later. Introduce 'Icelake-Server-v6'
CPU model with 'vmx-page-walk-5' enabled by default.
Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Message-Id: <20220221145316.576138-1-vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 1c886fa6344fb7eba6baf136a916e2a286eb67e2
https://github.com/qemu/qemu/commit/1c886fa6344fb7eba6baf136a916e2a286eb67e2
Author: Vitaly Kuznetsov <vkuznets@redhat.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M scripts/kvm/vmxcap
Log Message:
-----------
vmxcap: Add 5-level EPT bit
5-level EPT is present in Icelake Server CPUs and is supported by QEMU
('vmx-page-walk-5').
Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Message-Id: <20220221145316.576138-2-vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 201cf200fe4615ac4295193a8dfe418e152290c6
https://github.com/qemu/qemu/commit/201cf200fe4615ac4295193a8dfe418e152290c6
Author: Maxim Levitsky <mlevitsk@redhat.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
KVM: SVM: always set MSR_AMD64_TSC_RATIO to default value
Even when the feature is not supported in guest CPUID,
still set the msr to the default value which will
be the only value KVM will accept in this case
Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
Message-Id: <20220223115824.319821-1-mlevitsk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: d7d26bdef221030822268831d5f0a3ae485bd068
https://github.com/qemu/qemu/commit/d7d26bdef221030822268831d5f0a3ae485bd068
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M linux-headers/asm-x86/kvm.h
M linux-headers/linux/kvm.h
Log Message:
-----------
linux-headers: include missing changes from 5.17
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: be2f9e61478e4dfbe0437b4201c769de5041039f
https://github.com/qemu/qemu/commit/be2f9e61478e4dfbe0437b4201c769de5041039f
Author: Jing Liu <jing2.liu@intel.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/kvm-cpu.c
Log Message:
-----------
x86: Fix the 64-byte boundary enumeration for extended state
The extended state subleaves (EAX=0Dh, ECX=n, n>1).ECX[1]
indicate whether the extended state component locates
on the next 64-byte boundary following the preceding state
component when the compacted format of an XSAVE area is
used.
Right now, they are all zero because no supported component
needed the bit to be set, but the upcoming AMX feature will
use it. Fix the subleaves value according to KVM's supported
cpuid.
Signed-off-by: Jing Liu <jing2.liu@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20220217060434.52460-2-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 179fc426e4537c5e6f676f490b0096db716bdf4f
https://github.com/qemu/qemu/commit/179fc426e4537c5e6f676f490b0096db716bdf4f
Author: Jing Liu <jing2.liu@intel.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
x86: Add AMX XTILECFG and XTILEDATA components
The AMX TILECFG register and the TMMx tile data registers are
saved/restored via XSAVE, respectively in state component 17
(64 bytes) and state component 18 (8192 bytes).
Add AMX feature bits to x86_ext_save_areas array to set
up AMX components. Add structs that define the layout of
AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the
structs sizes.
Signed-off-by: Jing Liu <jing2.liu@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20220217060434.52460-3-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 7c3202091f84cf92261d0a5027a478bdf639c902
https://github.com/qemu/qemu/commit/7c3202091f84cf92261d0a5027a478bdf639c902
Author: Yang Zhong <yang.zhong@intel.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/kvm-cpu.c
M target/i386/kvm/kvm.c
M target/i386/kvm/kvm_i386.h
Log Message:
-----------
x86: Grant AMX permission for guest
Kernel allocates 4K xstate buffer by default. For XSAVE features
which require large state component (e.g. AMX), Linux kernel
dynamically expands the xstate buffer only after the process has
acquired the necessary permissions. Those are called dynamically-
enabled XSAVE features (or dynamic xfeatures).
There are separate permissions for native tasks and guests.
Qemu should request the guest permissions for dynamic xfeatures
which will be exposed to the guest. This only needs to be done
once before the first vcpu is created.
KVM implemented one new ARCH_GET_XCOMP_SUPP system attribute API to
get host side supported_xcr0 and Qemu can decide if it can request
dynamically enabled XSAVE features permission.
https://lore.kernel.org/all/20220126152210.3044876-1-pbonzini@redhat.com/
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Signed-off-by: Jing Liu <jing2.liu@intel.com>
Message-Id: <20220217060434.52460-4-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: a8cc1c1a7ededd2a3dff0472936a3eefbef20558
https://github.com/qemu/qemu/commit/a8cc1c1a7ededd2a3dff0472936a3eefbef20558
Author: Jing Liu <jing2.liu@intel.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
x86: Add XFD faulting bit for state components
Intel introduces XFD faulting mechanism for extended
XSAVE features to dynamically enable the features in
runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set
as 1, it indicates support for XFD faulting of this
state component.
Signed-off-by: Jing Liu <jing2.liu@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20220217060434.52460-5-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 168ed1d0f2e87727f2c5d5352c9b5da588d83c9f
https://github.com/qemu/qemu/commit/168ed1d0f2e87727f2c5d5352c9b5da588d83c9f
Author: Jing Liu <jing2.liu@intel.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M target/i386/cpu.c
M target/i386/kvm/kvm.c
Log Message:
-----------
x86: Add AMX CPUIDs enumeration
Add AMX primary feature bits XFD and AMX_TILE to
enumerate the CPU's AMX capability. Meanwhile, add
AMX TILE and TMUL CPUID leaf and subleaves which
exist when AMX TILE is present to provide the maximum
capability of TILE and TMUL.
Signed-off-by: Jing Liu <jing2.liu@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20220217060434.52460-6-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 4f9c00188d2e41e776dd3289554f0b77b7aa773d
https://github.com/qemu/qemu/commit/4f9c00188d2e41e776dd3289554f0b77b7aa773d
Author: Jing Liu <jing2.liu@intel.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M target/i386/cpu.h
M target/i386/kvm/kvm.c
M target/i386/xsave_helper.c
Log Message:
-----------
x86: add support for KVM_CAP_XSAVE2 and AMX state migration
When dynamic xfeatures (e.g. AMX) are used by the guest, the xsave
area would be larger than 4KB. KVM_GET_XSAVE2 and KVM_SET_XSAVE
under KVM_CAP_XSAVE2 works with a xsave buffer larger than 4KB.
Always use the new ioctls under KVM_CAP_XSAVE2 when KVM supports it.
Signed-off-by: Jing Liu <jing2.liu@intel.com>
Signed-off-by: Zeng Guang <guang.zeng@intel.com>
Signed-off-by: Wei Wang <wei.w.wang@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20220217060434.52460-7-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: b7390f6e7a0be099e084464019e45749a04b4a99
https://github.com/qemu/qemu/commit/b7390f6e7a0be099e084464019e45749a04b4a99
Author: Zeng Guang <guang.zeng@intel.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M target/i386/cpu.h
M target/i386/kvm/kvm.c
M target/i386/machine.c
Log Message:
-----------
x86: Support XFD and AMX xsave data migration
XFD(eXtended Feature Disable) allows to enable a
feature on xsave state while preventing specific
user threads from using the feature.
Support save and restore XFD MSRs if CPUID.D.1.EAX[4]
enumerate to be valid. Likewise migrate the MSRs and
related xsave state necessarily.
Signed-off-by: Zeng Guang <guang.zeng@intel.com>
Signed-off-by: Wei Wang <wei.w.wang@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20220217060434.52460-8-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 3600062b955399088cb7fd2bcfa0558466acf32d
https://github.com/qemu/qemu/commit/3600062b955399088cb7fd2bcfa0558466acf32d
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M meson.build
Log Message:
-----------
meson: fix generic location of vss headers
This is a left-over, despite requesting the change before the merge.
Fixes: commit 8821a389 ("configure, meson: replace VSS SDK checks and options
with --enable-vss-sdk")
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20220222194008.610377-2-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: bd1c4f4a75359193161062f18ceb996c7e539ce3
https://github.com/qemu/qemu/commit/bd1c4f4a75359193161062f18ceb996c7e539ce3
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M meson.build
M qga/vss-win32/install.cpp
M qga/vss-win32/provider.cpp
M qga/vss-win32/vss-common.h
Log Message:
-----------
qga/vss-win32: check old VSS SDK headers
The VssCoordinator & VssAdmin interfaces have been moved to vsadmin.h in
the Windows SDK.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20220222194008.610377-3-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 4d43a424df7af9245d84c52b5c02923dc2c0e3d2
https://github.com/qemu/qemu/commit/4d43a424df7af9245d84c52b5c02923dc2c0e3d2
Author: Marc-André Lureau <marcandre.lureau@redhat.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M qga/meson.build
Log Message:
-----------
qga/vss: update informative message about MinGW
The headers are now all available in MinGW master branch.
(commit 13390dbbf885f and earlier) aiming for 10.0.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20220222194008.610377-4-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 339f97120fb39f41a77884e0c73de06accc2aaf4
https://github.com/qemu/qemu/commit/339f97120fb39f41a77884e0c73de06accc2aaf4
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2022-02-28 (Mon, 28 Feb 2022)
Changed paths:
M scripts/meson-buildoptions.sh
Log Message:
-----------
update meson-buildoptions.sh
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 1e8f1a3dcdbfabea7f54049252c6ca1948422d52
https://github.com/qemu/qemu/commit/1e8f1a3dcdbfabea7f54049252c6ca1948422d52
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-03-06 (Sun, 06 Mar 2022)
Changed paths:
M linux-headers/asm-x86/kvm.h
M linux-headers/linux/kvm.h
M meson.build
M qga/meson.build
M qga/vss-win32/install.cpp
M qga/vss-win32/provider.cpp
M qga/vss-win32/vss-common.h
M scripts/kvm/vmxcap
M scripts/meson-buildoptions.sh
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/kvm-cpu.c
M target/i386/kvm/kvm.c
M target/i386/kvm/kvm_i386.h
M target/i386/machine.c
M target/i386/whpx/whpx-all.c
M target/i386/xsave_helper.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into
staging
* whpx fixes in preparation for GDB support
* Intel AMX support
* Optimize no-op route changes
* VSS header fixes by Marc-André
* always set MSR_AMD64_TSC_RATIO to default value
* Add 5-level EPT support to Icelake-Server CPU model and vmxcap
# gpg: Signature made Mon 28 Feb 2022 17:21:30 GMT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* remotes/bonzini-gitlab/tags/for-upstream:
update meson-buildoptions.sh
qga/vss: update informative message about MinGW
qga/vss-win32: check old VSS SDK headers
meson: fix generic location of vss headers
x86: Support XFD and AMX xsave data migration
x86: add support for KVM_CAP_XSAVE2 and AMX state migration
x86: Add AMX CPUIDs enumeration
x86: Add XFD faulting bit for state components
x86: Grant AMX permission for guest
x86: Add AMX XTILECFG and XTILEDATA components
x86: Fix the 64-byte boundary enumeration for extended state
linux-headers: include missing changes from 5.17
KVM: SVM: always set MSR_AMD64_TSC_RATIO to default value
vmxcap: Add 5-level EPT bit
i386: Add Icelake-Server-v6 CPU model with 5-level EPT support
whpx: Fixed incorrect CR8/TPR synchronization
whpx: Fixed reporting of the CPU context to GDB for 64-bit
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/9d662a6b22a0...1e8f1a3dcdbf