qemu-commits
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-commits] [qemu/qemu] 9becc3: tcg/optimize: only read val after con


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 9becc3: tcg/optimize: only read val after const check
Date: Sat, 05 Mar 2022 10:03:03 -0800

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 9becc36f0285da206150bc4f0c774f3298aaa439
      
https://github.com/qemu/qemu/commit/9becc36f0285da206150bc4f0c774f3298aaa439
  Author: Alex Bennée <alex.bennee@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M tcg/optimize.c

  Log Message:
  -----------
  tcg/optimize: only read val after const check

valgrind pointed out that arg_info()->val can be undefined which will
be the case if the arguments are not constant. The ordering of the
checks will have ensured we never relied on an undefined value but for
the sake of completeness re-order the code to be clear.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220209112142.3367525-1-alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0166feda3257b5987be62566ad1f421c6527ba67
      
https://github.com/qemu/qemu/commit/0166feda3257b5987be62566ad1f421c6527ba67
  Author: Ziqiao Kong <ziqiaokong@gmail.com>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M include/tcg/tcg.h
    M tcg/tci/tcg-target.c.inc

  Log Message:
  -----------
  tcg: Set MAX_OPC_PARAM_IARGS to 7

The last entry of DEF_HELPERS_FLAGS_n is DEF_HELPER_FLAGS_7 and
thus the MAX_OPC_PARAM_IARGS should be 7.

Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Ziqiao Kong <ziqiaokong@gmail.com>
Message-Id: <20220227113127.414533-2-ziqiaokong@gmail.com>
Fixes: e6cadf49c3d ("tcg: Add support for a helper with 7 arguments")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ed5234735af0c9ddc120ba2297e47714c5126abd
      
https://github.com/qemu/qemu/commit/ed5234735af0c9ddc120ba2297e47714c5126abd
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M include/tcg/tcg-opc.h
    M include/tcg/tcg.h
    M tcg/aarch64/tcg-target.h
    M tcg/arm/tcg-target.h
    M tcg/i386/tcg-target.h
    M tcg/optimize.c
    M tcg/ppc/tcg-target.h
    M tcg/s390x/tcg-target.h
    M tcg/tcg-op-vec.c
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Add opcodes for vector nand, nor, eqv

We've had placeholders for these opcodes for a while,
and should have support on ppc, s390x and avx512 hosts.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: fa8e90d69f94d3d54369d763200691ba8f1c1751
      
https://github.com/qemu/qemu/commit/fa8e90d69f94d3d54369d763200691ba8f1c1751
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc
    M tcg/ppc/tcg-target.h

  Log Message:
  -----------
  tcg/ppc: Implement vector NAND, NOR, EQV

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 21eab5bfaef49c6c0a8736943754e4e3a34a7139
      
https://github.com/qemu/qemu/commit/21eab5bfaef49c6c0a8736943754e4e3a34a7139
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc
    M tcg/s390x/tcg-target.h

  Log Message:
  -----------
  tcg/s390x: Implement vector NAND, NOR, EQV

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ba597b66d998910b6d6192ee556f85e52004375d
      
https://github.com/qemu/qemu/commit/ba597b66d998910b6d6192ee556f85e52004375d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M include/qemu/cpuid.h
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h

  Log Message:
  -----------
  tcg/i386: Detect AVX512

There are some operation sizes in some subsets of AVX512 that
are missing from previous iterations of AVX.  Detect them.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 08b032f7916e871d4b14cee27a809aeea85a1ebc
      
https://github.com/qemu/qemu/commit/08b032f7916e871d4b14cee27a809aeea85a1ebc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Add tcg_out_evex_opc

The evex encoding is added here, for use in a subsequent patch.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 54e2d650ddea28968160dee6d51cccd4dbfc7aea
      
https://github.com/qemu/qemu/commit/54e2d650ddea28968160dee6d51cccd4dbfc7aea
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv

The condition for UMIN/UMAX availability is about to change;
use the canonical version.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ef77ce0d5c4b2e738cd09b4425ce56e071a4aadc
      
https://github.com/qemu/qemu/commit/ef77ce0d5c4b2e738cd09b4425ce56e071a4aadc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Implement avx512 variable shifts

AVX512VL has VPSRAVQ, and
AVX512BW has VPSLLVW, VPSRAVW, VPSRLVW.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 47b331b2a8dae9d414971de1d92b4b8a2fbcfe89
      
https://github.com/qemu/qemu/commit/47b331b2a8dae9d414971de1d92b4b8a2fbcfe89
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Implement avx512 scalar shift

AVX512VL has VPSRAQ.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 264e4182303488fdb2917cd908f9243b317bb499
      
https://github.com/qemu/qemu/commit/264e4182303488fdb2917cd908f9243b317bb499
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Implement avx512 immediate sari shift

AVX512 has VPSRAQ with immediate operand, in the same form as
with AVX, but requires EVEX encoding and W1.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4e73f842e8b4d90776fb25a5b699b807902f1881
      
https://github.com/qemu/qemu/commit/4e73f842e8b4d90776fb25a5b699b807902f1881
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h

  Log Message:
  -----------
  tcg/i386: Implement avx512 immediate rotate

AVX512VL has VPROLD and VPROLQ, layered onto the same
opcode as PSHIFTD, but requires EVEX encoding and W1.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 102cd35c01ddb4ed434becb323d54f07e9c3158b
      
https://github.com/qemu/qemu/commit/102cd35c01ddb4ed434becb323d54f07e9c3158b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h

  Log Message:
  -----------
  tcg/i386: Implement avx512 variable rotate

AVX512VL has VPROLVD and VPRORVQ.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 965d5d0681a99540bf19f313a66ecb14cee2654a
      
https://github.com/qemu/qemu/commit/965d5d0681a99540bf19f313a66ecb14cee2654a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target-con-set.h
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.opc.h

  Log Message:
  -----------
  tcg/i386: Support avx512vbmi2 vector shift-double instructions

We will use VPSHLD, VPSHLDV and VPSHRDV for 16-bit rotates.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 786c7ef3b7668f232b3fe31a6867a7c4d114780e
      
https://github.com/qemu/qemu/commit/786c7ef3b7668f232b3fe31a6867a7c4d114780e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double

While there are no specific 16-bit rotate instructions, there
are double-word shifts, which can perform the same operation.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a2a19b429b0daaf560e03aaa4851feb9f1fc5fac
      
https://github.com/qemu/qemu/commit/a2a19b429b0daaf560e03aaa4851feb9f1fc5fac
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Remove rotls_vec from tcg_target_op_def

There is no such instruction on x86, so we should
not be pretending it has arguments.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1d442e427a66ed90ce3efb0048ceec0f9192cb02
      
https://github.com/qemu/qemu/commit/1d442e427a66ed90ce3efb0048ceec0f9192cb02
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Expand scalar rotate with avx512 insns

Expand 32-bit and 64-bit scalar rotate with VPRO[LR]V;
expand 16-bit scalar rotate with VPSHLDV.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: dac1648fd8460fbe0ff219eb41c9940617f28da0
      
https://github.com/qemu/qemu/commit/dac1648fd8460fbe0ff219eb41c9940617f28da0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Implement avx512 min/max/abs

AVX512VL has VPABSQ, VPMAXSQ, VPMAXUQ, VPMINSQ, VPMINUQ.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4c8b9686833f595176d28a90c973e0e469c7ebe7
      
https://github.com/qemu/qemu/commit/4c8b9686833f595176d28a90c973e0e469c7ebe7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Implement avx512 multiply

AVX512DQ has VPMULLQ.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3143767b743b3512a056d4d8ecdc104a95334a37
      
https://github.com/qemu/qemu/commit/3143767b743b3512a056d4d8ecdc104a95334a37
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h

  Log Message:
  -----------
  tcg/i386: Implement more logical operations for avx512

AVX512VL has a general ternary logic operation, VPTERNLOGQ,
which can implement NOT, ORC, NAND, NOR, EQV.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: cf320769476c3e2820be2a6280bfa1e15baf396f
      
https://github.com/qemu/qemu/commit/cf320769476c3e2820be2a6280bfa1e15baf396f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h

  Log Message:
  -----------
  tcg/i386: Implement bitsel for avx512

The general ternary logic operation can implement BITSEL.
Funnel the 4-operand operation into three variants of the
3-operand instruction, depending on input operand overlap.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2acf5e1d0e0f15be1b0ad85cf05b3a6e6307680c
      
https://github.com/qemu/qemu/commit/2acf5e1d0e0f15be1b0ad85cf05b3a6e6307680c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-05 (Sat, 05 Mar 2022)

  Changed paths:
    M include/qemu/cpuid.h
    M include/tcg/tcg-opc.h
    M include/tcg/tcg.h
    M tcg/aarch64/tcg-target.h
    M tcg/arm/tcg-target.h
    M tcg/i386/tcg-target-con-set.h
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h
    M tcg/i386/tcg-target.opc.h
    M tcg/optimize.c
    M tcg/ppc/tcg-target.c.inc
    M tcg/ppc/tcg-target.h
    M tcg/s390x/tcg-target.c.inc
    M tcg/s390x/tcg-target.h
    M tcg/tcg-op-vec.c
    M tcg/tcg.c
    M tcg/tci/tcg-target.c.inc

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20220304' into 
staging

Reorder do_constant_folding_cond test to satisfy valgrind.
Fix value of MAX_OPC_PARAM_IARGS.
Add opcodes for vector nand, nor, eqv.
Support vector nand, nor, eqv on PPC and S390X hosts.
Support AVX512VL, AVX512BW, AVX512DQ, and AVX512VBMI2.

# gpg: Signature made Fri 04 Mar 2022 18:59:08 GMT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-tcg-20220304: (21 commits)
  tcg/i386: Implement bitsel for avx512
  tcg/i386: Implement more logical operations for avx512
  tcg/i386: Implement avx512 multiply
  tcg/i386: Implement avx512 min/max/abs
  tcg/i386: Expand scalar rotate with avx512 insns
  tcg/i386: Remove rotls_vec from tcg_target_op_def
  tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double
  tcg/i386: Support avx512vbmi2 vector shift-double instructions
  tcg/i386: Implement avx512 variable rotate
  tcg/i386: Implement avx512 immediate rotate
  tcg/i386: Implement avx512 immediate sari shift
  tcg/i386: Implement avx512 scalar shift
  tcg/i386: Implement avx512 variable shifts
  tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv
  tcg/i386: Add tcg_out_evex_opc
  tcg/i386: Detect AVX512
  tcg/s390x: Implement vector NAND, NOR, EQV
  tcg/ppc: Implement vector NAND, NOR, EQV
  tcg: Add opcodes for vector nand, nor, eqv
  tcg: Set MAX_OPC_PARAM_IARGS to 7
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/d7e2fe4aac8b...2acf5e1d0e0f



reply via email to

[Prev in Thread] Current Thread [Next in Thread]