[Qemu-commits] [qemu/qemu] 16d323: tcg/optimize: only read val after con

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[Qemu-commits] [qemu/qemu] 16d323: tcg/optimize: only read val after con

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 16d323: tcg/optimize: only read val after const check
Date:	Fri, 04 Mar 2022 05:24:57 -0800
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 16d323233f563c86bf7f444ec4dd0e490905c8a0
      
https://github.com/qemu/qemu/commit/16d323233f563c86bf7f444ec4dd0e490905c8a0
  Author: Alex Bennée <alex.bennee@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/optimize.c

  Log Message:
  -----------
  tcg/optimize: only read val after const check

valgrind pointed out that arg_info()->val can be undefined which will
be the case if the arguments are not constant. The ordering of the
checks will have ensured we never relied on an undefined value but for
the sake of completeness re-order the code to be clear.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220209112142.3367525-1-alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 7980fe3efccc2b361f14abb0f2a15e50d1eb876c
      
https://github.com/qemu/qemu/commit/7980fe3efccc2b361f14abb0f2a15e50d1eb876c
  Author: Ziqiao Kong <ziqiaokong@gmail.com>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M include/tcg/tcg.h
    M tcg/tci/tcg-target.c.inc

  Log Message:
  -----------
  tcg: Set MAX_OPC_PARAM_IARGS to 7

The last entry of DEF_HELPERS_FLAGS_n is DEF_HELPER_FLAGS_7 and
thus the MAX_OPC_PARAM_IARGS should be 7.

Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Ziqiao Kong <ziqiaokong@gmail.com>
Message-Id: <20220227113127.414533-2-ziqiaokong@gmail.com>
Fixes: e6cadf49c3d ("tcg: Add support for a helper with 7 arguments")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4928095aaf6e87e19317a85552526759c5786a73
      
https://github.com/qemu/qemu/commit/4928095aaf6e87e19317a85552526759c5786a73
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M include/tcg/tcg-opc.h
    M include/tcg/tcg.h
    M tcg/aarch64/tcg-target.h
    M tcg/arm/tcg-target.h
    M tcg/i386/tcg-target.h
    M tcg/optimize.c
    M tcg/ppc/tcg-target.h
    M tcg/s390x/tcg-target.h
    M tcg/tcg-op-vec.c
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Add opcodes for vector nand, nor, eqv

We've had placeholders for these opcodes for a while,
and should have support on ppc, s390x and avx512 hosts.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8ba743dcac47316fed79c210eb4670a5f0e78c73
      
https://github.com/qemu/qemu/commit/8ba743dcac47316fed79c210eb4670a5f0e78c73
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc
    M tcg/ppc/tcg-target.h

  Log Message:
  -----------
  tcg/ppc: Implement vector NAND, NOR, EQV

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a4f72de89e0397851e266e9bda86b6b96c793c95
      
https://github.com/qemu/qemu/commit/a4f72de89e0397851e266e9bda86b6b96c793c95
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc
    M tcg/s390x/tcg-target.h

  Log Message:
  -----------
  tcg/s390x: Implement vector NAND, NOR, EQV

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 32c6033539734c6741a8e8085997358522d95516
      
https://github.com/qemu/qemu/commit/32c6033539734c6741a8e8085997358522d95516
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M include/qemu/cpuid.h
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h

  Log Message:
  -----------
  tcg/i386: Detect AVX512

There are some operation sizes in some subsets of AVX512 that
are missing from previous iterations of AVX.  Detect them.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e7ae60e6dfb0a77dcbcb89df296f9eaf134e05a4
      
https://github.com/qemu/qemu/commit/e7ae60e6dfb0a77dcbcb89df296f9eaf134e05a4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Add tcg_out_evex_opc

The evex encoding is added here, for use in a subsequent patch.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4c758caed09a5654884127d7fc5856626095e87b
      
https://github.com/qemu/qemu/commit/4c758caed09a5654884127d7fc5856626095e87b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv

The condition for UMIN/UMAX availability is about to change;
use the canonical version.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 5b4ab567295f90c2084d4fd4d80b74642332645e
      
https://github.com/qemu/qemu/commit/5b4ab567295f90c2084d4fd4d80b74642332645e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Implement avx512 variable shifts

AVX512VL has VPSRAVQ, and
AVX512BW has VPSLLVW, VPSRAVW, VPSRLVW.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2a3c03189162d270e7b703872444a96441f730bc
      
https://github.com/qemu/qemu/commit/2a3c03189162d270e7b703872444a96441f730bc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Implement avx512 scalar shift

AVX512VL has VPSRAQ.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a0e3d1f8dc73eb478d347d5303c31aa8bfa17fb7
      
https://github.com/qemu/qemu/commit/a0e3d1f8dc73eb478d347d5303c31aa8bfa17fb7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Implement avx512 immediate sari shift

AVX512 has VPSRAQ with immediate operand, in the same form as
with AVX, but requires EVEX encoding and W1.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 6d3f946d48ce9888556b5b815ae6352eb7812bab
      
https://github.com/qemu/qemu/commit/6d3f946d48ce9888556b5b815ae6352eb7812bab
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h

  Log Message:
  -----------
  tcg/i386: Implement avx512 immediate rotate

AVX512VL has VPROLD and VPROLQ, layered onto the same
opcode as PSHIFTD, but requires EVEX encoding and W1.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: dd83c68c83535231d2c26ee5ed77a2a865795aa0
      
https://github.com/qemu/qemu/commit/dd83c68c83535231d2c26ee5ed77a2a865795aa0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h

  Log Message:
  -----------
  tcg/i386: Implement avx512 variable rotate

AVX512VL has VPROLVD and VPRORVQ.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e39196f1933b5159dd5f191175c2ae9ad97ce763
      
https://github.com/qemu/qemu/commit/e39196f1933b5159dd5f191175c2ae9ad97ce763
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target-con-set.h
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.opc.h

  Log Message:
  -----------
  tcg/i386: Support avx512vbmi2 vector shift-double instructions

We will use VPSHLD, VPSHLDV and VPSHRDV for 16-bit rotates.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d35777a186ecb9af48691dcb2b524b7488aa41cc
      
https://github.com/qemu/qemu/commit/d35777a186ecb9af48691dcb2b524b7488aa41cc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double

While there are no specific 16-bit rotate instructions, there
are double-word shifts, which can perform the same operation.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 15bc722be9f5eaee1fb153a6004f8c0d69d1b902
      
https://github.com/qemu/qemu/commit/15bc722be9f5eaee1fb153a6004f8c0d69d1b902
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Remove rotls_vec from tcg_target_op_def

There is no such instruction on x86, so we should
not be pretending it has arguments.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 31e438cdf740523f467f9102bad67e847fc53ce6
      
https://github.com/qemu/qemu/commit/31e438cdf740523f467f9102bad67e847fc53ce6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Expand scalar rotate with avx512 insns

Expand 32-bit and 64-bit scalar rotate with VPRO[LR]V;
expand 16-bit scalar rotate with VPSHLDV.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 237ca0d1271a3fd78cf58f5508f8a4e863a59934
      
https://github.com/qemu/qemu/commit/237ca0d1271a3fd78cf58f5508f8a4e863a59934
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Implement avx512 min/max/abs

AVX512VL has VPABSQ, VPMAXSQ, VPMAXUQ, VPMINSQ, VPMINUQ.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 6687cba21cf8de468ab101021e04db3b6766cec1
      
https://github.com/qemu/qemu/commit/6687cba21cf8de468ab101021e04db3b6766cec1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Implement avx512 multiply

AVX512DQ has VPMULLQ.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: fdf20be5762c1ed2075a1539cd97c84c8311054d
      
https://github.com/qemu/qemu/commit/fdf20be5762c1ed2075a1539cd97c84c8311054d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h

  Log Message:
  -----------
  tcg/i386: Implement more logical operations for avx512

AVX512VL has a general ternary logic operation, VPTERNLOGQ,
which can implement NOT, ORC, NAND, NOR, EQV.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 277be99feae3d7cbd489b99965878a763071f191
      
https://github.com/qemu/qemu/commit/277be99feae3d7cbd489b99965878a763071f191
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h

  Log Message:
  -----------
  tcg/i386: Implement bitsel for avx512

The general ternary logic operation can implement BITSEL.
Funnel the 4-operand operation into three variants of the
3-operand instruction, depending on input operand overlap.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4d750b3af01844b826b155c7f3b72526fed7e652
      
https://github.com/qemu/qemu/commit/4d750b3af01844b826b155c7f3b72526fed7e652
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    A tcg/aarch64/tcg-target-sa32.h
    A tcg/arm/tcg-target-sa32.h
    A tcg/i386/tcg-target-sa32.h
    A tcg/loongarch64/tcg-target-sa32.h
    A tcg/mips/tcg-target-sa32.h
    A tcg/ppc/tcg-target-sa32.h
    A tcg/riscv/tcg-target-sa32.h
    A tcg/s390x/tcg-target-sa32.h
    A tcg/sparc/tcg-target-sa32.h
    M tcg/tcg.c
    A tcg/tci/tcg-target-sa32.h

  Log Message:
  -----------
  tcg: Add TCG_TARGET_SIGNED_ADDR32

Define as 0 for all tcg hosts.  Put this in a separate header,
because we'll want this in places that do not ordinarily have
access to all of tcg/tcg.h.

Reviewed-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 466c5e1439ae5b93cf370931d982e561dfb86aa4
      
https://github.com/qemu/qemu/commit/466c5e1439ae5b93cf370931d982e561dfb86aa4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  accel/tcg: Split out g2h_tlbe

Create a new function to combine a CPUTLBEntry addend
with the guest address to form a host address.

Reviewed-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: deb70f945bf309186a8287903351920d6841b643
      
https://github.com/qemu/qemu/commit/deb70f945bf309186a8287903351920d6841b643
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu

When TCG_TARGET_SIGNED_ADDR32 is set, adjust the tlb addend to
allow the 32-bit guest address to be sign extended within the
64-bit host register instead of zero extended.

This will simplify tcg hosts like MIPS, RISC-V, and LoongArch,
which naturally sign-extend 32-bit values, in contrast to x86_64
and AArch64 which zero-extend them.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ee490b3f61f4337290309bb050300f0cf8c21689
      
https://github.com/qemu/qemu/commit/ee490b3f61f4337290309bb050300f0cf8c21689
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M bsd-user/main.c
    M include/exec/cpu-all.h
    M include/exec/cpu_ldst.h
    M linux-user/main.c

  Log Message:
  -----------
  accel/tcg: Add guest_base_signed_addr32 for user-only

While the host may prefer to treat 32-bit addresses as signed,
there are edge cases of guests that cannot be implemented with
addresses 0x7fff_ffff and 0x8000_0000 being non-consecutive.

Therefore, default to guest_base_signed_addr32 false, and allow
probe_guest_base to determine whether it is possible to set it
to true.  A tcg backend which sets TCG_TARGET_SIGNED_ADDR32 will
have to cope with either setting for user-only.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 372462f8e935ce4ba63fa9126e78e6b51ee077c6
      
https://github.com/qemu/qemu/commit/372462f8e935ce4ba63fa9126e78e6b51ee077c6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M include/exec/cpu-all.h
    M linux-user/elfload.c

  Log Message:
  -----------
  linux-user: Support TCG_TARGET_SIGNED_ADDR32

When using reserved_va, which is the default for a 64-bit host
and a 32-bit guest, set guest_base_signed_addr32 if requested
by TCG_TARGET_SIGNED_ADDR32, and the executable layout allows.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ef827487a61677d91b92f8575b9bf14fd88e2205
      
https://github.com/qemu/qemu/commit/ef827487a61677d91b92f8575b9bf14fd88e2205
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/aarch64/tcg-target-sa32.h
    M tcg/aarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/aarch64: Support TCG_TARGET_SIGNED_ADDR32

AArch64 has both sign and zero-extending addressing modes, which
means that either treatment of guest addresses is equally efficient.
Enabling this for AArch64 gives us testing of the feature in CI.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 43559e068025c635b52d8e30e38f30bb8afae861
      
https://github.com/qemu/qemu/commit/43559e068025c635b52d8e30e38f30bb8afae861
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/mips/tcg-target-sa32.h
    M tcg/mips/tcg-target.c.inc

  Log Message:
  -----------
  tcg/mips: Support TCG_TARGET_SIGNED_ADDR32

All 32-bit mips operations sign-extend the output, so we are easily
able to keep TCG_TYPE_I32 values sign-extended in host registers.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: bbe823a306a0e74cf8ba16b2e8beeea0b19a52d8
      
https://github.com/qemu/qemu/commit/bbe823a306a0e74cf8ba16b2e8beeea0b19a52d8
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/riscv/tcg-target-sa32.h
    M tcg/riscv/tcg-target.c.inc

  Log Message:
  -----------
  tcg/riscv: Support TCG_TARGET_SIGNED_ADDR32

All RV64 32-bit operations sign-extend the output, so we are easily
able to keep TCG_TYPE_I32 values sign-extended in host registers.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f23e6de25c31cadd9a3b7122f9384e6b259ce37f
      
https://github.com/qemu/qemu/commit/f23e6de25c31cadd9a3b7122f9384e6b259ce37f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M tcg/loongarch64/tcg-target-sa32.h
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Support TCG_TARGET_SIGNED_ADDR32

All 32-bit LoongArch operations sign-extend the output, so we are easily
able to keep TCG_TYPE_I32 values sign-extended in host registers.

Cc: WANG Xuerui <git@xen0n.name>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 110929300ee3eb0f7b0a8d30eb571af29f5b14f8
      
https://github.com/qemu/qemu/commit/110929300ee3eb0f7b0a8d30eb571af29f5b14f8
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-03-04 (Fri, 04 Mar 2022)

  Changed paths:
    M accel/tcg/cputlb.c
    M bsd-user/main.c
    M include/exec/cpu-all.h
    M include/exec/cpu_ldst.h
    M include/qemu/cpuid.h
    M include/tcg/tcg-opc.h
    M include/tcg/tcg.h
    M linux-user/elfload.c
    M linux-user/main.c
    A tcg/aarch64/tcg-target-sa32.h
    M tcg/aarch64/tcg-target.c.inc
    M tcg/aarch64/tcg-target.h
    A tcg/arm/tcg-target-sa32.h
    M tcg/arm/tcg-target.h
    M tcg/i386/tcg-target-con-set.h
    A tcg/i386/tcg-target-sa32.h
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h
    M tcg/i386/tcg-target.opc.h
    A tcg/loongarch64/tcg-target-sa32.h
    M tcg/loongarch64/tcg-target.c.inc
    A tcg/mips/tcg-target-sa32.h
    M tcg/mips/tcg-target.c.inc
    M tcg/optimize.c
    A tcg/ppc/tcg-target-sa32.h
    M tcg/ppc/tcg-target.c.inc
    M tcg/ppc/tcg-target.h
    A tcg/riscv/tcg-target-sa32.h
    M tcg/riscv/tcg-target.c.inc
    A tcg/s390x/tcg-target-sa32.h
    M tcg/s390x/tcg-target.c.inc
    M tcg/s390x/tcg-target.h
    A tcg/sparc/tcg-target-sa32.h
    M tcg/tcg-op-vec.c
    M tcg/tcg.c
    A tcg/tci/tcg-target-sa32.h
    M tcg/tci/tcg-target.c.inc

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20220303' into 
staging

Reorder do_constant_folding_cond test to satisfy valgrind.
Fix value of MAX_OPC_PARAM_IARGS.
Add opcodes for vector nand, nor, eqv.
Support vector nand, nor, eqv on PPC and S390X hosts.
Support AVX512VL, AVX512BW, AVX512DQ, and AVX512VBMI2.
Support 32-bit guest addresses as signed values.

# gpg: Signature made Thu 03 Mar 2022 20:58:00 GMT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-tcg-20220303: (30 commits)
  tcg/loongarch64: Support TCG_TARGET_SIGNED_ADDR32
  tcg/riscv: Support TCG_TARGET_SIGNED_ADDR32
  tcg/mips: Support TCG_TARGET_SIGNED_ADDR32
  tcg/aarch64: Support TCG_TARGET_SIGNED_ADDR32
  linux-user: Support TCG_TARGET_SIGNED_ADDR32
  accel/tcg: Add guest_base_signed_addr32 for user-only
  accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu
  accel/tcg: Split out g2h_tlbe
  tcg: Add TCG_TARGET_SIGNED_ADDR32
  tcg/i386: Implement bitsel for avx512
  tcg/i386: Implement more logical operations for avx512
  tcg/i386: Implement avx512 multiply
  tcg/i386: Implement avx512 min/max/abs
  tcg/i386: Expand scalar rotate with avx512 insns
  tcg/i386: Remove rotls_vec from tcg_target_op_def
  tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double
  tcg/i386: Support avx512vbmi2 vector shift-double instructions
  tcg/i386: Implement avx512 variable rotate
  tcg/i386: Implement avx512 immediate rotate
  tcg/i386: Implement avx512 immediate sari shift
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/4c1d764d586f...110929300ee3
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