[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 90f9e3: target/riscv: fix inverted checks for
From: |
Peter Maydell |
Subject: |
[Qemu-commits] [qemu/qemu] 90f9e3: target/riscv: fix inverted checks for ext_zb[abcs] |
Date: |
Fri, 04 Mar 2022 02:32:19 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 90f9e35b7895b32a451df82c773d95faba910f49
https://github.com/qemu/qemu/commit/90f9e35b7895b32a451df82c773d95faba910f49
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: 2022-03-03 (Thu, 03 Mar 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvb.c.inc
Log Message:
-----------
target/riscv: fix inverted checks for ext_zb[abcs]
While changing to the use of cfg_ptr, the conditions for REQUIRE_ZB[ABCS]
inadvertently became inverted and slipped through the initial testing (which
used RV64GC_XVentanaCondOps as a target).
This fixes the regression.
Tested against SPEC2017 w/ GCC 12 (prerelease) for RV64GC_zba_zbb_zbc_zbs.
Fixes: f2a32bec8f0da99 ("target/riscv: access cfg structure through
DisasContext")
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220203153946.2676353-1-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e6faee65855bf6d2ee480c5515f6d157c3229a38
https://github.com/qemu/qemu/commit/e6faee65855bf6d2ee480c5515f6d157c3229a38
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-03-03 (Thu, 03 Mar 2022)
Changed paths:
M hw/riscv/Kconfig
M hw/riscv/virt.c
M include/hw/riscv/virt.h
Log Message:
-----------
hw/riscv: virt: Add optional AIA APLIC support to virt machine
We extend virt machine to emulate AIA APLIC devices only when
"aia=aplic" parameter is passed along with machine name in QEMU
command-line. When "aia=none" or not specified then we fallback
to original PLIC device emulation.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220220085526.808674-2-anup@brainfault.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9746e583fe6ca67d9645448989535bc19adb6150
https://github.com/qemu/qemu/commit/9746e583fe6ca67d9645448989535bc19adb6150
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-03-03 (Thu, 03 Mar 2022)
Changed paths:
M hw/intc/Kconfig
M hw/intc/meson.build
A hw/intc/riscv_imsic.c
A include/hw/intc/riscv_imsic.h
Log Message:
-----------
hw/intc: Add RISC-V AIA IMSIC device emulation
The RISC-V AIA (Advanced Interrupt Architecture) defines a new
interrupt controller for MSIs (message signal interrupts) called
IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC
is per-HART device and also suppport virtualizaiton of MSIs using
dedicated VS-level guest interrupt files.
This patch adds device emulation for RISC-V AIA IMSIC which
supports M-level, S-level, and VS-level MSIs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-Id: <20220220085526.808674-3-anup@brainfault.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 28d8c281200f20a060c456c81fd1564f3d119fda
https://github.com/qemu/qemu/commit/28d8c281200f20a060c456c81fd1564f3d119fda
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-03-03 (Thu, 03 Mar 2022)
Changed paths:
M hw/riscv/Kconfig
M hw/riscv/virt.c
M include/hw/riscv/virt.h
Log Message:
-----------
hw/riscv: virt: Add optional AIA IMSIC support to virt machine
We extend virt machine to emulate both AIA IMSIC and AIA APLIC
devices only when "aia=aplic-imsic" parameter is passed along
with machine name in the QEMU command-line. The AIA IMSIC is
only a per-HART MSI controller so we use AIA APLIC in MSI-mode
to forward all wired interrupts as MSIs to the AIA IMSIC.
We also provide "aia-guests=<xyz>" parameter which can be used
to specify number of VS-level AIA IMSIC Guests MMIO pages for
each HART.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220220085526.808674-4-anup@brainfault.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c65bc383edc7aa7c12afcdad3be30521b3280203
https://github.com/qemu/qemu/commit/c65bc383edc7aa7c12afcdad3be30521b3280203
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-03-03 (Thu, 03 Mar 2022)
Changed paths:
M docs/system/riscv/virt.rst
Log Message:
-----------
docs/system: riscv: Document AIA options for virt machine
We have two new machine options "aia" and "aia-guests" available
for the RISC-V virt machine so let's document these options.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-Id: <20220220085526.808674-5-anup@brainfault.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0631aaae31cccf5ae61e8c67c198e064bfaafc66
https://github.com/qemu/qemu/commit/0631aaae31cccf5ae61e8c67c198e064bfaafc66
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-03-03 (Thu, 03 Mar 2022)
Changed paths:
M hw/riscv/virt.c
M include/hw/riscv/virt.h
Log Message:
-----------
hw/riscv: virt: Increase maximum number of allowed CPUs
To facilitate software development of RISC-V systems with large number
of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).
We also add a detailed source level comments about limit defines which
impact the physical address space utilization.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-Id: <20220220085526.808674-6-anup@brainfault.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: aecabd50b7432e7173f51b2dd9d845717c6796ea
https://github.com/qemu/qemu/commit/aecabd50b7432e7173f51b2dd9d845717c6796ea
Author: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Date: 2022-03-03 (Thu, 03 Mar 2022)
Changed paths:
M hw/riscv/opentitan.c
M include/hw/riscv/opentitan.h
Log Message:
-----------
hw: riscv: opentitan: fixup SPI addresses
This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1
base addresses. Also adds these as unimplemented devices.
The address references can be found [1].
[1]
https://github.com/lowRISC/opentitan/blob/6c317992fbd646818b34f2a2dbf44bc850e461e4/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h#L107
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220218063839.405082-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 89ffdcec2722c92aac99d1c2bd547ac9b2ff0179
https://github.com/qemu/qemu/commit/89ffdcec2722c92aac99d1c2bd547ac9b2ff0179
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-03-03 (Thu, 03 Mar 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220211043920.28981-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c163b3baf93cdccc531410f76598cc8146b8f578
https://github.com/qemu/qemu/commit/c163b3baf93cdccc531410f76598cc8146b8f578
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-03-03 (Thu, 03 Mar 2022)
Changed paths:
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: hardwire mstatus.FS to zero when enable zfinx
Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220211043920.28981-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e1a29bbd5493634afd52f1724331728abdd196b8
https://github.com/qemu/qemu/commit/e1a29bbd5493634afd52f1724331728abdd196b8
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-03-03 (Thu, 03 Mar 2022)
Changed paths:
M target/riscv/fpu_helper.c
M target/riscv/helper.h
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/internals.h
M target/riscv/translate.c
Log Message:
-----------
target/riscv: add support for zfinx
- update extension check REQUIRE_ZFINX_OR_F
- update single float point register read/write
- disable nanbox_s check
Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220211043920.28981-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 026e73fa2665f07d24bb715f2c405c3e38587812
https://github.com/qemu/qemu/commit/026e73fa2665f07d24bb715f2c405c3e38587812
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-03-03 (Thu, 03 Mar 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: add support for zdinx
-- update extension check REQUIRE_ZDINX_OR_D
-- update double float point register read/write
Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220211043920.28981-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a2464a4cec4740c3703d8232f695d6643e0e086e
https://github.com/qemu/qemu/commit/a2464a4cec4740c3703d8232f695d6643e0e086e
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-03-03 (Thu, 03 Mar 2022)
Changed paths:
M target/riscv/fpu_helper.c
M target/riscv/helper.h
M target/riscv/insn_trans/trans_rvzfh.c.inc
M target/riscv/internals.h
Log Message:
-----------
target/riscv: add support for zhinx/zhinxmin
- update extension check REQUIRE_ZHINX_OR_ZFH and
REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN
- update half float point register read/write
- disable nanbox_h check
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220211043920.28981-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 6b1accefd4876ea5475d55454c7d5b52c02cb73c
https://github.com/qemu/qemu/commit/6b1accefd4876ea5475d55454c7d5b52c02cb73c
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-03-03 (Thu, 03 Mar 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: expose zfinx, zdinx, zhinx{min} properties
Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220211043920.28981-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5959ef7d431ffd02db112209cf55e47b677256fd
https://github.com/qemu/qemu/commit/5959ef7d431ffd02db112209cf55e47b677256fd
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-03-03 (Thu, 03 Mar 2022)
Changed paths:
M docs/system/riscv/virt.rst
M hw/intc/Kconfig
M hw/intc/meson.build
A hw/intc/riscv_imsic.c
M hw/riscv/Kconfig
M hw/riscv/opentitan.c
M hw/riscv/virt.c
A include/hw/intc/riscv_imsic.h
M include/hw/riscv/opentitan.h
M include/hw/riscv/virt.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/fpu_helper.c
M target/riscv/helper.h
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvf.c.inc
M target/riscv/insn_trans/trans_rvzfh.c.inc
M target/riscv/internals.h
M target/riscv/translate.c
Log Message:
-----------
Merge remote-tracking branch
'remotes/alistair/tags/pull-riscv-to-apply-20220303' into staging
Fifth RISC-V PR for QEMU 7.0
* Fixup checks for ext_zb[abcs]
* Add AIA support for virt machine
* Increase maximum number of CPUs in virt machine
* Fixup OpenTitan SPI address
* Add support for zfinx, zdinx and zhinx{min} extensions
# gpg: Signature made Thu 03 Mar 2022 05:26:55 GMT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20220303:
target/riscv: expose zfinx, zdinx, zhinx{min} properties
target/riscv: add support for zhinx/zhinxmin
target/riscv: add support for zdinx
target/riscv: add support for zfinx
target/riscv: hardwire mstatus.FS to zero when enable zfinx
target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
hw: riscv: opentitan: fixup SPI addresses
hw/riscv: virt: Increase maximum number of allowed CPUs
docs/system: riscv: Document AIA options for virt machine
hw/riscv: virt: Add optional AIA IMSIC support to virt machine
hw/intc: Add RISC-V AIA IMSIC device emulation
hw/riscv: virt: Add optional AIA APLIC support to virt machine
target/riscv: fix inverted checks for ext_zb[abcs]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/6629bf78aac7...5959ef7d431f