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[Qemu-commits] [qemu/qemu] cc3b66: mps3-an547: Add missing user ahb inte
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] cc3b66: mps3-an547: Add missing user ahb interfaces |
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Date: |
Thu, 03 Mar 2022 11:57:37 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: cc3b66ac949e28e030eeb9b5e2950f24d894be95
https://github.com/qemu/qemu/commit/cc3b66ac949e28e030eeb9b5e2950f24d894be95
Author: Jimmy Brisson <jimmy.brisson@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
mps3-an547: Add missing user ahb interfaces
With these interfaces missing, TFM would delegate peripherals 0, 1,
2, 3 and 8, and qemu would ignore the delegation of interface 8, as
it thought interface 4 was eth & USB.
This patch corrects this behavior and allows TFM to delegate the
eth & USB peripheral to NS mode.
(The old QEMU behaviour was based on revision B of the AN547
appnote; revision C corrects this error in the documentation,
and this commit brings QEMU in to line with how the FPGA
image really behaves.)
Signed-off-by: Jimmy Brisson <jimmy.brisson@linaro.org>
Message-id: 20220210210227.3203883-1-jimmy.brisson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: added commit message note clarifying that the old behaviour
was a docs issue, not because there were two different versions
of the FPGA image]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e212fb05cd2694fdb7a20abe8f0968715d67f9e5
https://github.com/qemu/qemu/commit/e212fb05cd2694fdb7a20abe8f0968715d67f9e5
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz.c: Update AN547 documentation URL
The AN547 application note URL has changed: update our comment
accordingly. (Rev B is still downloadable from the old URL,
but there is a new Rev C of the document now.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220221094144.426191-1-peter.maydell@linaro.org
Commit: bad187dfcb0834dd67d1bfa40a305a08f0d5641a
https://github.com/qemu/qemu/commit/bad187dfcb0834dd67d1bfa40a305a08f0d5641a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M hw/input/tsc210x.c
Log Message:
-----------
hw/input/tsc210x: Don't abort on bad SPI word widths
The tsc210x doesn't support anything other than 16-bit reads on the
SPI bus, but the guest can program the SPI controller to attempt
them anyway. If this happens, don't abort QEMU, just log this as
a guest error.
This fixes our machine_arm_n8x0.py:N8x0Machine.test_n800
acceptance test, which hits this assertion.
The reason we hit the assertion is because the guest kernel thinks
there is a TSC2005 on this SPI bus address, not a TSC210x. (The n810
*does* have a TSC2005 at this address.) The TSC2005 supports the
24-bit accesses which the guest driver makes, and the TSC210x does
not (that is, our TSC210x emulation is not missing support for a word
width the hardware can handle). It's not clear whether the problem
here is that the guest kernel incorrectly thinks the n800 has the
same device at this SPI bus address as the n810, or that QEMU's n810
board model doesn't get the SPI devices right. At this late date
there no longer appears to be any reliable information on the web
about the hardware behaviour, but I am inclined to think this is a
guest kernel bug. In any case, we prefer not to abort QEMU for
guest-triggerable conditions, so logging the error is the right thing
to do.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/736
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20220221140750.514557-1-peter.maydell@linaro.org
Commit: d8bdf9797248eb48ac3c8bc970f60e19984546bd
https://github.com/qemu/qemu/commit/d8bdf9797248eb48ac3c8bc970f60e19984546bd
Author: Patrick Venture <venture@google.com>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M hw/i2c/i2c_mux_pca954x.c
Log Message:
-----------
hw/i2c: flatten pca954x mux device
Previously this device created N subdevices which each owned an i2c bus.
Now this device simply owns the N i2c busses directly.
Tested: Verified devices behind mux are still accessible via qmp and i2c
from within an arm32 SoC.
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220202164533.1283668-1-venture@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0dc71c701cd68c0c0508360944367faebc394196
https://github.com/qemu/qemu/commit/0dc71c701cd68c0c0508360944367faebc394196
Author: Akihiko Odaki <akihiko.odaki@gmail.com>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M hw/arm/boot.c
M target/arm/cpu.c
M target/arm/hvf/hvf.c
M target/arm/kvm-consts.h
M target/arm/kvm64.c
M target/arm/psci.c
Log Message:
-----------
target/arm: Support PSCI 1.1 and SMCCC 1.0
Support the latest PSCI on TCG and HVF. A 64-bit function called from
AArch32 now returns NOT_SUPPORTED, which is necessary to adhere to SMC
Calling Convention 1.0. It is still not compliant with SMCCC 1.3 since
they do not implement mandatory functions.
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Message-id: 20220213035753.34577-1-akihiko.odaki@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: update MISMATCH_CHECK checks on PSCI_VERSION macros to match]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 23d5acf3d40f8010275ae9a5a80daf652a97308f
https://github.com/qemu/qemu/commit/23d5acf3d40f8010275ae9a5a80daf652a97308f
Author: Wentao_Liang <Wentao_Liang_g@163.com>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()
handle_simd_shift_fpint_conv() was accidentally freeing the TCG
temporary tcg_fpstatus too early, before the last use of it. Move
the free down to where it belongs.
Signed-off-by: Wentao_Liang <Wentao_Liang_g@163.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[PMM: cleaned up commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4c579e15bdde6468317b40a84bf93e0114a0b179
https://github.com/qemu/qemu/commit/4c579e15bdde6468317b40a84bf93e0114a0b179
Author: Shengtan Mao <stmao@google.com>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M tests/qtest/meson.build
A tests/qtest/npcm7xx_sdhci-test.c
Log Message:
-----------
tests/qtest: add qtests for npcm7xx sdhci
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Chris Rauer <crauer@google.com>
Signed-off-by: Shengtan Mao <stmao@google.com>
Signed-off-by: Patrick Venture <venture@google.com>
Message-id: 20220225174451.192304-1-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d5e51efb9f1842d85f24fb0e2fe298641de6e129
https://github.com/qemu/qemu/commit/d5e51efb9f1842d85f24fb0e2fe298641de6e129
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M include/hw/registerfields.h
Log Message:
-----------
hw/registerfields: Add FIELD_SEX<N> and FIELD_SDP<N>
Add new macros to manipulate signed fields within the register.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-2-richard.henderson@linaro.org
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 691f1ffdfc446acc1a9f0831fcced5012f6de52a
https://github.com/qemu/qemu/commit/691f1ffdfc446acc1a9f0831fcced5012f6de52a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Set TCR_EL1.TSZ for user-only
Set this as the kernel would, to 48 bits, to keep the computation
of the address space correct for PAuth.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ebf93ce7c07b91eecf8b00cd2218bc0be99d7f6c
https://github.com/qemu/qemu/commit/ebf93ce7c07b91eecf8b00cd2218bc0be99d7f6c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Fault on invalid TCR_ELx.TxSZ
Without FEAT_LVA, the behaviour of programming an invalid value
is IMPLEMENTATION DEFINED. With FEAT_LVA, programming an invalid
minimum value requires a Translation fault.
It is most self-consistent to choose to generate the fault always.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 71a77257dd4926e782bc8939c3323d7017e2936f
https://github.com/qemu/qemu/commit/71a77257dd4926e782bc8939c3323d7017e2936f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Move arm_pamax out of line
We will shortly share parts of this function with other portions
of address translation.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 49ba115bb7429bb64bcbc7e5705a04090058e9a3
https://github.com/qemu/qemu/commit/49ba115bb7429bb64bcbc7e5705a04090058e9a3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Pass outputsize down to check_s2_mmu_setup
Pass down the width of the output address from translation.
For now this is still just PAMax, but a subsequent patch will
compute the correct value from TCR_ELx.{I}PS.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d06449f2eb555896057ee047b3009a3616d52028
https://github.com/qemu/qemu/commit/d06449f2eb555896057ee047b3009a3616d52028
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Use MAKE_64BIT_MASK to compute indexmask
The macro is a bit more readable than the inlined computation.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f4ecc01537684a4125c35433f3097295d0a1f839
https://github.com/qemu/qemu/commit/f4ecc01537684a4125c35433f3097295d0a1f839
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Honor TCR_ELx.{I}PS
This field controls the output (intermediate) physical address size
of the translation process. V8 requires to raise an AddressSize
fault if the page tables are programmed incorrectly, such that any
intermediate descriptor address, or the final translated address,
is out of range.
Add a PS field to ARMVAParameters, and properly compute outputsize
in get_phys_addr_lpae. Test the descaddr as extracted from TTBR
and from page table entries.
Restrict descaddrmask so that we won't raise the fault for v7.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 777ab8d84442dd6c0c5fbf787de87779d5ab82e8
https://github.com/qemu/qemu/commit/777ab8d84442dd6c0c5fbf787de87779d5ab82e8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA
The original A.a revision of the AArch64 ARM required that we
force-extend the addresses in these registers from 49 bits.
This language has been loosened via a combination of IMPLEMENTATION
DEFINED and CONSTRAINTED UNPREDICTABLE to allow consideration of
the entire aligned address.
This means that we do not have to consider whether or not FEAT_LVA
is enabled, and decide from which bit an address might need to be
extended.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0af312b6edd231e1c8d0dec12494a80bc39ac761
https://github.com/qemu/qemu/commit/0af312b6edd231e1c8d0dec12494a80bc39ac761
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu-param.h
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement FEAT_LVA
This feature is relatively small, as it applies only to
64k pages and thus requires no additional changes to the
table descriptor walking algorithm, only a change to the
minimum TSZ (which is the inverse of the maximum virtual
address space size).
Note that this feature widens VBAR_ELx, but we already
treat the register as being 64 bits wide.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7a928f43d8724bdf0777d7fc67a5ad973a0bf4bf
https://github.com/qemu/qemu/commit/7a928f43d8724bdf0777d7fc67a5ad973a0bf4bf
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu-param.h
M target/arm/cpu64.c
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement FEAT_LPA
This feature widens physical addresses (and intermediate physical
addresses for 2-stage translation) from 48 to 52 bits, when using
64k pages. The only thing left at this point is to handle the
extra bits in the TTBR and in the table descriptors.
Note that PAR_EL1 and HPFAR_EL2 are nominally extended, but we don't
mask out the high bits when writing to those registers, so no changes
are required there.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 13e481c9335582fc7eed12e24e8d4d7068b24ff8
https://github.com/qemu/qemu/commit/13e481c9335582fc7eed12e24e8d4d7068b24ff8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M target/arm/internals.h
Log Message:
-----------
target/arm: Extend arm_fi_to_lfsc to level -1
With FEAT_LPA2, rather than introducing translation level 4,
we introduce level -1, below the current level 0. Extend
arm_fi_to_lfsc to handle these faults.
Assert that this new translation level does not leak into
fault types for which it is not defined, which allows some
masking of fi->level to be removed.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ab1cdb47bf89602b3cacf60720971c68f1758a40
https://github.com/qemu/qemu/commit/ab1cdb47bf89602b3cacf60720971c68f1758a40
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Introduce tlbi_aa64_get_range
Merge tlbi_aa64_range_get_length and tlbi_aa64_range_get_base,
returning a structure containing both results. Pass in the
ARMMMUIdx, rather than the digested two_ranges boolean.
This is in preparation for FEAT_LPA2, where the interpretation
of 'value' depends on the effective value of DS for the regime.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d976de218c534735e307fc4a6c03e3ae764fd419
https://github.com/qemu/qemu/commit/d976de218c534735e307fc4a6c03e3ae764fd419
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Fix TLBIRange.base for 16k and 64k pages
The shift of the BaseADDR field depends on the translation
granule in use.
Fixes: 84940ed8255 ("target/arm: Add support for FEAT_TLBIRANGE")
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3974ff93a7632739189ed6fce374cd9c16b525fc
https://github.com/qemu/qemu/commit/3974ff93a7632739189ed6fce374cd9c16b525fc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Validate tlbi TG matches translation granule in use
For FEAT_LPA2, we will need other ARMVAParameters, which themselves
depend on the translation granule in use. We might as well validate
that the given TG matches; the architecture "does not require that
the instruction invalidates any entries" if this is not true.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c20281b2a5048a220e09e98e002e6d3119f8c00b
https://github.com/qemu/qemu/commit/c20281b2a5048a220e09e98e002e6d3119f8c00b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Advertise all page sizes for -cpu max
We support 16k pages, but do not advertize that in ID_AA64MMFR0.
The value 0 in the TGRAN*_2 fields indicates that stage2 lookups defer
to the same support as stage1 lookups. This setting is deprecated, so
indicate support for all stage2 page sizes directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220301215958.157011-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ef56c2425e5f3e5f14ac080b5f037e5c36a0abdc
https://github.com/qemu/qemu/commit/ef56c2425e5f3e5f14ac080b5f037e5c36a0abdc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Implement FEAT_LPA2
This feature widens physical addresses (and intermediate physical
addresses for 2-stage translation) from 48 to 52 bits, when using
4k or 16k pages.
This introduces the DS bit to TCR_ELx, which is RES0 unless the
page size is enabled and supports LPA2, resulting in the effective
value of DS for a given table walk. The DS bit changes the format
of the page table descriptor slightly, moving the PS field out to
TCR so that all pages have the same sharability and repurposing
those bits of the page table descriptor for the highest bits of
the output address.
Do not yet enable FEAT_LPA2; we need extra plumbing to avoid
tickling an old kernel bug.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: dc8bc9d6574aa563ed2fcc0ff495e77a2a2a8faa
https://github.com/qemu/qemu/commit/dc8bc9d6574aa563ed2fcc0ff495e77a2a2a8faa
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M hw/arm/boot.c
M target/arm/kvm-consts.h
M target/arm/kvm64.c
Log Message:
-----------
target/arm: Report KVM's actual PSCI version to guest in dtb
When we're using KVM, the PSCI implementation is provided by the
kernel, but QEMU has to tell the guest about it via the device tree.
Currently we look at the KVM_CAP_ARM_PSCI_0_2 capability to determine
if the kernel is providing at least PSCI 0.2, but if the kernel
provides a newer version than that we will still only tell the guest
it has PSCI 0.2. (This is fairly harmless; it just means the guest
won't use newer parts of the PSCI API.)
The kernel exposes the specific PSCI version it is implementing via
the ONE_REG API; use this to report in the dtb that the PSCI
implementation is 1.0-compatible if appropriate. (The device tree
binding currently only distinguishes "pre-0.2", "0.2-compatible" and
"1.0-compatible".)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20220224134655.1207865-1-peter.maydell@linaro.org
Commit: 8d65dee2c42abf323a0494200f2086ddf05444c2
https://github.com/qemu/qemu/commit/8d65dee2c42abf323a0494200f2086ddf05444c2
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M ui/cocoa.m
Log Message:
-----------
ui/cocoa.m: Fix updateUIInfo threading issues
The updateUIInfo method makes Cocoa API calls. It also calls back
into QEMU functions like dpy_set_ui_info(). To do this safely, we
need to follow two rules:
* Cocoa API calls are made on the Cocoa UI thread
* When calling back into QEMU we must hold the iothread lock
Fix the places where we got this wrong, by taking the iothread lock
while executing updateUIInfo, and moving the call in cocoa_switch()
inside the dispatch_async block.
Some of the Cocoa UI methods which call updateUIInfo are invoked as
part of the initial application startup, while we're still doing the
little cross-thread dance described in the comment just above
call_qemu_main(). This meant they were calling back into the QEMU UI
layer before we'd actually finished initializing our display and
registered the DisplayChangeListener, which isn't really valid. Once
updateUIInfo takes the iothread lock, we no longer get away with
this, because during this startup phase the iothread lock is held by
the QEMU main-loop thread which is waiting for us to finish our
display initialization. So we must suppress updateUIInfo until
applicationDidFinishLaunching allows the QEMU main-loop thread to
continue.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Message-id: 20220224101330.967429-2-peter.maydell@linaro.org
Commit: 268c11984e67867c22f53beb3c7f8b98900d66b2
https://github.com/qemu/qemu/commit/268c11984e67867c22f53beb3c7f8b98900d66b2
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-03-02 (Wed, 02 Mar 2022)
Changed paths:
M ui/cocoa.m
Log Message:
-----------
ui/cocoa.m: Remove unnecessary NSAutoreleasePools
In commit 6e657e64cdc478 in 2013 we added some autorelease pools to
deal with complaints from macOS when we made calls into Cocoa from
threads that didn't have automatically created autorelease pools.
Later on, macOS got stricter about forbidding cross-thread Cocoa
calls, and in commit 5588840ff77800e839d8 we restructured the code to
avoid them. This left the autorelease pool creation in several
functions without any purpose; delete it.
We still need the pool in cocoa_refresh() for the clipboard related
code which is called directly there.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Message-id: 20220224101330.967429-3-peter.maydell@linaro.org
Commit: 6629bf78aac7e53f83fd0bcbdbe322e2302dfd1f
https://github.com/qemu/qemu/commit/6629bf78aac7e53f83fd0bcbdbe322e2302dfd1f
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-03-03 (Thu, 03 Mar 2022)
Changed paths:
M docs/system/arm/emulation.rst
M hw/arm/boot.c
M hw/arm/mps2-tz.c
M hw/i2c/i2c_mux_pca954x.c
M hw/input/tsc210x.c
M include/hw/registerfields.h
M target/arm/cpu-param.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/hvf/hvf.c
M target/arm/internals.h
M target/arm/kvm-consts.h
M target/arm/kvm64.c
M target/arm/psci.c
M target/arm/translate-a64.c
M tests/qtest/meson.build
A tests/qtest/npcm7xx_sdhci-test.c
M ui/cocoa.m
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220302'
into staging
target-arm queue:
* mps3-an547: Add missing user ahb interfaces
* hw/arm/mps2-tz.c: Update AN547 documentation URL
* hw/input/tsc210x: Don't abort on bad SPI word widths
* hw/i2c: flatten pca954x mux device
* target/arm: Support PSCI 1.1 and SMCCC 1.0
* target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()
* tests/qtest: add qtests for npcm7xx sdhci
* Implement FEAT_LVA
* Implement FEAT_LPA
* Implement FEAT_LPA2 (but do not enable it yet)
* Report KVM's actual PSCI version to guest in dtb
* ui/cocoa.m: Fix updateUIInfo threading issues
* ui/cocoa.m: Remove unnecessary NSAutoreleasePools
# gpg: Signature made Wed 02 Mar 2022 20:52:06 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20220302: (26 commits)
ui/cocoa.m: Remove unnecessary NSAutoreleasePools
ui/cocoa.m: Fix updateUIInfo threading issues
target/arm: Report KVM's actual PSCI version to guest in dtb
target/arm: Implement FEAT_LPA2
target/arm: Advertise all page sizes for -cpu max
target/arm: Validate tlbi TG matches translation granule in use
target/arm: Fix TLBIRange.base for 16k and 64k pages
target/arm: Introduce tlbi_aa64_get_range
target/arm: Extend arm_fi_to_lfsc to level -1
target/arm: Implement FEAT_LPA
target/arm: Implement FEAT_LVA
target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA
target/arm: Honor TCR_ELx.{I}PS
target/arm: Use MAKE_64BIT_MASK to compute indexmask
target/arm: Pass outputsize down to check_s2_mmu_setup
target/arm: Move arm_pamax out of line
target/arm: Fault on invalid TCR_ELx.TxSZ
target/arm: Set TCR_EL1.TSZ for user-only
hw/registerfields: Add FIELD_SEX<N> and FIELD_SDP<N>
tests/qtest: add qtests for npcm7xx sdhci
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/36eae3a732a1...6629bf78aac7