[Qemu-commits] [qemu/qemu] f85ad2: hw/openrisc/openrisc_sim: Create machine state for...

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: f85ad231e4f4df7962d9385db4605b6a54ddc263
      
https://github.com/qemu/qemu/commit/f85ad231e4f4df7962d9385db4605b6a54ddc263
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2022-02-25 (Fri, 25 Feb 2022)

  Changed paths:
    M hw/openrisc/openrisc_sim.c

  Log Message:
  -----------
  hw/openrisc/openrisc_sim: Create machine state for or1ksim

This will allow us to attach machine state attributes like
the device tree fdt.

Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 76f36985e54e1ebb2c1907bee75b5f7d778a5902
      
https://github.com/qemu/qemu/commit/76f36985e54e1ebb2c1907bee75b5f7d778a5902
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2022-02-25 (Fri, 25 Feb 2022)

  Changed paths:
    M hw/openrisc/openrisc_sim.c

  Log Message:
  -----------
  hw/openrisc/openrisc_sim: Parameterize initialization

Move magic numbers to variables and enums. These will be reused for
upcoming fdt initialization.

Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 22991cfbdfacc195b982d3ee12a823e75ded4b29
      
https://github.com/qemu/qemu/commit/22991cfbdfacc195b982d3ee12a823e75ded4b29
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2022-02-25 (Fri, 25 Feb 2022)

  Changed paths:
    M hw/openrisc/openrisc_sim.c

  Log Message:
  -----------
  hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UART

Currently the OpenRISC SMP configuration only supports 2 cores due to
the UART IRQ routing being limited to 2 cores.  As was done in commit
1eeffbeb11 ("hw/openrisc/openrisc_sim: Use IRQ splitter when connecting
IRQ to multiple CPUs") we can use a splitter to wire more than 2 CPUs.

This patch moves serial initialization out to it's own function and
uses a splitter to connect multiple CPU irq lines to the UART.

Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: f42e09e6a6b3dd996419fe0e6c1bbc68898f3a6e
      
https://github.com/qemu/qemu/commit/f42e09e6a6b3dd996419fe0e6c1bbc68898f3a6e
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2022-02-25 (Fri, 25 Feb 2022)

  Changed paths:
    M hw/openrisc/openrisc_sim.c

  Log Message:
  -----------
  hw/openrisc/openrisc_sim: Increase max_cpus to 4

Now that we no longer have a limit of 2 CPUs due to fixing the
IRQ routing issues we can increase the max.  Here we increase
the limit to 4, we could go higher, but currently OMPIC has a
limit of 4, so we align with that.

Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 5852c1f86529ca6f4055a69d1683f91384fceaed
      
https://github.com/qemu/qemu/commit/5852c1f86529ca6f4055a69d1683f91384fceaed
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2022-02-26 (Sat, 26 Feb 2022)

  Changed paths:
    M configs/targets/or1k-softmmu.mak
    M hw/openrisc/meson.build
    M hw/openrisc/openrisc_sim.c

  Log Message:
  -----------
  hw/openrisc/openrisc_sim: Add automatic device tree generation

Using the device tree means that qemu can now directly tell
the kernel what hardware is configured rather than use having
to maintain and update a separate device tree file.

This patch adds automatic device tree generation support for the
OpenRISC simulator.  A device tree is built up based on the state of the
configure openrisc simulator.

This is then dumped to memory and the load address is passed to the
kernel in register r3.

Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9576abf28280499a4497f39c2fae55bf97285e94
      
https://github.com/qemu/qemu/commit/9576abf28280499a4497f39c2fae55bf97285e94
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2022-02-26 (Sat, 26 Feb 2022)

  Changed paths:
    M hw/openrisc/openrisc_sim.c

  Log Message:
  -----------
  hw/openrisc/openrisc_sim: Add support for initrd loading

The initrd passed via the command line is loaded into memory.  It's
location and size is then added to the device tree so the kernel knows
where to find it.

Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 00483d386901173e84c7965f9f0d678791a75e01
      
https://github.com/qemu/qemu/commit/00483d386901173e84c7965f9f0d678791a75e01
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-02-28 (Mon, 28 Feb 2022)

  Changed paths:
    M configs/targets/or1k-softmmu.mak
    M hw/openrisc/meson.build
    M hw/openrisc/openrisc_sim.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/shorne/tags/or1k-pull-request' into 
staging

OpenRISC patches

 - Add automatic DTS generation to openrisc_sim

# gpg: Signature made Sat 26 Feb 2022 01:39:55 GMT
# gpg:                using RSA key D9C47354AEF86C103A25EFF1C3B31C2D5E6627E4
# gpg: Good signature from "Stafford Horne <shorne@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25  EFF1 C3B3 1C2D 5E66 27E4

* remotes/shorne/tags/or1k-pull-request:
  hw/openrisc/openrisc_sim: Add support for initrd loading
  hw/openrisc/openrisc_sim: Add automatic device tree generation
  hw/openrisc/openrisc_sim: Increase max_cpus to 4
  hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UART
  hw/openrisc/openrisc_sim: Parameterize initialization
  hw/openrisc/openrisc_sim: Create machine state for or1ksim

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/fa435db8ce1d...00483d386901