[Qemu-commits] [qemu/qemu] 5852c1: hw/openrisc/openrisc_sim: Add automatic device tre...

[Peter Maydell]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 5852c1f86529ca6f4055a69d1683f91384fceaed
      
https://github.com/qemu/qemu/commit/5852c1f86529ca6f4055a69d1683f91384fceaed
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2022-02-26 (Sat, 26 Feb 2022)

  Changed paths:
    M configs/targets/or1k-softmmu.mak
    M hw/openrisc/meson.build
    M hw/openrisc/openrisc_sim.c

  Log Message:
  -----------
  hw/openrisc/openrisc_sim: Add automatic device tree generation

Using the device tree means that qemu can now directly tell
the kernel what hardware is configured rather than use having
to maintain and update a separate device tree file.

This patch adds automatic device tree generation support for the
OpenRISC simulator.  A device tree is built up based on the state of the
configure openrisc simulator.

This is then dumped to memory and the load address is passed to the
kernel in register r3.

Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9576abf28280499a4497f39c2fae55bf97285e94
      
https://github.com/qemu/qemu/commit/9576abf28280499a4497f39c2fae55bf97285e94
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2022-02-26 (Sat, 26 Feb 2022)

  Changed paths:
    M hw/openrisc/openrisc_sim.c

  Log Message:
  -----------
  hw/openrisc/openrisc_sim: Add support for initrd loading

The initrd passed via the command line is loaded into memory.  It's
location and size is then added to the device tree so the kernel knows
where to find it.

Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 00483d386901173e84c7965f9f0d678791a75e01
      
https://github.com/qemu/qemu/commit/00483d386901173e84c7965f9f0d678791a75e01
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-02-28 (Mon, 28 Feb 2022)

  Changed paths:
    M configs/targets/or1k-softmmu.mak
    M hw/openrisc/meson.build
    M hw/openrisc/openrisc_sim.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/shorne/tags/or1k-pull-request' into 
staging

OpenRISC patches

 - Add automatic DTS generation to openrisc_sim

# gpg: Signature made Sat 26 Feb 2022 01:39:55 GMT
# gpg:                using RSA key D9C47354AEF86C103A25EFF1C3B31C2D5E6627E4
# gpg: Good signature from "Stafford Horne <shorne@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25  EFF1 C3B3 1C2D 5E66 27E4

* remotes/shorne/tags/or1k-pull-request:
  hw/openrisc/openrisc_sim: Add support for initrd loading
  hw/openrisc/openrisc_sim: Add automatic device tree generation
  hw/openrisc/openrisc_sim: Increase max_cpus to 4
  hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UART
  hw/openrisc/openrisc_sim: Parameterize initialization
  hw/openrisc/openrisc_sim: Create machine state for or1ksim

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/8b3c71d0808b...00483d386901