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[Qemu-commits] [qemu/qemu] 3e3596: nvdimm: Add realize, unrealize callba


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 3e3596: nvdimm: Add realize, unrealize callbacks to NVDIMM...
Date: Sun, 20 Feb 2022 07:11:15 -0800

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 3e35960bf130f759c1b6d72f6a8c08039c08ec16
      
https://github.com/qemu/qemu/commit/3e35960bf130f759c1b6d72f6a8c08039c08ec16
  Author: Shivaprasad G Bhat <sbhat@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M hw/mem/nvdimm.c
    M hw/mem/pc-dimm.c
    M include/hw/mem/nvdimm.h
    M include/hw/mem/pc-dimm.h

  Log Message:
  -----------
  nvdimm: Add realize, unrealize callbacks to NVDIMMDevice class

A new subclass inheriting NVDIMMDevice is going to be introduced in
subsequent patches. The new subclass uses the realize and unrealize
callbacks. Add them on NVDIMMClass to appropriately call them as part
of plug-unplug.

Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: 
<164396253158.109112.1926755104259023743.stgit@ltczzess4.aus.stglabs.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: b5513584a08db477160ea7f0b700a2367028720c
      
https://github.com/qemu/qemu/commit/b5513584a08db477160ea7f0b700a2367028720c
  Author: Shivaprasad G Bhat <sbhat@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_nvdimm.c
    M include/hw/ppc/spapr.h
    M include/hw/ppc/spapr_nvdimm.h

  Log Message:
  -----------
  spapr: nvdimm: Implement H_SCM_FLUSH hcall

The patch adds support for the SCM flush hcall for the nvdimm devices.
To be available for exploitation by guest through the next patch. The
hcall is applicable only for new SPAPR specific device class which is
also introduced in this patch.

The hcall expects the semantics such that the flush to return with
H_LONG_BUSY_ORDER_10_MSEC when the operation is expected to take longer
time along with a continue_token. The hcall to be called again by providing
the continue_token to get the status. So, all fresh requests are put into
a 'pending' list and flush worker is submitted to the thread pool. The
thread pool completion callbacks move the requests to 'completed' list,
which are cleaned up after collecting the return status for the guest
in subsequent hcall from the guest.

The semantics makes it necessary to preserve the continue_tokens and
their return status across migrations. So, the completed flush states
are forwarded to the destination and the pending ones are restarted
at the destination in post_load. The necessary nvdimm flush specific
vmstate structures are also introduced in this patch which are to be
saved in the new SPAPR specific nvdimm device to be introduced in the
following patch.

Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: 
<164396254862.109112.16675611182159105748.stgit@ltczzess4.aus.stglabs.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 8601b4f11d47d36927a617e67687a4a85445ccdd
      
https://github.com/qemu/qemu/commit/8601b4f11d47d36927a617e67687a4a85445ccdd
  Author: Shivaprasad G Bhat <sbhat@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M hw/ppc/spapr_nvdimm.c

  Log Message:
  -----------
  spapr: nvdimm: Introduce spapr-nvdimm device

If the device backend is not persistent memory for the nvdimm, there is
need for explicit IO flushes on the backend to ensure persistence.

On SPAPR, the issue is addressed by adding a new hcall to request for
an explicit flush from the guest when the backend is not pmem. So, the
approach here is to convey when the hcall flush is required in a device
tree property. The guest once it knows the device backend is not pmem,
makes the hcall whenever flush is required.

To set the device tree property, a new PAPR specific device type inheriting
the nvdimm device is implemented. When the backend doesn't have pmem=on
the device tree property "ibm,hcall-flush-required" is set, and the guest
makes hcall H_SCM_FLUSH requesting for an explicit flush. The new device
has boolean property pmem-override which when "on" advertises the device
tree property even when pmem=on for the backend. The flush function
invokes the fdatasync or pmem_persist() based on the type of backend.

The vmstate structures are made part of the spapr-nvdimm device object.
The patch attempts to keep the migration compatibility between source and
destination while rejecting the incompatibles ones with failures.

Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: 
<164396256092.109112.17933240273840803354.stgit@ltczzess4.aus.stglabs.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 4ffcef2a88b4a92c15db00d2cd802ab0950829a4
      
https://github.com/qemu/qemu/commit/4ffcef2a88b4a92c15db00d2cd802ab0950829a4
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/mmu-radix64.c

  Log Message:
  -----------
  target/ppc: raise HV interrupts for partition table entry problems

Invalid or missing partition table entry exceptions should cause HV
interrupts. HDSISR is set to bad MMU config, which is consistent with
the ISA and experimentally matches what POWER9 generates.

Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[ clg: checkpatch fixes ]
Message-Id: <20220216102545.1808018-2-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 5ff40b01244932734ee2ee0075580c653b6dd201
      
https://github.com/qemu/qemu/commit/5ff40b01244932734ee2ee0075580c653b6dd201
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M hw/ppc/ppc.c
    M hw/ppc/spapr_cpu_core.c

  Log Message:
  -----------
  spapr: prevent hdec timer being set up under virtual hypervisor

The spapr virtual hypervisor does not require the hdecr timer.
Remove it.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20220216102545.1808018-3-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 93aeb702105e0dabaf70518bacc7f6fc102c1c34
      
https://github.com/qemu/qemu/commit/93aeb702105e0dabaf70518bacc7f6fc102c1c34
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M hw/ppc/ppc.c
    M include/hw/ppc/ppc.h

  Log Message:
  -----------
  ppc: allow the hdecr timer to be created/destroyed

Machines which don't emulate the HDEC facility are able to use the
timer for something else. Provide functions to start and stop the
hdecr timer.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[ clg: checkpatch fixes ]
Message-Id: <20220216102545.1808018-4-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 4dce0bde3047e773750237390ecd64829f1eac58
      
https://github.com/qemu/qemu/commit/4dce0bde3047e773750237390ecd64829f1eac58
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/mmu-radix64.c

  Log Message:
  -----------
  target/ppc: add vhyp addressing mode helper for radix MMU

The radix on vhyp MMU uses a single-level radix table walk, with the
partition scope mapping provided by the flat QEMU machine memory.

A subsequent change will use the two-level radix walk on vhyp in some
situations, so provide a helper which can abstract that logic.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20220216102545.1808018-5-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: f32d4ab41c467c0e4ddcaff37e4f2af57bcaad8c
      
https://github.com/qemu/qemu/commit/f32d4ab41c467c0e4ddcaff37e4f2af57bcaad8c
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M hw/ppc/spapr.c
    M target/ppc/cpu.h
    M target/ppc/mmu-radix64.c

  Log Message:
  -----------
  target/ppc: make vhyp get_pate method take lpid and return success

In prepartion for implementing a full partition table option for
vhyp, update the get_pate method to take an lpid and return a
success/fail indicator.

The spapr implementation currently just asserts lpid is always 0
and always return success.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[ clg: checkpatch fixes ]
Message-Id: <20220216102545.1808018-6-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 4c6cf6b295d233552fb448ed4a8b4356e18dfabb
      
https://github.com/qemu/qemu/commit/4c6cf6b295d233552fb448ed4a8b4356e18dfabb
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/excp_helper.c

  Log Message:
  -----------
  target/ppc: add helper for books vhyp hypercall handler

The virtual hypervisor currently always intercepts and handles
hypercalls but with a future change this will not always be the case.

Add a helper for the test so the logic is abstracted from the mechanism.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20220216102545.1808018-7-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 3680e99461b6d33bd45fce9b4bd5e20475c13525
      
https://github.com/qemu/qemu/commit/3680e99461b6d33bd45fce9b4bd5e20475c13525
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/excp_helper.c

  Log Message:
  -----------
  target/ppc: Add powerpc_reset_excp_state helper

This moves the logic to reset the QEMU exception state into its own
function.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[ clg: checkpatch fixes ]
Message-Id: <20220216102545.1808018-8-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 7cebc5db2eba6dc655b62af41e52716fc4fa66ae
      
https://github.com/qemu/qemu/commit/7cebc5db2eba6dc655b62af41e52716fc4fa66ae
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M hw/ppc/pegasos2.c
    M hw/ppc/spapr.c
    M target/ppc/cpu.h
    M target/ppc/excp_helper.c
    M target/ppc/mmu-radix64.c

  Log Message:
  -----------
  target/ppc: Introduce a vhyp framework for nested HV support

Introduce virtual hypervisor methods that can support a "Nested KVM HV"
implementation using the bare metal 2-level radix MMU, and using HV
exceptions to return from H_ENTER_NESTED (rather than cause interrupts).

HV exceptions can now be raised in the TCG spapr machine when running a
nested KVM HV guest. The main ones are the lev==1 syscall, the hdecr,
hdsi and hisi, hv fu, and hv emu, and h_virt external interrupts.

HV exceptions are intercepted in the exception handler code and instead
of causing interrupts in the guest and switching the machine to HV mode,
they go to the vhyp where it may exit the H_ENTER_NESTED hcall with the
interrupt vector numer as return value as required by the hcall API.

Address translation is provided by the 2-level page table walker that is
implemented for the bare metal radix MMU. The partition scope page table
is pointed to the L1's partition scope by the get_pate vhc method.

Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220216102545.1808018-9-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 120f738a4671977481546ff3027232f0c911127d
      
https://github.com/qemu/qemu/commit/120f738a4671977481546ff3027232f0c911127d
  Author: Nicholas Piggin <npiggin@gmail.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_caps.c
    M hw/ppc/spapr_hcall.c
    M include/hw/ppc/spapr.h
    M include/hw/ppc/spapr_cpu_core.h

  Log Message:
  -----------
  spapr: implement nested-hv capability for the virtual hypervisor

This implements the Nested KVM HV hcall API for spapr under TCG.

The L2 is switched in when the H_ENTER_NESTED hcall is made, and the
L1 is switched back in returned from the hcall when a HV exception
is sent to the vhyp. Register state is copied in and out according to
the nested KVM HV hcall API specification.

The hdecr timer is started when the L2 is switched in, and it provides
the HDEC / 0x980 return to L1.

The MMU re-uses the bare metal radix 2-level page table walker by
using the get_pate method to point the MMU to the nested partition
table entry. MMU faults due to partition scope errors raise HV
exceptions and accordingly are routed back to the L1.

The MMU does not tag translations for the L1 (direct) vs L2 (nested)
guests, so the TLB is flushed on any L1<->L2 transition (hcall entry
and exit).

Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: checkpatch fixes ]
Message-Id: <20220216102545.1808018-10-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: acf629eb7a38ed83c34bcd8242590e3611d59d0f
      
https://github.com/qemu/qemu/commit/acf629eb7a38ed83c34bcd8242590e3611d59d0f
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Remove not implemented comments

The /* XXX : not implemented */ comments all over cpu_init are
confusing and ambiguous.

Do they mean not implemented by QEMU, not implemented in a specific
access mode? Not implemented by the CPU? Do they apply to just the
register right after or to a whole block? Do they mean we have an
action to take in the future to implement these?  Are they only
informative?

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 363bd7d0d55466cd363bc2776ae6aa40070beb98
      
https://github.com/qemu/qemu/commit/363bd7d0d55466cd363bc2776ae6aa40070beb98
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Remove G2LE init code

The G2LE CPU initialization code is the same as the G2. Use the latter
for both.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: e78280a237ecfea0278c62cb503d12185a505189
      
https://github.com/qemu/qemu/commit/e78280a237ecfea0278c62cb503d12185a505189
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Group registration of generic SPRs

The top level init_proc calls register_generic_sprs but also registers
some other SPRs outside of that function. Let's group everything into
a single place.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 024b40e0ae065af4e3ed4a70250100a634067a72
      
https://github.com/qemu/qemu/commit/024b40e0ae065af4e3ed4a70250100a634067a72
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Move Timebase registration into the common function

Now that the 601 was removed, all of our CPUs have a timebase, so that
can be moved into the common function.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-5-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 4ffb8c5e434195ce1d8a6bc148e6f4971d089258
      
https://github.com/qemu/qemu/commit/4ffb8c5e434195ce1d8a6bc148e6f4971d089258
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Avoid nested SPR register functions

Make sure that every register_*_sprs function only has calls to
spr_register* to register individual SPRs. Do not allow nesting. This
makes the code easier to follow and a look at init_proc_* should
suffice to know what SPRs a CPU has.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-6-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: acd1f78870aca0b7f9e54d788b9bc3d36f80f01d
      
https://github.com/qemu/qemu/commit/acd1f78870aca0b7f9e54d788b9bc3d36f80f01d
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Move 405 SPRs into register_405_sprs

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-7-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: e599bcedf9407dcdc8a5d98138744080e118ef3f
      
https://github.com/qemu/qemu/commit/e599bcedf9407dcdc8a5d98138744080e118ef3f
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Move G2 SPRs into register_G2_sprs

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-8-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 1a71c5d158529bcfdadb131714710efb7679f529
      
https://github.com/qemu/qemu/commit/1a71c5d158529bcfdadb131714710efb7679f529
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Decouple G2 SPR registration from 755

We're considering these two to be in different CPU families (6xx and
7xx), so keep their SPR registration separate.

The code was copied into register_G2_sprs and the common function was
renamed to apply only to the 755.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-9-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 674f45096f7dafefe22269dd017417f506b54c2b
      
https://github.com/qemu/qemu/commit/674f45096f7dafefe22269dd017417f506b54c2b
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx

We're considering these two to be from different CPU families, so
duplicate some code to keep them separate.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-10-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 49ed82b29a5ce3effc8aa199ff626f3cc9f614d8
      
https://github.com/qemu/qemu/commit/49ed82b29a5ce3effc8aa199ff626f3cc9f614d8
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Deduplicate 440 SPR registration

Move some of the 440 registers that are being repeated in the 440*
CPUs to register_440_sprs.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-11-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: d2b29d0ade43db99af4f7a176abb55c0a2fbf0e4
      
https://github.com/qemu/qemu/commit/d2b29d0ade43db99af4f7a176abb55c0a2fbf0e4
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Deduplicate 603 SPR registration

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-12-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 20f6fb99b2a820f4c0e067c46efc63ea00f90180
      
https://github.com/qemu/qemu/commit/20f6fb99b2a820f4c0e067c46efc63ea00f90180
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Deduplicate 604 SPR registration

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-13-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: a5d1120b1ddbce120dc6d963364d778b6550ce66
      
https://github.com/qemu/qemu/commit/a5d1120b1ddbce120dc6d963364d778b6550ce66
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Deduplicate 745/755 SPR registration

The 745 and 755 can share the HID registration, so move it all into
register_755_sprs, which applies for both CPUs.

Also rename that function to register_745_sprs, since the 745 is the
earliest of the two. This will help with separating 755-specific
registers in a subsequent patch.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-14-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 0301b39c78c8de08c0806d42640d606238b37d2f
      
https://github.com/qemu/qemu/commit/0301b39c78c8de08c0806d42640d606238b37d2f
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Deduplicate 7xx SPR registration

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-15-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 28930245a823c3e452d65523c9ad01f56801df72
      
https://github.com/qemu/qemu/commit/28930245a823c3e452d65523c9ad01f56801df72
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Move 755 L2 cache SPRs into a function

This is just to have 755-specific registers contained into a function,
intead of leaving them open-coded in init_proc_755. It makes init_proc
easier to read and keeps later patches that touch this code a bit
cleaner.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-16-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: a3a27674883e1d4fb205f1f5f1dcfb646fb0ff70
      
https://github.com/qemu/qemu/commit/a3a27674883e1d4fb205f1f5f1dcfb646fb0ff70
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Move e300 SPR registration into a function

This is done to improve init_proc readability and to make subsequent
patches that touch this code a bit cleaner.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-17-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 3b18ec7687de2bf7ef5eef6e5db3a544ee8c8bb5
      
https://github.com/qemu/qemu/commit/3b18ec7687de2bf7ef5eef6e5db3a544ee8c8bb5
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Move 604e SPR registration into a function

This is done to improve init_proc readability and to make subsequent
patches that touch this code a bit cleaner.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-18-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 9f33f3d8760f1bb1c2cf6de4f67acbcbd7c05c40
      
https://github.com/qemu/qemu/commit/9f33f3d8760f1bb1c2cf6de4f67acbcbd7c05c40
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Reuse init_proc_603 for the e300

init_proc_603 is defined after init_proc_e300, so I had to move some
code around to make it work.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-19-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 0df0ca16b4aa491e9228d887b80ed392b2ef1039
      
https://github.com/qemu/qemu/commit/0df0ca16b4aa491e9228d887b80ed392b2ef1039
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Reuse init_proc_604 for the 604e

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-20-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: c1f215772810626930d44132adc080eb488c7e60
      
https://github.com/qemu/qemu/commit/c1f215772810626930d44132adc080eb488c7e60
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Reuse init_proc_745 for the 755

The init_proc_755 function is identical to the 745 one except for the
755-specific registers. I think it is worth it to make them share
code.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-21-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 217781afdef2b42ee3a15a78b4b9d685ff2b9aa4
      
https://github.com/qemu/qemu/commit/217781afdef2b42ee3a15a78b4b9d685ff2b9aa4
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Rename register_ne_601_sprs

The important part of this function is that it applies to non-embedded
CPUs, not that it also applies to the 601. We removed support for the
601 anyway, so rename this function.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-22-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 2a48d83dfd74a6c15a758039313a4a7cf82be2d3
      
https://github.com/qemu/qemu/commit/2a48d83dfd74a6c15a758039313a4a7cf82be2d3
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Remove register_usprg3_sprs

This function registers just one SPR and has only two callers, so open
code it.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-23-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 99e964ef955e9cd0c1dd0ebe3e432bee8f576eee
      
https://github.com/qemu/qemu/commit/99e964ef955e9cd0c1dd0ebe3e432bee8f576eee
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c
    A target/ppc/spr_common.h
    R target/ppc/spr_tcg.h
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Rename spr_tcg.h to spr_common.h

Initial intent for the spr_tcg header was to expose the spr_read|write
callbacks that are only used by TCG code. However, although these
routines are TCG-specific, the KVM code needs access to env->sprs
which creation is currently coupled to the callback registration.

We are probably not going to decouple SPR creation and TCG callback
registration any time soon, so let's rename the header to spr_common
to accomodate the register_*_sprs functions that will be moved out of
cpu_init.c in the following patches.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-24-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 917ea4381add2eb57494c6aca24d8d80070fb9b1
      
https://github.com/qemu/qemu/commit/917ea4381add2eb57494c6aca24d8d80070fb9b1
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c
    M target/ppc/spr_common.h

  Log Message:
  -----------
  target/ppc: cpu_init: Expose some SPR registration helpers

The following patches will move CPU-specific code into separate files,
so expose the most used SPR registration functions:

register_sdr1_sprs         | 22 callers
register_low_BATs          | 20 callers
register_non_embedded_sprs | 19 callers
register_high_BATs         | 10 callers
register_thrm_sprs         | 8 callers
register_usprgh_sprs       | 6 callers
register_6xx_7xx_soft_tlb  | only 3 callers, but it helps to
                             keep the soft TLB code consistent.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-25-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 565873b3804e90fafba23bb09489790ec4e50f09
      
https://github.com/qemu/qemu/commit/565873b3804e90fafba23bb09489790ec4e50f09
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c
    M target/ppc/spr_common.h

  Log Message:
  -----------
  target/ppc: cpu_init: Move SPR registration macros to a header

Put the SPR registration macros in a header that is accessible outside
of cpu_init.c. The following patches will move CPU-specific code to
separate files and will need to access it.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-26-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: b58fd0c39b6dd9f955b84c74a358e07a83e257c4
      
https://github.com/qemu/qemu/commit/b58fd0c39b6dd9f955b84c74a358e07a83e257c4
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  target/ppc: cpu_init: Move check_pow and QOM macros to a header

These will need to be accessed from other files once we move the CPUs
code to separate files.

The check_pow_hid0 and check_pow_hid0_74xx are too specific to be
moved to a header so I'll deal with them later when splitting this
code between the multiple CPU families.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-27-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 65e0446c86ee70d2125c1f1d1e36e6c2dfb08642
      
https://github.com/qemu/qemu/commit/65e0446c86ee70d2125c1f1d1e36e6c2dfb08642
  Author: Fabiano Rosas <farosas@linux.ibm.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M target/ppc/cpu_init.c
    M target/ppc/helper_regs.c
    M target/ppc/spr_common.h

  Log Message:
  -----------
  target/ppc: Move common SPR functions out of cpu_init

Let's leave cpu_init with just generic CPU initialization and
QOM-related functions.

The rest of the SPR registration functions will be moved in the
following patches along with the code that uses them. These are only
the commonly used ones.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-28-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: e670f6d825d4dee248b311197fd4048469d6772b
      
https://github.com/qemu/qemu/commit/e670f6d825d4dee248b311197fd4048469d6772b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-02-20 (Sun, 20 Feb 2022)

  Changed paths:
    M hw/mem/nvdimm.c
    M hw/mem/pc-dimm.c
    M hw/ppc/pegasos2.c
    M hw/ppc/ppc.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_caps.c
    M hw/ppc/spapr_cpu_core.c
    M hw/ppc/spapr_hcall.c
    M hw/ppc/spapr_nvdimm.c
    M include/hw/mem/nvdimm.h
    M include/hw/mem/pc-dimm.h
    M include/hw/ppc/ppc.h
    M include/hw/ppc/spapr.h
    M include/hw/ppc/spapr_cpu_core.h
    M include/hw/ppc/spapr_nvdimm.h
    M target/ppc/cpu.h
    M target/ppc/cpu_init.c
    M target/ppc/excp_helper.c
    M target/ppc/helper_regs.c
    M target/ppc/mmu-radix64.c
    A target/ppc/spr_common.h
    R target/ppc/spr_tcg.h
    M target/ppc/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220218' into 
staging

ppc-7.0 queue

* target/ppc: SPR registration cleanups (Fabiano)
* ppc: nested KVM HV for spapr virtual hypervisor (Nicholas)
* spapr: nvdimm: Introduce spapr-nvdimm device (Shivaprasad)

# gpg: Signature made Fri 18 Feb 2022 07:59:29 GMT
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* remotes/legoater/tags/pull-ppc-20220218: (39 commits)
  target/ppc: Move common SPR functions out of cpu_init
  target/ppc: cpu_init: Move check_pow and QOM macros to a header
  target/ppc: cpu_init: Move SPR registration macros to a header
  target/ppc: cpu_init: Expose some SPR registration helpers
  target/ppc: Rename spr_tcg.h to spr_common.h
  target/ppc: cpu_init: Remove register_usprg3_sprs
  target/ppc: cpu_init: Rename register_ne_601_sprs
  target/ppc: cpu_init: Reuse init_proc_745 for the 755
  target/ppc: cpu_init: Reuse init_proc_604 for the 604e
  target/ppc: cpu_init: Reuse init_proc_603 for the e300
  target/ppc: cpu_init: Move 604e SPR registration into a function
  target/ppc: cpu_init: Move e300 SPR registration into a function
  target/ppc: cpu_init: Move 755 L2 cache SPRs into a function
  target/ppc: cpu_init: Deduplicate 7xx SPR registration
  target/ppc: cpu_init: Deduplicate 745/755 SPR registration
  target/ppc: cpu_init: Deduplicate 604 SPR registration
  target/ppc: cpu_init: Deduplicate 603 SPR registration
  target/ppc: cpu_init: Deduplicate 440 SPR registration
  target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx
  target/ppc: cpu_init: Decouple G2 SPR registration from 755
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/242f2cae782d...e670f6d825d4



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