[Qemu-commits] [qemu/qemu] a6b7bd: include: hw: remove ibex

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[Qemu-commits] [qemu/qemu] a6b7bd: include: hw: remove ibex_plic.h

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] a6b7bd: include: hw: remove ibex_plic.h
Date:	Wed, 16 Feb 2022 01:57:46 -0800
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: a6b7bd35f307bafb1f05d248194ae976e29949c8
      
https://github.com/qemu/qemu/commit/a6b7bd35f307bafb1f05d248194ae976e29949c8
  Author: Wilfred Mallawa <wilfred.mallawa@wdc.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    R include/hw/intc/ibex_plic.h

  Log Message:
  -----------
  include: hw: remove ibex_plic.h

This patch removes the left-over/unused `ibex_plic.h` file. Previously
used by opentitan, which now follows the RISC-V standard and uses the
SiFivePlicState.

Fixes: 434e7e021 ("hw/intc: Remove the Ibex PLIC")
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220121055005.3159846-1-alistair.francis@opensource.wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f42483d776bce29a9925ed61cc10eb27a5b2446c
      
https://github.com/qemu/qemu/commit/f42483d776bce29a9925ed61cc10eb27a5b2446c
  Author: Petr Tesarik <ptesarik@suse.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M hw/core/generic-loader.c

  Log Message:
  -----------
  Allow setting up to 8 bytes with the generic loader

The documentation for the generic loader says that "the maximum size of
the data is 8 bytes". However, attempts to set data-len=8 trigger the
following assertion failure:

../hw/core/generic-loader.c:59: generic_loader_reset: Assertion `s->data_len < 
sizeof(s->data)' failed.

The type of s->data is uint64_t (i.e. 8 bytes long), so I believe this
assert should use <= instead of <.

Fixes: e481a1f63c93 ("generic-loader: Add a generic loader")
Signed-off-by: Petr Tesarik <ptesarik@suse.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120092715.7805-1-ptesarik@suse.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6c3a9247259940069402ee169e63aac0ac5f8f6b
      
https://github.com/qemu/qemu/commit/6c3a9247259940069402ee169e63aac0ac5f8f6b
  Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/gdbstub.c

  Log Message:
  -----------
  target/riscv: correct "code should not be reached" for x-rv128

The addition of uxl support in gdbstub adds a few checks on the maximum
register length, but omitted MXL_RV128, an experimental feature.
This patch makes rv128 react as rv64, as previously.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220124202456.420258-1-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 466292bd4aa0908794116d96dad816e4155e8b69
      
https://github.com/qemu/qemu/commit/466292bd4aa0908794116d96dad816e4155e8b69
  Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct 
RISCVCPUConfig'

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220202005249.3566542-2-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3b91323e33d85150eb482458b1f1e2b08a59d8a2
      
https://github.com/qemu/qemu/commit/3b91323e33d85150eb482458b1f1e2b08a59d8a2
  Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr

As the number of extensions is growing, copying them individiually
into the DisasContext will scale less and less... instead we populate
a pointer to the RISCVCPUConfig structure in the DisasContext.

This adds an extra indirection when checking for the availability of
an extension (compared to copying the fields into DisasContext).
While not a performance problem today, we can always (shallow) copy
the entire structure into the DisasContext (instead of putting a
pointer to it) if this is ever deemed necessary.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220202005249.3566542-3-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 79bf3b51acb4a6245b500005859e8b1d1611302f
      
https://github.com/qemu/qemu/commit/79bf3b51acb4a6245b500005859e8b1d1611302f
  Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/insn_trans/trans_rvzfh.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: access configuration through cfg_ptr in DisasContext

The implementation in trans_{rvi,rvv,rvzfh}.c.inc accesses the shallow
copies (in DisasContext) of some of the elements available in the
RISCVCPUConfig structure.  This commit redirects accesses to use the
cfg_ptr copied into DisasContext and removes the shallow copies.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220202005249.3566542-4-philipp.tomsich@vrull.eu>
[ Changes by AF:
 - Fixup checkpatch failures
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f2a32bec8f0da993f67698b6c7ebd60e0f19622e
      
https://github.com/qemu/qemu/commit/f2a32bec8f0da993f67698b6c7ebd60e0f19622e
  Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/insn_trans/trans_rvb.c.inc

  Log Message:
  -----------
  target/riscv: access cfg structure through DisasContext

The Zb[abcs] support code still uses the RISCV_CPU macros to access
the configuration information (i.e., check whether an extension is
available/enabled).  Now that we provide this information directly
from DisasContext, we can access this directly via the cfg_ptr field.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220202005249.3566542-5-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 5e199b6bdc544658ecc9d614779b2cf3fe215ead
      
https://github.com/qemu/qemu/commit/5e199b6bdc544658ecc9d614779b2cf3fe215ead
  Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: iterate over a table of decoders

To split up the decoder into multiple functions (both to support
vendor-specific opcodes in separate files and to simplify maintenance
of orthogonal extensions), this changes decode_op to iterate over a
table of decoders predicated on guard functions.

This commit only adds the new structure and the table, allowing for
the easy addition of additional decoders in the future.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220202005249.3566542-6-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0d429bd243dd391e844213d97bb14a0f119b33b5
      
https://github.com/qemu/qemu/commit/0d429bd243dd391e844213d97bb14a0f119b33b5
  Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    A target/riscv/XVentanaCondOps.decode
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    A target/riscv/insn_trans/trans_xventanacondops.c.inc
    M target/riscv/meson.build
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Add XVentanaCondOps custom extension

This adds the decoder and translation for the XVentanaCondOps custom
extension (vendor-defined by Ventana Micro Systems), which is
documented at 
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf

This commit then also adds a guard-function (has_XVentanaCondOps_p)
and the decoder function to the table of decoders, enabling the
support for the XVentanaCondOps extension.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220202005249.3566542-7-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 34888f01b7a905bbbddf1fc8f41691f43b94fcd6
      
https://github.com/qemu/qemu/commit/34888f01b7a905bbbddf1fc8f41691f43b94fcd6
  Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  target/riscv: add a MAINTAINERS entry for XVentanaCondOps

The XVentanaCondOps extension is supported by VRULL on behalf of the
Ventana Micro.  Add myself as a point-of-contact.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220202005249.3566542-8-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ac6bcf4d467a091b11ece782f4bf0a41e0f59cef
      
https://github.com/qemu/qemu/commit/ac6bcf4d467a091b11ece782f4bf0a41e0f59cef
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: Fix vill field write in vtype

The guest should be able to set the vill bit as part of vsetvl.

Currently we may set env->vill to 1 in the vsetvl helper, but there
is nowhere that we set it to 0, so once it transitions to 1 it's stuck
there until the system is reset.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220201064601.41143-1-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: dceecac8a2fa36f6ab6927da2052f06e2de7a2a4
      
https://github.com/qemu/qemu/commit/dceecac8a2fa36f6ab6927da2052f06e2de7a2a4
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode

We should be returning illegal instruction trap when RV64 HS-mode tries
to access RV32 HS-mode CSR.

Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions")
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-2-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 881df35d3df52efd845087fb76d0b0116b366468
      
https://github.com/qemu/qemu/commit/881df35d3df52efd845087fb76d0b0116b366468
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Implement SGEIP bit in hip and hie CSRs

A hypervisor can optionally take guest external interrupts using
SGEIP bit of hip and hie CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-3-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: cd032fe75c1f7b24ccad772d50bfb689e7f5835d
      
https://github.com/qemu/qemu/commit/cd032fe75c1f7b24ccad772d50bfb689e7f5835d
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/machine.c

  Log Message:
  -----------
  target/riscv: Implement hgeie and hgeip CSRs

The hgeie and hgeip CSRs are required for emulating an external
interrupt controller capable of injecting virtual external interrupt
to Guest/VM running at VS-level.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-4-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 02d9565b92c97af6bac2ff1bb18967a5e95b9694
      
https://github.com/qemu/qemu/commit/02d9565b92c97af6bac2ff1bb18967a5e95b9694
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Improve delivery of guest external interrupts

The guest external interrupts from an interrupt controller are
delivered only when the Guest/VM is running (i.e. V=1). This means
any guest external interrupt which is triggered while the Guest/VM
is not running (i.e. V=0) will be missed on QEMU resulting in Guest
with sluggish response to serial console input and other I/O events.

To solve this, we check and inject interrupt after setting V=1.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-5-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f87adf23fa66fd07d9f003173d386c0a54d9ddb0
      
https://github.com/qemu/qemu/commit/f87adf23fa66fd07d9f003173d386c0a54d9ddb0
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Allow setting CPU feature from machine/device emulation

The machine or device emulation should be able to force set certain
CPU features because:
1) We can have certain CPU features which are in-general optional
   but implemented by RISC-V CPUs on the machine.
2) We can have devices which require a certain CPU feature. For example,
   AIA IMSIC devices expect AIA CSRs implemented by RISC-V CPUs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-6-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 32b0ada038629311aa90499a68de29473df7935d
      
https://github.com/qemu/qemu/commit/32b0ada038629311aa90499a68de29473df7935d
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Add AIA cpu feature

We define a CPU feature for AIA CSR support in RISC-V CPUs which
can be set by machine/device emulation. The RISC-V CSR emulation
will also check this feature for emulating AIA CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-7-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: aa7508bbc63afe5c9fb65ce3353c9828ee12c4b3
      
https://github.com/qemu/qemu/commit/aa7508bbc63afe5c9fb65ce3353c9828ee12c4b3
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/cpu_bits.h

  Log Message:
  -----------
  target/riscv: Add defines for AIA CSRs

The RISC-V AIA specification extends RISC-V local interrupts and
introduces new CSRs. This patch adds defines for the new AIA CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-8-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 69077dd687a5e388943548b0eb8e3747cc047324
      
https://github.com/qemu/qemu/commit/69077dd687a5e388943548b0eb8e3747cc047324
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Allow AIA device emulation to set ireg rmw callback

The AIA device emulation (such as AIA IMSIC) should be able to set
(or provide) AIA ireg read-modify-write callback for each privilege
level of a RISC-V HART.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-9-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 43dc93af36dced9d23911be2ed6b0fe82bf3c42c
      
https://github.com/qemu/qemu/commit/43dc93af36dced9d23911be2ed6b0fe82bf3c42c
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/machine.c

  Log Message:
  -----------
  target/riscv: Implement AIA local interrupt priorities

The AIA spec defines programmable 8-bit priority for each local interrupt
at M-level, S-level and VS-level so we extend local interrupt processing
to consider AIA interrupt priorities. The AIA CSRs which help software
configure local interrupt priorities will be added by subsequent patches.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220204174700.534953-10-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d028ac7512f1a781a5cba7659a1d25dc972afdd4
      
https://github.com/qemu/qemu/commit/d028ac7512f1a781a5cba7659a1d25dc972afdd4
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/machine.c

  Log Message:
  -----------
  target/riscv: Implement AIA CSRs for 64 local interrupts on RV32

The AIA specification adds new CSRs for RV32 so that RISC-V hart can
support 64 local interrupts on both RV32 and RV64.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-11-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2b6023987955a887aae3ad6882557960b2253a4f
      
https://github.com/qemu/qemu/commit/2b6023987955a887aae3ad6882557960b2253a4f
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/csr.c
    M target/riscv/machine.c

  Log Message:
  -----------
  target/riscv: Implement AIA hvictl and hviprioX CSRs

The AIA hvictl and hviprioX CSRs allow hypervisor to control
interrupts visible at VS-level. This patch implements AIA hvictl
and hviprioX CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-12-anup@brainfault.org
[ Changes by AF:
 - Fix possible unintilised variable error in rmw_sie()
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d0237b4df07e7b532b9b917639d6eb6b2c825c67
      
https://github.com/qemu/qemu/commit/d0237b4df07e7b532b9b917639d6eb6b2c825c67
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Implement AIA interrupt filtering CSRs

The AIA specificaiton adds interrupt filtering support for M-mode
and HS-mode. Using AIA interrupt filtering M-mode and H-mode can
take local interrupt 13 or above and selectively inject same local
interrupt to lower privilege modes.

At the moment, we don't have any local interrupts above 12 so we
add dummy implementation (i.e. read zero and ignore write) of AIA
interrupt filtering CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-13-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: c7de92b4e829b0df4087371b23e41bbe8aec766d
      
https://github.com/qemu/qemu/commit/c7de92b4e829b0df4087371b23e41bbe8aec766d
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs

The AIA specification introduces new [m|s|vs]topi CSRs for
reporting pending local IRQ number and associated IRQ priority.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-14-anup@brainfault.org
[ Changed by AF:
 - Fixup indentation
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d1ceff405ae476127ec805ae99afa71d095a1bd2
      
https://github.com/qemu/qemu/commit/d1ceff405ae476127ec805ae99afa71d095a1bd2
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/csr.c
    M target/riscv/machine.c

  Log Message:
  -----------
  target/riscv: Implement AIA xiselect and xireg CSRs

The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
which allow indirect access to interrupt priority arrays and per-HART
IMSIC registers. This patch implements AIA xiselect and xireg CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-15-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ac4b0302b0ca986a759538f453b44037c7b66dd9
      
https://github.com/qemu/qemu/commit/ac4b0302b0ca986a759538f453b44037c7b66dd9
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Implement AIA IMSIC interface CSRs

The AIA specification defines IMSIC interface CSRs for easy access
to the per-HART IMSIC registers without using indirect xiselect and
xireg CSRs. This patch implements the AIA IMSIC interface CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-16-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d207863cd3ed056055e2324a4abe47f54e7c6384
      
https://github.com/qemu/qemu/commit/d207863cd3ed056055e2324a4abe47f54e7c6384
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: virt: Use AIA INTC compatible string when available

We should use the AIA INTC compatible string in the CPU INTC
DT nodes when the CPUs support AIA feature. This will allow
Linux INTC driver to use AIA local interrupt CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-17-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 91870b510ae5d1cb9688231b8f01dceaab64de68
      
https://github.com/qemu/qemu/commit/91870b510ae5d1cb9688231b8f01dceaab64de68
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Allow users to force enable AIA CSRs in HART

We add "x-aia" command-line option for RISC-V HART using which
allows users to force enable CPU AIA CSRs without changing the
interrupt controller available in RISC-V machine.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-18-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e8f79343cfc886aaa225cec9faf6881f75945209
      
https://github.com/qemu/qemu/commit/e8f79343cfc886aaa225cec9faf6881f75945209
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M hw/intc/Kconfig
    M hw/intc/meson.build
    A hw/intc/riscv_aplic.c
    A include/hw/intc/riscv_aplic.h

  Log Message:
  -----------
  hw/intc: Add RISC-V AIA APLIC device emulation

The RISC-V AIA (Advanced Interrupt Architecture) defines a new
interrupt controller for wired interrupts called APLIC (Advanced
Platform Level Interrupt Controller). The APLIC is capabable of
forwarding wired interupts to RISC-V HARTs directly or as MSIs
(Message Signaled Interupts).

This patch adds device emulation for RISC-V AIA APLIC.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-19-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 05e6ca5e156d1d114d1eb878cae9744cb4a539e3
      
https://github.com/qemu/qemu/commit/05e6ca5e156d1d114d1eb878cae9744cb4a539e3
  Author: Guo Ren <ren_guo@c-sky.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Ignore reserved bits in PTE for RV64

Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
need to ignore them. They cannot be a part of ppn.

1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
   4.4 Sv39: Page-Based 39-bit Virtual-Memory System
   4.5 Sv48: Page-Based 48-bit Virtual-Memory System

2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: b6ecc63c569bb88c0fcadf79fb92bf4b88aefea8
      
https://github.com/qemu/qemu/commit/b6ecc63c569bb88c0fcadf79fb92bf4b88aefea8
  Author: Weiwei Li <liweiwei@iscas.ac.cn>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE

For non-leaf PTEs, the D, A, and U bits are reserved for future standard use.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2bacb22446a45b07f542d32b6d760da757233b20
      
https://github.com/qemu/qemu/commit/2bacb22446a45b07f542d32b6d760da757233b20
  Author: Weiwei Li <liweiwei@iscas.ac.cn>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: add support for svnapot extension

- add PTE_N bit
- add PTE_N bit check for inner PTE
- update address translation to support 64KiB continuous region (napot_bits = 4)

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: c5d77ddd8ebcd33da9561982e29c8f4b2dec0978
      
https://github.com/qemu/qemu/commit/c5d77ddd8ebcd33da9561982e29c8f4b2dec0978
  Author: Weiwei Li <liweiwei@iscas.ac.cn>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/insn32.decode
    A target/riscv/insn_trans/trans_svinval.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: add support for svinval extension

- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, 
hfence.vvma and hfence.gvma except extension check
- do nothing other than extension check for sfence.w.inval and sfence.inval.ir

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: bbce8ba8e6bddcd77abef4810a9426bad9939f3b
      
https://github.com/qemu/qemu/commit/bbce8ba8e6bddcd77abef4810a9426bad9939f3b
  Author: Weiwei Li <liweiwei@iscas.ac.cn>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: add support for svpbmt extension

- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, 
since QEMU is sequentially consistent and doesn't model PMAs currently
- add PTE_PBMT bit check for inner PTE

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7035b8420fa52e8c94cf4317c0f88c1b73ced28d
      
https://github.com/qemu/qemu/commit/7035b8420fa52e8c94cf4317c0f88c1b73ced28d
  Author: Yu Li <liyu.yukiteru@bytedance.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M docs/system/riscv/virt.rst

  Log Message:
  -----------
  docs/system: riscv: Update description of CPU

Since the hypervisor extension been non experimental and enabled for
default CPU, the previous command is no longer available and the
option `x-h=true` or `h=true` is also no longer required.

Signed-off-by: Yu Li <liyu.yukiteru@bytedance.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <9040401e-8f87-ef4a-d840-6703f08d068c@bytedance.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: c13b8e9973635f34f3ce4356af27a311c993729c
      
https://github.com/qemu/qemu/commit/c13b8e9973635f34f3ce4356af27a311c993729c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M MAINTAINERS
    M docs/system/riscv/virt.rst
    M hw/core/generic-loader.c
    M hw/intc/Kconfig
    M hw/intc/meson.build
    A hw/intc/riscv_aplic.c
    M hw/riscv/virt.c
    R include/hw/intc/ibex_plic.h
    A include/hw/intc/riscv_aplic.h
    A target/riscv/XVentanaCondOps.decode
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/gdbstub.c
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvb.c.inc
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/insn_trans/trans_rvzfh.c.inc
    A target/riscv/insn_trans/trans_svinval.c.inc
    A target/riscv/insn_trans/trans_xventanacondops.c.inc
    M target/riscv/machine.c
    M target/riscv/meson.build
    M target/riscv/translate.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20220216' into staging

Fourth RISC-V PR for QEMU 7.0

 * Remove old Ibex PLIC header file
 * Allow writing 8 bytes with generic loader
 * Fixes for RV128
 * Refactor RISC-V CPU configs
 * Initial support for XVentanaCondOps custom extension
 * Fix for vill field in vtype
 * Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
 * Support for svnapot, svinval and svpbmt extensions

# gpg: Signature made Wed 16 Feb 2022 06:24:52 GMT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20220216: (35 commits)
  docs/system: riscv: Update description of CPU
  target/riscv: add support for svpbmt extension
  target/riscv: add support for svinval extension
  target/riscv: add support for svnapot extension
  target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
  target/riscv: Ignore reserved bits in PTE for RV64
  hw/intc: Add RISC-V AIA APLIC device emulation
  target/riscv: Allow users to force enable AIA CSRs in HART
  hw/riscv: virt: Use AIA INTC compatible string when available
  target/riscv: Implement AIA IMSIC interface CSRs
  target/riscv: Implement AIA xiselect and xireg CSRs
  target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
  target/riscv: Implement AIA interrupt filtering CSRs
  target/riscv: Implement AIA hvictl and hviprioX CSRs
  target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
  target/riscv: Implement AIA local interrupt priorities
  target/riscv: Allow AIA device emulation to set ireg rmw callback
  target/riscv: Add defines for AIA CSRs
  target/riscv: Add AIA cpu feature
  target/riscv: Allow setting CPU feature from machine/device emulation
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/e27c3627bb31...c13b8e997363
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