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[Qemu-commits] [qemu/qemu] 0da53b: include: hw: remove ibex_plic.h
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 0da53b: include: hw: remove ibex_plic.h |
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Date: |
Mon, 14 Feb 2022 13:53:57 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 0da53b462512adbd2156ccb2216fb7bc11c19bf5
https://github.com/qemu/qemu/commit/0da53b462512adbd2156ccb2216fb7bc11c19bf5
Author: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
R include/hw/intc/ibex_plic.h
Log Message:
-----------
include: hw: remove ibex_plic.h
This patch removes the left-over/unused `ibex_plic.h` file. Previously
used by opentitan, which now follows the RISC-V standard and uses the
SiFivePlicState.
Fixes: 434e7e021 ("hw/intc: Remove the Ibex PLIC")
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220121055005.3159846-1-alistair.francis@opensource.wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 31b35b42d633f9c0b9487bf9d28c176d3b7e683b
https://github.com/qemu/qemu/commit/31b35b42d633f9c0b9487bf9d28c176d3b7e683b
Author: Petr Tesarik <ptesarik@suse.com>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
M hw/core/generic-loader.c
Log Message:
-----------
Allow setting up to 8 bytes with the generic loader
The documentation for the generic loader says that "the maximum size of
the data is 8 bytes". However, attempts to set data-len=8 trigger the
following assertion failure:
../hw/core/generic-loader.c:59: generic_loader_reset: Assertion `s->data_len <
sizeof(s->data)' failed.
The type of s->data is uint64_t (i.e. 8 bytes long), so I believe this
assert should use <= instead of <.
Fixes: e481a1f63c93 ("generic-loader: Add a generic loader")
Signed-off-by: Petr Tesarik <ptesarik@suse.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120092715.7805-1-ptesarik@suse.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 40a35c2c2e60f9d16a6525b522baef81e66a7584
https://github.com/qemu/qemu/commit/40a35c2c2e60f9d16a6525b522baef81e66a7584
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/gdbstub.c
Log Message:
-----------
target/riscv: correct "code should not be reached" for x-rv128
The addition of uxl support in gdbstub adds a few checks on the maximum
register length, but omitted MXL_RV128, an experimental feature.
This patch makes rv128 react as rv64, as previously.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220124202456.420258-1-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 6efad3b498d2df697f209bacb42d2e3fd73f8b88
https://github.com/qemu/qemu/commit/6efad3b498d2df697f209bacb42d2e3fd73f8b88
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct
RISCVCPUConfig'
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220202005249.3566542-2-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: cea4c440d8a188f835f9855f670b74e3355c53b0
https://github.com/qemu/qemu/commit/cea4c440d8a188f835f9855f670b74e3355c53b0
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
M target/riscv/translate.c
Log Message:
-----------
target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr
As the number of extensions is growing, copying them individiually
into the DisasContext will scale less and less... instead we populate
a pointer to the RISCVCPUConfig structure in the DisasContext.
This adds an extra indirection when checking for the availability of
an extension (compared to copying the fields into DisasContext).
While not a performance problem today, we can always (shallow) copy
the entire structure into the DisasContext (instead of putting a
pointer to it) if this is ever deemed necessary.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220202005249.3566542-3-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9bae1b388ddb8421eb5dbd998bea175560304bc3
https://github.com/qemu/qemu/commit/9bae1b388ddb8421eb5dbd998bea175560304bc3
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/insn_trans/trans_rvzfh.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: access configuration through cfg_ptr in DisasContext
The implementation in trans_{rvi,rvv,rvzfh}.c.inc accesses the shallow
copies (in DisasContext) of some of the elements available in the
RISCVCPUConfig structure. This commit redirects accesses to use the
cfg_ptr copied into DisasContext and removes the shallow copies.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220202005249.3566542-4-philipp.tomsich@vrull.eu>
[ Changes by AF:
- Fixup checkpatch failures
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e7e65e13f4a2c0276d4350c4393b514bd7d1c21d
https://github.com/qemu/qemu/commit/e7e65e13f4a2c0276d4350c4393b514bd7d1c21d
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvb.c.inc
Log Message:
-----------
target/riscv: access cfg structure through DisasContext
The Zb[abcs] support code still uses the RISCV_CPU macros to access
the configuration information (i.e., check whether an extension is
available/enabled). Now that we provide this information directly
from DisasContext, we can access this directly via the cfg_ptr field.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220202005249.3566542-5-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e9037c20245f6f74cab84b6fc0e8db404c8fa685
https://github.com/qemu/qemu/commit/e9037c20245f6f74cab84b6fc0e8db404c8fa685
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
M target/riscv/translate.c
Log Message:
-----------
target/riscv: iterate over a table of decoders
To split up the decoder into multiple functions (both to support
vendor-specific opcodes in separate files and to simplify maintenance
of orthogonal extensions), this changes decode_op to iterate over a
table of decoders predicated on guard functions.
This commit only adds the new structure and the table, allowing for
the easy addition of additional decoders in the future.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220202005249.3566542-6-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1a76bc94ec2b8bfeb37826b4e697d643fe571f1c
https://github.com/qemu/qemu/commit/1a76bc94ec2b8bfeb37826b4e697d643fe571f1c
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
A target/riscv/XVentanaCondOps.decode
M target/riscv/cpu.c
M target/riscv/cpu.h
A target/riscv/insn_trans/trans_xventanacondops.c.inc
M target/riscv/meson.build
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Add XVentanaCondOps custom extension
This adds the decoder and translation for the XVentanaCondOps custom
extension (vendor-defined by Ventana Micro Systems), which is
documented at
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
This commit then also adds a guard-function (has_XVentanaCondOps_p)
and the decoder function to the table of decoders, enabling the
support for the XVentanaCondOps extension.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220202005249.3566542-7-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e47c9687edaa56a49883398ffc0c0bad5f2168ad
https://github.com/qemu/qemu/commit/e47c9687edaa56a49883398ffc0c0bad5f2168ad
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
M MAINTAINERS
Log Message:
-----------
target/riscv: add a MAINTAINERS entry for XVentanaCondOps
The XVentanaCondOps extension is supported by VRULL on behalf of the
Ventana Micro. Add myself as a point-of-contact.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220202005249.3566542-8-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 29f1c7b1b3f08e94a756ba13d0f32c006b617aae
https://github.com/qemu/qemu/commit/29f1c7b1b3f08e94a756ba13d0f32c006b617aae
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Fix vill field write in vtype
The guest should be able to set the vill bit as part of vsetvl.
Currently we may set env->vill to 1 in the vsetvl helper, but there
is nowhere that we set it to 0, so once it transitions to 1 it's stuck
there until the system is reset.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220201064601.41143-1-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c6042bb5239f87b669b0b1d2846bc42709e23307
https://github.com/qemu/qemu/commit/c6042bb5239f87b669b0b1d2846bc42709e23307
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
We should be returning illegal instruction trap when RV64 HS-mode tries
to access RV32 HS-mode CSR.
Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions")
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-2-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: be73331f92d9fc4b606258519761fb53ec23aa2c
https://github.com/qemu/qemu/commit/be73331f92d9fc4b606258519761fb53ec23aa2c
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_bits.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Implement SGEIP bit in hip and hie CSRs
A hypervisor can optionally take guest external interrupts using
SGEIP bit of hip and hie CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-3-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0256835e96044ba165bcf5ed2e3af29275155146
https://github.com/qemu/qemu/commit/0256835e96044ba165bcf5ed2e3af29275155146
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/machine.c
Log Message:
-----------
target/riscv: Implement hgeie and hgeip CSRs
The hgeie and hgeip CSRs are required for emulating an external
interrupt controller capable of injecting virtual external interrupt
to Guest/VM running at VS-level.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-4-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5adc58b2f84a5650418c3bd4afc4413f1d51a08f
https://github.com/qemu/qemu/commit/5adc58b2f84a5650418c3bd4afc4413f1d51a08f
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Improve delivery of guest external interrupts
The guest external interrupts from an interrupt controller are
delivered only when the Guest/VM is running (i.e. V=1). This means
any guest external interrupt which is triggered while the Guest/VM
is not running (i.e. V=0) will be missed on QEMU resulting in Guest
with sluggish response to serial console input and other I/O events.
To solve this, we check and inject interrupt after setting V=1.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-5-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fbc4da78e49bfd617ece7220ffe4ead6f240d6f0
https://github.com/qemu/qemu/commit/fbc4da78e49bfd617ece7220ffe4ead6f240d6f0
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: Allow setting CPU feature from machine/device emulation
The machine or device emulation should be able to force set certain
CPU features because:
1) We can have certain CPU features which are in-general optional
but implemented by RISC-V CPUs on the machine.
2) We can have devices which require a certain CPU feature. For example,
AIA IMSIC devices expect AIA CSRs implemented by RISC-V CPUs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-6-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c8bb4e22b342aca9d31d696e0d6e323ef17ec6e9
https://github.com/qemu/qemu/commit/c8bb4e22b342aca9d31d696e0d6e323ef17ec6e9
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: Add AIA cpu feature
We define a CPU feature for AIA CSR support in RISC-V CPUs which
can be set by machine/device emulation. The RISC-V CSR emulation
will also check this feature for emulating AIA CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-7-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f2ad253fce6facc5eed4d23e3b690c4bb144f4d8
https://github.com/qemu/qemu/commit/f2ad253fce6facc5eed4d23e3b690c4bb144f4d8
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
M target/riscv/cpu_bits.h
Log Message:
-----------
target/riscv: Add defines for AIA CSRs
The RISC-V AIA specification extends RISC-V local interrupts and
introduces new CSRs. This patch adds defines for the new AIA CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-8-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3f8fd7105d2b0e0abed57fe789790d489df7f3a2
https://github.com/qemu/qemu/commit/3f8fd7105d2b0e0abed57fe789790d489df7f3a2
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Allow AIA device emulation to set ireg rmw callback
The AIA device emulation (such as AIA IMSIC) should be able to set
(or provide) AIA ireg read-modify-write callback for each privilege
level of a RISC-V HART.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-9-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 53420c87565bb8e3fd2d6a24974fbfb5e181e165
https://github.com/qemu/qemu/commit/53420c87565bb8e3fd2d6a24974fbfb5e181e165
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/machine.c
Log Message:
-----------
target/riscv: Implement AIA local interrupt priorities
The AIA spec defines programmable 8-bit priority for each local interrupt
at M-level, S-level and VS-level so we extend local interrupt processing
to consider AIA interrupt priorities. The AIA CSRs which help software
configure local interrupt priorities will be added by subsequent patches.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220204174700.534953-10-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9c12636070ad4c5e64c5a265f2afe34aa07fc112
https://github.com/qemu/qemu/commit/9c12636070ad4c5e64c5a265f2afe34aa07fc112
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-10 (Thu, 10 Feb 2022)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/machine.c
Log Message:
-----------
target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
The AIA specification adds new CSRs for RV32 so that RISC-V hart can
support 64 local interrupts on both RV32 and RV64.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-11-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fecfef5e9ca1f72ba8db74cd19a600774c96fa8b
https://github.com/qemu/qemu/commit/fecfef5e9ca1f72ba8db74cd19a600774c96fa8b
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-11 (Fri, 11 Feb 2022)
Changed paths:
M target/riscv/cpu.h
M target/riscv/csr.c
M target/riscv/machine.c
Log Message:
-----------
target/riscv: Implement AIA hvictl and hviprioX CSRs
The AIA hvictl and hviprioX CSRs allow hypervisor to control
interrupts visible at VS-level. This patch implements AIA hvictl
and hviprioX CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-12-anup@brainfault.org
[ Changes by AF:
- Fix possible unintilised variable error in rmw_sie()
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: bbd481e174cacbb5b15d157686160129022aa5e3
https://github.com/qemu/qemu/commit/bbd481e174cacbb5b15d157686160129022aa5e3
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-11 (Fri, 11 Feb 2022)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Implement AIA interrupt filtering CSRs
The AIA specificaiton adds interrupt filtering support for M-mode
and HS-mode. Using AIA interrupt filtering M-mode and H-mode can
take local interrupt 13 or above and selectively inject same local
interrupt to lower privilege modes.
At the moment, we don't have any local interrupts above 12 so we
add dummy implementation (i.e. read zero and ignore write) of AIA
interrupt filtering CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-13-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 07ec93683a0e61c5b37a46258bf6cc04a54a9efe
https://github.com/qemu/qemu/commit/07ec93683a0e61c5b37a46258bf6cc04a54a9efe
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-11 (Fri, 11 Feb 2022)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
The AIA specification introduces new [m|s|vs]topi CSRs for
reporting pending local IRQ number and associated IRQ priority.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-14-anup@brainfault.org
[ Changed by AF:
- Fixup indentation
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 193012766e98935c9748e9d4078a8b23a332c39e
https://github.com/qemu/qemu/commit/193012766e98935c9748e9d4078a8b23a332c39e
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-11 (Fri, 11 Feb 2022)
Changed paths:
M target/riscv/cpu.h
M target/riscv/csr.c
M target/riscv/machine.c
Log Message:
-----------
target/riscv: Implement AIA xiselect and xireg CSRs
The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
which allow indirect access to interrupt priority arrays and per-HART
IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-15-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3cf16712b3d674b661b67219d7bf40162e697d77
https://github.com/qemu/qemu/commit/3cf16712b3d674b661b67219d7bf40162e697d77
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-11 (Fri, 11 Feb 2022)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Implement AIA IMSIC interface CSRs
The AIA specification defines IMSIC interface CSRs for easy access
to the per-HART IMSIC registers without using indirect xiselect and
xireg CSRs. This patch implements the AIA IMSIC interface CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-16-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 38d9211b363f7713cfeac8ce4bb4cdb7a482e65c
https://github.com/qemu/qemu/commit/38d9211b363f7713cfeac8ce4bb4cdb7a482e65c
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-11 (Fri, 11 Feb 2022)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: virt: Use AIA INTC compatible string when available
We should use the AIA INTC compatible string in the CPU INTC
DT nodes when the CPUs support AIA feature. This will allow
Linux INTC driver to use AIA local interrupt CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-17-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 76e83965794e91291a784574d4ec643aa423ddbf
https://github.com/qemu/qemu/commit/76e83965794e91291a784574d4ec643aa423ddbf
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-11 (Fri, 11 Feb 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: Allow users to force enable AIA CSRs in HART
We add "x-aia" command-line option for RISC-V HART using which
allows users to force enable CPU AIA CSRs without changing the
interrupt controller available in RISC-V machine.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-18-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f1849f18d27692e6b4490e1cb0a9733295424ae5
https://github.com/qemu/qemu/commit/f1849f18d27692e6b4490e1cb0a9733295424ae5
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-11 (Fri, 11 Feb 2022)
Changed paths:
M hw/intc/Kconfig
M hw/intc/meson.build
A hw/intc/riscv_aplic.c
A include/hw/intc/riscv_aplic.h
Log Message:
-----------
hw/intc: Add RISC-V AIA APLIC device emulation
The RISC-V AIA (Advanced Interrupt Architecture) defines a new
interrupt controller for wired interrupts called APLIC (Advanced
Platform Level Interrupt Controller). The APLIC is capabable of
forwarding wired interupts to RISC-V HARTs directly or as MSIs
(Message Signaled Interupts).
This patch adds device emulation for RISC-V AIA APLIC.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-19-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e7a9e27681a857054fb6411d8a985816c693132d
https://github.com/qemu/qemu/commit/e7a9e27681a857054fb6411d8a985816c693132d
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-11 (Fri, 11 Feb 2022)
Changed paths:
M hw/riscv/Kconfig
M hw/riscv/virt.c
M include/hw/riscv/virt.h
Log Message:
-----------
hw/riscv: virt: Add optional AIA APLIC support to virt machine
We extend virt machine to emulate AIA APLIC devices only when
"aia=aplic" parameter is passed along with machine name in QEMU
command-line. When "aia=none" or not specified then we fallback
to original PLIC device emulation.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220204174700.534953-20-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1479398dabbe40367872ebf7530660db95e91567
https://github.com/qemu/qemu/commit/1479398dabbe40367872ebf7530660db95e91567
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-11 (Fri, 11 Feb 2022)
Changed paths:
M hw/intc/Kconfig
M hw/intc/meson.build
A hw/intc/riscv_imsic.c
A include/hw/intc/riscv_imsic.h
Log Message:
-----------
hw/intc: Add RISC-V AIA IMSIC device emulation
The RISC-V AIA (Advanced Interrupt Architecture) defines a new
interrupt controller for MSIs (message signal interrupts) called
IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC
is per-HART device and also suppport virtualizaiton of MSIs using
dedicated VS-level guest interrupt files.
This patch adds device emulation for RISC-V AIA IMSIC which
supports M-level, S-level, and VS-level MSIs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-21-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c39faae1a8bef057b044293c834be62ecb5de7c4
https://github.com/qemu/qemu/commit/c39faae1a8bef057b044293c834be62ecb5de7c4
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-11 (Fri, 11 Feb 2022)
Changed paths:
M hw/riscv/Kconfig
M hw/riscv/virt.c
M include/hw/riscv/virt.h
Log Message:
-----------
hw/riscv: virt: Add optional AIA IMSIC support to virt machine
We extend virt machine to emulate both AIA IMSIC and AIA APLIC
devices only when "aia=aplic-imsic" parameter is passed along
with machine name in the QEMU command-line. The AIA IMSIC is
only a per-HART MSI controller so we use AIA APLIC in MSI-mode
to forward all wired interrupts as MSIs to the AIA IMSIC.
We also provide "aia-guests=<xyz>" parameter which can be used
to specify number of VS-level AIA IMSIC Guests MMIO pages for
each HART.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220204174700.534953-22-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1cf7df027728c31a5b7117047c54d16b7015b2f2
https://github.com/qemu/qemu/commit/1cf7df027728c31a5b7117047c54d16b7015b2f2
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-11 (Fri, 11 Feb 2022)
Changed paths:
M docs/system/riscv/virt.rst
Log Message:
-----------
docs/system: riscv: Document AIA options for virt machine
We have two new machine options "aia" and "aia-guests" available
for the RISC-V virt machine so let's document these options.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-23-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8ea362b80743c4b5efd416fc8fc7fde312a3b342
https://github.com/qemu/qemu/commit/8ea362b80743c4b5efd416fc8fc7fde312a3b342
Author: Anup Patel <anup.patel@wdc.com>
Date: 2022-02-11 (Fri, 11 Feb 2022)
Changed paths:
M hw/riscv/virt.c
M include/hw/riscv/virt.h
Log Message:
-----------
hw/riscv: virt: Increase maximum number of allowed CPUs
To facilitate software development of RISC-V systems with large number
of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).
We also add a detailed source level comments about limit defines which
impact the physical address space utilization.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-24-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 882035d71a3efe30d6beb98dbffea8385cb09933
https://github.com/qemu/qemu/commit/882035d71a3efe30d6beb98dbffea8385cb09933
Author: Guo Ren <ren_guo@c-sky.com>
Date: 2022-02-11 (Fri, 11 Feb 2022)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Ignore reserved bits in PTE for RV64
Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
need to ignore them. They cannot be a part of ppn.
1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
4.4 Sv39: Page-Based 39-bit Virtual-Memory System
4.5 Sv48: Page-Based 48-bit Virtual-Memory System
2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8fcfe170b1fb686d28442ec462ac34c4f297b4b2
https://github.com/qemu/qemu/commit/8fcfe170b1fb686d28442ec462ac34c4f297b4b2
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-02-11 (Fri, 11 Feb 2022)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
For non-leaf PTEs, the D, A, and U bits are reserved for future standard use.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 01fca9e8c56a6bae8aef8c847efc9fe0b8aaedb0
https://github.com/qemu/qemu/commit/01fca9e8c56a6bae8aef8c847efc9fe0b8aaedb0
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-02-11 (Fri, 11 Feb 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: add support for svnapot extension
- add PTE_N bit
- add PTE_N bit check for inner PTE
- update address translation to support 64KiB continuous region (napot_bits = 4)
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 6b7c1fd2721954008c914073ae70311133891b15
https://github.com/qemu/qemu/commit/6b7c1fd2721954008c914073ae70311133891b15
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-02-11 (Fri, 11 Feb 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/insn32.decode
A target/riscv/insn_trans/trans_svinval.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: add support for svinval extension
- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma,
hfence.vvma and hfence.gvma except extension check
- do nothing other than extension check for sfence.w.inval and sfence.inval.ir
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 828ecdd075797210dd9381739b8538146184dd90
https://github.com/qemu/qemu/commit/828ecdd075797210dd9381739b8538146184dd90
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2022-02-11 (Fri, 11 Feb 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: add support for svpbmt extension
- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU,
since QEMU is sequentially consistent and doesn't model PMAs currently
- add PTE_PBMT bit check for inner PTE
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 31d69b66ed89fa0f66d4e5a15e9664c92c3ed8f8
https://github.com/qemu/qemu/commit/31d69b66ed89fa0f66d4e5a15e9664c92c3ed8f8
Author: Yu Li <liyu.yukiteru@bytedance.com>
Date: 2022-02-11 (Fri, 11 Feb 2022)
Changed paths:
M docs/system/riscv/virt.rst
Log Message:
-----------
docs/system: riscv: Update description of CPU
Since the hypervisor extension been non experimental and enabled for
default CPU, the previous command is no longer available and the
option `x-h=true` or `h=true` is also no longer required.
Signed-off-by: Yu Li <liyu.yukiteru@bytedance.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <9040401e-8f87-ef4a-d840-6703f08d068c@bytedance.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1bb1e5df91c8e9161f38fc31adfd21b48fc1417e
https://github.com/qemu/qemu/commit/1bb1e5df91c8e9161f38fc31adfd21b48fc1417e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-02-14 (Mon, 14 Feb 2022)
Changed paths:
M MAINTAINERS
M docs/system/riscv/virt.rst
M hw/core/generic-loader.c
M hw/intc/Kconfig
M hw/intc/meson.build
A hw/intc/riscv_aplic.c
A hw/intc/riscv_imsic.c
M hw/riscv/Kconfig
M hw/riscv/virt.c
R include/hw/intc/ibex_plic.h
A include/hw/intc/riscv_aplic.h
A include/hw/intc/riscv_imsic.h
M include/hw/riscv/virt.h
A target/riscv/XVentanaCondOps.decode
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/gdbstub.c
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/insn_trans/trans_rvzfh.c.inc
A target/riscv/insn_trans/trans_svinval.c.inc
A target/riscv/insn_trans/trans_xventanacondops.c.inc
M target/riscv/machine.c
M target/riscv/meson.build
M target/riscv/translate.c
M target/riscv/vector_helper.c
Log Message:
-----------
Merge remote-tracking branch
'remotes/alistair/tags/pull-riscv-to-apply-20220212' into staging
Fourth RISC-V PR for QEMU 7.0
* Remove old Ibex PLIC header file
* Allow writing 8 bytes with generic loader
* Fixes for RV128
* Refactor RISC-V CPU configs
* Initial support for XVentanaCondOps custom extension
* Fix for vill field in vtype
* Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
* RISC-V AIA support for virt machine
* Support for svnapot, svinval and svpbmt extensions
# gpg: Signature made Fri 11 Feb 2022 23:59:41 GMT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20220212: (40 commits)
docs/system: riscv: Update description of CPU
target/riscv: add support for svpbmt extension
target/riscv: add support for svinval extension
target/riscv: add support for svnapot extension
target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
target/riscv: Ignore reserved bits in PTE for RV64
hw/riscv: virt: Increase maximum number of allowed CPUs
docs/system: riscv: Document AIA options for virt machine
hw/riscv: virt: Add optional AIA IMSIC support to virt machine
hw/intc: Add RISC-V AIA IMSIC device emulation
hw/riscv: virt: Add optional AIA APLIC support to virt machine
hw/intc: Add RISC-V AIA APLIC device emulation
target/riscv: Allow users to force enable AIA CSRs in HART
hw/riscv: virt: Use AIA INTC compatible string when available
target/riscv: Implement AIA IMSIC interface CSRs
target/riscv: Implement AIA xiselect and xireg CSRs
target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
target/riscv: Implement AIA interrupt filtering CSRs
target/riscv: Implement AIA hvictl and hviprioX CSRs
target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/2d88a3a595f1...1bb1e5df91c8
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