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[Qemu-commits] [qemu/qemu] 84f54d: target/ppc: Remove 440x4 CPU
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 84f54d: target/ppc: Remove 440x4 CPU |
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Date: |
Mon, 14 Feb 2022 07:23:54 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 84f54da51349132e59999487cbce79433a5a0e10
https://github.com/qemu/qemu/commit/84f54da51349132e59999487cbce79433a5a0e10
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Remove 440x4 CPU
This CPU was partially removed due to lack of support in 2017 by commit
aef7796057 ("ppc: remove non implemented cpu models").
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220128221611.1221715-1-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 180952cedc0eef37ac43f9de66bdc0ebd43e2ed8
https://github.com/qemu/qemu/commit/180952cedc0eef37ac43f9de66bdc0ebd43e2ed8
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Introduce powerpc_excp_booke
Introduce a new powerpc_excp function specific for BookE CPUs. This
commit copies powerpc_excp_legacy verbatim so the next one has a clean
diff.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220128224018.1228062-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9dc20cc37db9d13ccce00e7274f22d41f5306443
https://github.com/qemu/qemu/commit/9dc20cc37db9d13ccce00e7274f22d41f5306443
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Simplify powerpc_excp_booke
Differences from the generic powerpc_excp code:
- No MSR bits are cleared at interrupt dispatch;
- No MSR_HV;
- No power saving states;
- No Hypervisor Emulation Assistance;
- SPEU needs special handling;
- Big endian only;
- Both 64 and 32 bits;
- No System call vectored;
- No Alternate Interrupt Location.
Exceptions used:
POWERPC_EXCP_ALIGN
POWERPC_EXCP_APU
POWERPC_EXCP_CRITICAL
POWERPC_EXCP_DEBUG
POWERPC_EXCP_DECR
POWERPC_EXCP_DSI
POWERPC_EXCP_DTLB
POWERPC_EXCP_EFPDI
POWERPC_EXCP_EFPRI
POWERPC_EXCP_EXTERNAL
POWERPC_EXCP_FIT
POWERPC_EXCP_FPU
POWERPC_EXCP_ISI
POWERPC_EXCP_ITLB
POWERPC_EXCP_MCHECK
POWERPC_EXCP_PROGRAM
POWERPC_EXCP_RESET
POWERPC_EXCP_SPEU
POWERPC_EXCP_SYSCALL
POWERPC_EXCP_WDT
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220128224018.1228062-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9c9b67fe91a0e5ff3961d85d7d51dce4075a6f08
https://github.com/qemu/qemu/commit/9c9b67fe91a0e5ff3961d85d7d51dce4075a6f08
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: booke: Critical exception cleanup
Remove 40x and G2 code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220128224018.1228062-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: db403211f8048c08cc948de8882c1a8c99f021dd
https://github.com/qemu/qemu/commit/db403211f8048c08cc948de8882c1a8c99f021dd
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: booke: Machine Check cleanups
There's no MSR_HV in BookE.
Also remove 40x code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220128224018.1228062-5-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: afdbc869412637190a7d1e11c1b830ceebb6ffda
https://github.com/qemu/qemu/commit/afdbc869412637190a7d1e11c1b830ceebb6ffda
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: booke: Data Storage exception cleanup
There is no DSISR or DAR in BookE. Change to ESR and DEAR.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220128224018.1228062-6-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: b583351d4b149980c07d7f7c26acc937d514783d
https://github.com/qemu/qemu/commit/b583351d4b149980c07d7f7c26acc937d514783d
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: booke: Instruction storage exception cleanup
The SRR1 should be set to the MSR value. There are no diagnostic bits
in the SRR1 for BookE.
Note that this fixes a bug where MSR_GS would be set and Linux would
go into KVM code when there's no KVM guest.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220128224018.1228062-7-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 5d54e8c18e56568fc52143dab0316e18015af185
https://github.com/qemu/qemu/commit/5d54e8c18e56568fc52143dab0316e18015af185
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: booke: External interrupt cleanup
There is no LPES0 in BookE and no MSR_HV.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220128224018.1228062-8-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f7a28f711939fe873dee762aa7dfe9f4bb63be06
https://github.com/qemu/qemu/commit/f7a28f711939fe873dee762aa7dfe9f4bb63be06
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: booke: Alignment interrupt cleanup
BookE has no DSISR or DAR. The proper registers ESR and DEAR were
already set at this point.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220128224018.1228062-9-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 904e842865f01cb1cb16ace5ecf49233c4612ec7
https://github.com/qemu/qemu/commit/904e842865f01cb1cb16ace5ecf49233c4612ec7
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: booke: System Call exception cleanup
QEMU does not support BookE as a hypervisor.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220128224018.1228062-10-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f2ba48779c626389eba828890f7c0979744ea305
https://github.com/qemu/qemu/commit/f2ba48779c626389eba828890f7c0979744ea305
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: booke: Watchdog Timer interrupt
Remove the switch as this function applies to BookE only.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220128224018.1228062-11-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 0fdd000a41ea57526d03b46301318f881abddc92
https://github.com/qemu/qemu/commit/0fdd000a41ea57526d03b46301318f881abddc92
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: booke: System Reset exception cleanup
There is no MSR_HV in BookE, so remove all of the HV logic.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220128224018.1228062-12-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 36387ca51c72407ec9f0f047767fcf3c6380b7de
https://github.com/qemu/qemu/commit/36387ca51c72407ec9f0f047767fcf3c6380b7de
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/mmu-radix64.c
Log Message:
-----------
target/ppc: Fix radix logging
ppc_radix64_partition_scoped_xlate() logs the host page protection
bits variable but it is uninitialized. The value is set later on in
ppc_radix64_check_prot(). Remove the output.
Fixes: Coverity CID 1468942
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Message-Id: <20220203142145.1301749-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 005b69fdccd798dd8f0996d0f1c93ff5a4672180
https://github.com/qemu/qemu/commit/005b69fdccd798dd8f0996d0f1c93ff5a4672180
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M hw/ppc/ppc.c
M hw/ppc/prep.c
M linux-user/ppc/cpu_loop.c
M target/ppc/cpu-models.c
M target/ppc/cpu-models.h
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/helper.h
M target/ppc/helper_regs.c
M target/ppc/int_helper.c
M target/ppc/machine.c
M target/ppc/misc_helper.c
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash32.h
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
M target/ppc/spr_tcg.h
M target/ppc/timebase_helper.c
M target/ppc/translate.c
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Remove PowerPC 601 CPUs
The PowerPC 601 processor is the first generation of processors to
implement the PowerPC architecture. It was designed as a bridge
processor and also could execute most of the instructions of the
previous POWER architecture. It was found on the first Macs and IBM
RS/6000 workstations.
There is not much interest in keeping the CPU model of this
POWER-PowerPC bridge processor. We have the 603 and 604 CPU models of
the 60x family which implement the complete PowerPC instruction set.
Cc: "Hervé Poussineau" <hpoussin@reactos.org>
Cc: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203142756.1302515-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9323650f973272c065ea28c8f2864cc30aecc665
https://github.com/qemu/qemu/commit/9323650f973272c065ea28c8f2864cc30aecc665
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Merge exception model IDs for 6xx CPUs
We don't need three separate exception model IDs for the 603, 604 and
G2.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 58d178fb8bb3177777dbc6f1c7946ec4b84b8da6
https://github.com/qemu/qemu/commit/58d178fb8bb3177777dbc6f1c7946ec4b84b8da6
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Introduce powerpc_excp_6xx
Introduce a new powerpc_excp function specific for PowerPC 6xx CPUs
(603, 604, G2, MPC5xx, MCP8xx). This commit copies powerpc_excp_legacy
verbatim so the next one has a clean diff.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 082d783bf02eaafa4610fbdd9fe8b1749bcf0e2d
https://github.com/qemu/qemu/commit/082d783bf02eaafa4610fbdd9fe8b1749bcf0e2d
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Simplify powerpc_excp_6xx
Differences from the generic powerpc_excp code:
- Not BookE, so some MSR bits are cleared at interrupt dispatch;
- No MSR_HV;
- No power saving states;
- No Hypervisor Emulation Assistance;
- Not 64 bits;
- No System call vectored;
- No Alternate Interrupt Location.
Exceptions used:
POWERPC_EXCP_ALIGN
POWERPC_EXCP_CRITICAL
POWERPC_EXCP_DABR
POWERPC_EXCP_DECR
POWERPC_EXCP_DLTLB
POWERPC_EXCP_DSI
POWERPC_EXCP_DSTLB
POWERPC_EXCP_DTLB
POWERPC_EXCP_EXTERNAL
POWERPC_EXCP_FPA
POWERPC_EXCP_FPU
POWERPC_EXCP_IABR
POWERPC_EXCP_IFTLB
POWERPC_EXCP_ISI
POWERPC_EXCP_ITLB
POWERPC_EXCP_MCHECK
POWERPC_EXCP_MEXTBR
POWERPC_EXCP_NMEXTBR
POWERPC_EXCP_PROGRAM
POWERPC_EXCP_RESET
POWERPC_EXCP_SMI
POWERPC_EXCP_SYSCALL
POWERPC_EXCP_TRACE
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: b7c32cdd9a7cd226fa41d49c4503b8f15c74cf7f
https://github.com/qemu/qemu/commit/b7c32cdd9a7cd226fa41d49c4503b8f15c74cf7f
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 6xx: Critical exception cleanup
This only applies to the G2s, the other 6xx CPUs will not have this
vector registered.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-5-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9b12ff43d428805d79315521ff2d242e67bb47ce
https://github.com/qemu/qemu/commit/9b12ff43d428805d79315521ff2d242e67bb47ce
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 6xx: Machine Check exception cleanup
There's no MSR_HV in the 6xx CPUs.
Also remove the 40x and BookE code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-6-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 3189fa391702314b84edbf0edbf25a5c08ccad9e
https://github.com/qemu/qemu/commit/3189fa391702314b84edbf0edbf25a5c08ccad9e
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 6xx: External interrupt cleanup
There's no Hypervisor mode in the 6xx, so remove all LPES0 logic.
Also remove BookE IRQ code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-7-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 25fe5f7534ee9dce6c2f038b1bd118e5d2eb5354
https://github.com/qemu/qemu/commit/25fe5f7534ee9dce6c2f038b1bd118e5d2eb5354
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 6xx: Program exception cleanup
There's no ESR in the 6xx CPUs.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-8-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c0e1928de5ff1152c4dafe36caf334e6fa10aad4
https://github.com/qemu/qemu/commit/c0e1928de5ff1152c4dafe36caf334e6fa10aad4
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 6xx: System Call exception cleanup
There is no Hypervisor mode in the 6xx CPUs.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-9-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 000ac49ad22be56e8ab21550e90e997b9ee39575
https://github.com/qemu/qemu/commit/000ac49ad22be56e8ab21550e90e997b9ee39575
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 6xx: System Reset interrupt cleanup
There is no HV support in the 6xx.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-10-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 8f8c7932d4be3fe4dc0fb9540c48132de7382cab
https://github.com/qemu/qemu/commit/8f8c7932d4be3fe4dc0fb9540c48132de7382cab
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 6xx: Software TLB exceptions cleanup
This code applies only to the 6xx CPUs, so we can remove the switch
statement.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-11-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c50eaed135216597cd75f71cec79ae28a7996c06
https://github.com/qemu/qemu/commit/c50eaed135216597cd75f71cec79ae28a7996c06
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 6xx: Set SRRs directly in exception code
The 6xx CPUs don't have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220203200957.1434641-12-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: fd7dc4bb7869e367f5b9c6934abbb13aa04a21f6
https://github.com/qemu/qemu/commit/fd7dc4bb7869e367f5b9c6934abbb13aa04a21f6
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Merge 7x5 and 7x0 exception model IDs
Since we've split the exception code by exception model, the exception
model IDs are becoming less useful. These two can be merged.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ccfca2fca5ef30078a3b8ed011556b55a098de8c
https://github.com/qemu/qemu/commit/ccfca2fca5ef30078a3b8ed011556b55a098de8c
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Introduce powerpc_excp_7xx
Introduce a new powerpc_excp function specific for PowerPC 7xx CPUs
(740, 745, 750, 750cl, 750cx, 750fx, 750gx, 755). This commit copies
powerpc_excp_legacy verbatim so the next one has a clean diff.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 93848d6a4c2f7f65553ec4583ed1f3fed621eecc
https://github.com/qemu/qemu/commit/93848d6a4c2f7f65553ec4583ed1f3fed621eecc
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Simplify powerpc_excp_7xx
Differences from the generic powerpc_excp code:
- Not BookE, so some MSR bits are cleared at interrupt dispatch;
- No MSR_HV;
- No power saving states;
- No Hypervisor Emulation Assistance;
- Not 64 bits;
- No System call vectored;
- No Alternate Interrupt Location.
Exceptions used:
POWERPC_EXCP_ALIGN
POWERPC_EXCP_DECR
POWERPC_EXCP_DLTLB
POWERPC_EXCP_DSI
POWERPC_EXCP_DSTLB
POWERPC_EXCP_EXTERNAL
POWERPC_EXCP_FPU
POWERPC_EXCP_IABR
POWERPC_EXCP_IFTLB
POWERPC_EXCP_ISI
POWERPC_EXCP_MCHECK
POWERPC_EXCP_PERFM
POWERPC_EXCP_PROGRAM
POWERPC_EXCP_RESET
POWERPC_EXCP_SMI
POWERPC_EXCP_SYSCALL
POWERPC_EXCP_THERM
POWERPC_EXCP_TRACE
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 784f5a3403097a4427c91e7f62d257a3dbbf751e
https://github.com/qemu/qemu/commit/784f5a3403097a4427c91e7f62d257a3dbbf751e
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 7xx: Machine Check exception cleanup
There's no MSR_HV in the 7xx.
Also remove 40x and BookE code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-5-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a53ce46537f7d6a8541ab91154a151f13601f102
https://github.com/qemu/qemu/commit/a53ce46537f7d6a8541ab91154a151f13601f102
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 7xx: External interrupt cleanup
There is no MSR_HV in the 7xx so remove the LPES0 handling.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-6-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ab369390337d22d867f863cd368e8cf8b4c9fdde
https://github.com/qemu/qemu/commit/ab369390337d22d867f863cd368e8cf8b4c9fdde
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 7xx: Program exception cleanup
There's no ESR in the 7xx.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-7-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 3b57863593864ef35215ef7e210f06f4cabd73ed
https://github.com/qemu/qemu/commit/3b57863593864ef35215ef7e210f06f4cabd73ed
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 7xx: System Call exception cleanup
Remove the BookE code and add a comment explaining why we need to keep
hypercall support even though this CPU does not have a hypervisor
mode.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-8-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 3c3fa438f6c008e536c809c20530b423ff877b2f
https://github.com/qemu/qemu/commit/3c3fa438f6c008e536c809c20530b423ff877b2f
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 7xx: System Reset cleanup
Thre is no HV support in the 7xx.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-9-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 7df40c5414b2f5e213fa30005f1600a429660cc5
https://github.com/qemu/qemu/commit/7df40c5414b2f5e213fa30005f1600a429660cc5
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 7xx: Software TLB cleanup
This code applies only to the 7xx CPUs, so we can remove the switch
statement.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-10-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: fe4b5c4c335c874ab05f3bdf40f2b62641d81c72
https://github.com/qemu/qemu/commit/fe4b5c4c335c874ab05f3bdf40f2b62641d81c72
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 7xx: Set SRRs directly in exception code
The 7xx CPUs don't have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-11-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2809137443030d89a0467e0c24db023c0951702a
https://github.com/qemu/qemu/commit/2809137443030d89a0467e0c24db023c0951702a
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Remove powerpc_excp_legacy
Now that all CPU families have their own separate exception
dispatching code we can remove powerpc_excp_legacy.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220207183036.1507882-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c6eaac893af2baef30d3fcce790cbd89fee82a42
https://github.com/qemu/qemu/commit/c6eaac893af2baef30d3fcce790cbd89fee82a42
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: powerpc_excp: Move common code to the caller function
Make the cpu-specific powerpc_excp_* functions a bit simpler by moving
the bounds check and logging to powerpc_excp.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220207183036.1507882-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: fce9fbafe910822be093abfbf5fa259d5931aa66
https://github.com/qemu/qemu/commit/fce9fbafe910822be093abfbf5fa259d5931aa66
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Assert if MSR bits differ from msr_mask during exceptions
We currently abort QEMU during the dispatch of an interrupt if we try
to set MSR_HV without having MSR_HVB in the msr_mask. I think we
should verify this for all MSR bits. There is no reason to ever have a
MSR bit set if the corresponding bit is not set in that CPU's
msr_mask.
Note that this is not about the emulated code setting reserved
bits. We clear the new_msr when starting to dispatch an exception, so
if we end up with bits not present in the msr_mask that is a QEMU
programming error.
I kept the HSRR verification for BookS because it is the only CPU
family that has HSRRs.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220207183036.1507882-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 10895ab6f76beaf2d2b5b450167c5d5102c8c3af
https://github.com/qemu/qemu/commit/10895ab6f76beaf2d2b5b450167c5d5102c8c3af
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: books: Remove excp_model argument from ppc_excp_apply_ail
We don't really need to check for exception model while applying
AIL. We can check the lpcr_mask for the presence of
LPCR_AIL/LPCR_HAIL.
This removes one more instance of passing the exception model ID
around.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220207183036.1507882-5-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 205eb5a89e06f790831b7f6903c92e0dc78b6805
https://github.com/qemu/qemu/commit/205eb5a89e06f790831b7f6903c92e0dc78b6805
Author: Víctor Colombo <victor.colombo@eldorado.org.br>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: Change VSX instructions behavior to fill with zeros
ISA v3.1 changed some VSX instructions behavior by changing what the
other words/doubleword in the result should contain when the result is
only one word/doubleword. e.g. xsmaxdp operates on doubleword 0 and
saves the result also in doubleword 0.
Before, the second doubleword result was undefined according to the
ISA, but now it's stated that it should be zeroed.
Even tough the result was undefined before, hardware implementing these
instructions already filled these fields with 0s. Changing every ISA
version in QEMU to this behavior makes the results match what happens
in hardware.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220204181944.65063-1-victor.colombo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 96a46def58b3b7938d200fca6bd4916c3640d2f3
https://github.com/qemu/qemu/commit/96a46def58b3b7938d200fca6bd4916c3640d2f3
Author: Cornelia Huck <cohuck@redhat.com>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M MAINTAINERS
R docs/amd-memory-encryption.txt
R docs/confidential-guest-support.txt
A docs/system/confidential-guest-support.rst
A docs/system/i386/amd-memory-encryption.rst
M docs/system/index.rst
M docs/system/ppc/pseries.rst
M docs/system/target-i386.rst
Log Message:
-----------
docs: rstfy confidential guest documentation
Also rstfy the documentation for AMD SEV, and link it.
The documentation for PEF had been merged into the pseries doc,
fix the reference.
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220204161251.241877-1-cohuck@redhat.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 10717c26dbe1c138ba6af6d09a3bb9958d4fe3f2
https://github.com/qemu/qemu/commit/10717c26dbe1c138ba6af6d09a3bb9958d4fe3f2
Author: Alexey Kardashevskiy <aik@ozlabs.ru>
Date: 2022-02-09 (Wed, 09 Feb 2022)
Changed paths:
M pc-bios/meson.build
Log Message:
-----------
spapr/vof: Install rom and nvram binaries
This installs VOF-related binaries (the firmware and the preformatted
NVRAM) as those were left out when the VOF was submitted initially.
Fixes: fc8c745d5015 ("spapr: Implement Open Firmware client interface")
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Message-Id: <20220208103751.1587902-1-aik@ozlabs.ru>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: cc5ce8b8b6be83e5fe3b668dbd061ad97c534e3f
https://github.com/qemu/qemu/commit/cc5ce8b8b6be83e5fe3b668dbd061ad97c534e3f
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-02-13 (Sun, 13 Feb 2022)
Changed paths:
M MAINTAINERS
R docs/amd-memory-encryption.txt
R docs/confidential-guest-support.txt
A docs/system/confidential-guest-support.rst
A docs/system/i386/amd-memory-encryption.rst
M docs/system/index.rst
M docs/system/ppc/pseries.rst
M docs/system/target-i386.rst
M hw/ppc/ppc.c
M hw/ppc/prep.c
M linux-user/ppc/cpu_loop.c
M pc-bios/meson.build
M target/ppc/cpu-models.c
M target/ppc/cpu-models.h
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/helper_regs.c
M target/ppc/int_helper.c
M target/ppc/machine.c
M target/ppc/misc_helper.c
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash32.h
M target/ppc/mmu-radix64.c
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
M target/ppc/spr_tcg.h
M target/ppc/timebase_helper.c
M target/ppc/translate.c
M target/ppc/translate/fp-impl.c.inc
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220210' into
staging
ppc-7.0 queue
* Exception model rework (Fabiano)
* Unused CPU models removal (Fabiano and Cédric)
* Fix for VOF installation (Alexey)
* Misc fixes
# gpg: Signature made Thu 10 Feb 2022 12:59:07 GMT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* remotes/legoater/tags/pull-ppc-20220210: (42 commits)
spapr/vof: Install rom and nvram binaries
docs: rstfy confidential guest documentation
target/ppc: Change VSX instructions behavior to fill with zeros
target/ppc: books: Remove excp_model argument from ppc_excp_apply_ail
target/ppc: Assert if MSR bits differ from msr_mask during exceptions
target/ppc: powerpc_excp: Move common code to the caller function
target/ppc: Remove powerpc_excp_legacy
target/ppc: 7xx: Set SRRs directly in exception code
target/ppc: 7xx: Software TLB cleanup
target/ppc: 7xx: System Reset cleanup
target/ppc: 7xx: System Call exception cleanup
target/ppc: 7xx: Program exception cleanup
target/ppc: 7xx: External interrupt cleanup
target/ppc: 7xx: Machine Check exception cleanup
target/ppc: Simplify powerpc_excp_7xx
target/ppc: Introduce powerpc_excp_7xx
target/ppc: Merge 7x5 and 7x0 exception model IDs
target/ppc: 6xx: Set SRRs directly in exception code
target/ppc: 6xx: Software TLB exceptions cleanup
target/ppc: 6xx: System Reset interrupt cleanup
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/48033ad678ae...cc5ce8b8b6be