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[Qemu-commits] [qemu/qemu] 6e3f09: spapr: Force 32bit when resetting a c
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 6e3f09: spapr: Force 32bit when resetting a core |
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Date: |
Mon, 31 Jan 2022 11:02:49 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 6e3f09c28a2e1767dddaf08b2f1414cd57c6c909
https://github.com/qemu/qemu/commit/6e3f09c28a2e1767dddaf08b2f1414cd57c6c909
Author: Alexey Kardashevskiy <aik@ozlabs.ru>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_vof.c
Log Message:
-----------
spapr: Force 32bit when resetting a core
"PowerPC Processor binding to IEEE 1275" says in
"8.2.1. Initial Register Values" that the initial state is defined as
32bit so do it for both SLOF and VOF.
This should not cause behavioral change as SLOF switches to 64bit very
early anyway. As nothing enforces LE anywhere, this drops it for VOF.
The goal is to make VOF work with TCG as otherwise it barfs with
qemu: fatal: TCG hflags mismatch (current:0x6c000004 rebuilt:0x6c000000)
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220107072423.2278113-1-aik@ozlabs.ru>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 5aad0457eceec0085a289dde72e73f15db556b99
https://github.com/qemu/qemu/commit/5aad0457eceec0085a289dde72e73f15db556b99
Author: Christophe Leroy <christophe.leroy@csgroup.eu>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 603: fix restore of GPRs 0-3 on rfi
After a TLB miss exception, GPRs 0-3 must be restored on rfi.
This is managed by hreg_store_msr() which is called by do_rfi()
However, hreg_store_msr() does it if MSR[TGPR] is unset in the
passed MSR value.
The problem is that do_rfi() is given the content of SRR1 as
the value to be set in MSR, but TGPR bit is not part of SRR1
and that bit is used for something else and is sometimes set
to 1, leading to hreg_store_msr() not restoring GPRs.
So, do the same way as for POW bit, force clearing it.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Cc: Cedric Le Goater <clg@kaod.org>
Cc: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220120103824.239573-1-christophe.leroy@csgroup.eu>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: e31ea5d89b613072e64b83f67e9763e9b149b87e
https://github.com/qemu/qemu/commit/e31ea5d89b613072e64b83f67e9763e9b149b87e
Author: Vitaly Cheptsov <cheptsov@ispras.ru>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common: Fix SRR1/MSR error code on Book-E
Book-E architecture does not set the error code in 31:27 bits
of SRR1, but instead uses these bits for custom fields such
as GS (Guest Supervisor).
Wrongly setting these fields will result in QEMU crashes
when attempting to execute not executable code due to the attempts
to use Guest Supervisor mode.
Cc: "Cédric Le Goater" <clg@kaod.org>
Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
Cc: David Gibson <david@gibson.dropbear.id.au>
Cc: Greg Kurz <groug@kaod.org>
Cc: qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org
Cc: qemu-stable@nongnu.org
Signed-off-by: Vitaly Cheptsov <cheptsov@ispras.ru>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220121093107.15478-1-cheptsov@ispras.ru>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 50c8e11ac0672b726a2b3e2217cb32dc8416299f
https://github.com/qemu/qemu/commit/50c8e11ac0672b726a2b3e2217cb32dc8416299f
Author: Frederic Barrat <fbarrat@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/pci-host/pnv_phb3.c
M hw/pci-host/pnv_phb4.c
Log Message:
-----------
ppc/pnv: Fail DMA access if page permissions are not correct
If an iommu page has wrong permissions, an error message is displayed,
but the access is allowed, which is odd. This patch fixes it.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220121152350.381685-1-fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 83d2bea68a778b98ecbf9472be6f1ed8031719ac
https://github.com/qemu/qemu/commit/83d2bea68a778b98ecbf9472be6f1ed8031719ac
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/pci-host/pnv_phb3.c
Log Message:
-----------
ppc/pnv: use a do-while() loop in pnv_phb3_translate_tve()
The 'taddr' variable is left unintialized, being set only inside the
"while ((lev--) >= 0)" loop where we get the TCE address. The 'lev' var
is an int32_t that is being initiliazed by the GETFIELD() macro, which
returns an uint64_t.
For a human reader this means that 'lev' will always be positive or zero.
But some compilers may beg to differ. 'lev' being an int32_t can in theory
be set as negative, and the "while ((lev--) >= 0)" loop might never be
reached, and 'taddr' will be left unitialized. This can cause phb3_error()
to use 'taddr' uninitialized down below:
if ((is_write & !(tce & 2)) || ((!is_write) && !(tce & 1))) {
phb3_error(phb, "TCE access fault at 0x%"PRIx64, taddr);
A quick way of fixing it is to use a do/while() loop. This will keep the
same semanting as the existing while() loop does and the compiler will
understand that 'taddr' will be initialized at least once.
Suggested-by: Matheus K. Ferst <matheus.ferst@eldorado.org.br>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/573
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220127122234.842145-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 799c179ed844b01542e729405c0bf5ef4cd294dc
https://github.com/qemu/qemu/commit/799c179ed844b01542e729405c0bf5ef4cd294dc
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/pci-host/pnv_phb4.c
Log Message:
-----------
ppc/pnv: use a do-while() loop in pnv_phb4_translate_tve()
pnv_phb4_translate_tve() is quite similar to pnv_phb3_translate_tve(),
and that includes the fact that 'taddr' can be considered uninitialized
when throwing the "TCE access fault" error because, in theory, the loop
that sets 'taddr' can be skippable due to 'lev' being an signed int.
No one complained about this specific case yet, but since we took the
time to handle the same situtation in pnv_phb3_translate_tve(), let's
replicate it here as well.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220127122234.842145-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: e9711c6149fc087f5cadd6f60e9ffa5541e421af
https://github.com/qemu/qemu/commit/e9711c6149fc087f5cadd6f60e9ffa5541e421af
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/intc/pnv_xive.c
Log Message:
-----------
ppc/xive: check return value of ldq_be_dma()
The ldq_be_dma() routine was recently changed to return a result of
the transaction. Use it when loading the virtual structure descriptors
in the XIVE PowerNV model.
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220124081635.3672439-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 0c0aac01c49cc159a37841b1954b1938f0582fb4
https://github.com/qemu/qemu/commit/0c0aac01c49cc159a37841b1954b1938f0582fb4
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/helper_regs.c
Log Message:
-----------
target/ppc: fix 'skip KVM' cond in cpu_interrupt_exittb()
cpu_interrupt_exittb() was introduced by commit 044897ef4a22
("target/ppc: Fix system lockups caused by interrupt_request state
corruption") as a way to wrap cpu_interrupt() helper in BQL.
After that, commit 6d38666a8931 ("ppc: Ignore the CPU_INTERRUPT_EXITTB
interrupt with KVM") added a condition to skip this interrupt if we're
running with KVM.
Problem is that the change made by the above commit, testing for
!kvm_enabled() at the start of cpu_interrupt_exittb():
static inline void cpu_interrupt_exittb(CPUState *cs)
{
if (!kvm_enabled()) {
return;
}
(... do cpu_interrupt(cs, CPU_INTERRUPT_EXITTB) ...)
is doing the opposite of what it intended to do. This will return
immediately if not kvm_enabled(), i.e. it's a emulated CPU, and if
kvm_enabled() it will proceed to fire CPU_INTERRUPT_EXITTB.
Fix the 'skip KVM' condition so the function is a no-op when
kvm_enabled().
CC: Greg Kurz <groug@kaod.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/809
Fixes: 6d38666a8931 ("ppc: Ignore the CPU_INTERRUPT_EXITTB interrupt with KVM")
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Message-Id: <20220121160841.9102-1-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 1977434bbfbdd97d28c2fea071ea00bf4ecd0079
https://github.com/qemu/qemu/commit/1977434bbfbdd97d28c2fea071ea00bf4ecd0079
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr.c: check bus != NULL in spapr_get_fw_dev_path()
spapr_get_fw_dev_path() is an impl of
FWPathProviderClass::get_dev_path(). This interface is used by
hw/core/qdev-fw.c via fw_path_provider_try_get_dev_path() in two
functions:
- static char *qdev_get_fw_dev_path_from_handler(), which is used only in
qdev_get_fw_dev_path_helper() and it's guarded by "if (dev &&
dev->parent_bus)";
- char *qdev_get_own_fw_dev_path_from_handler(), which is used in
softmmu/bootdevice.c in get_boot_device_path() like this:
if (dev) {
d = qdev_get_own_fw_dev_path_from_handler(dev->parent_bus, dev);
This means that, when called via softmmu/bootdevice.c, there's no check
of 'dev->parent_bus' being not NULL. The result is that the "BusState
*bus" arg of spapr_get_fw_dev_path() can potentially be NULL and if, at
the same time, "SCSIDevice *d" is not NULL, we'll hit this line:
void *spapr = CAST(void, bus->parent, "spapr-vscsi");
And we'll SIGINT because 'bus' is NULL and we're accessing bus->parent.
Adding a simple 'bus != NULL' check to guard the instances where we
access 'bus->parent' can avoid this altogether.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220121213852.30243-1-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 63f38cc3d228a0886b544e9a069b922b4416d29d
https://github.com/qemu/qemu/commit/63f38cc3d228a0886b544e9a069b922b4416d29d
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/helper_regs.c
Log Message:
-----------
target/ppc: Fix test on mmu_model in hreg_compute_hflags_value()
POWERPC_MMU_BOOKE is not a mask and should not be tested with a
bitwise AND operator.
It went unnoticed because it only impacts the 601 CPU implementation
for which we don't have a known firmware image.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220124081609.3672341-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a01b64cee77061118b8cdaefeacd5440ec26107c
https://github.com/qemu/qemu/commit/a01b64cee77061118b8cdaefeacd5440ec26107c
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Put do_rfi under a TCG-only block
The --disable-tcg build broke when do_rfi stopped being inlined.
Fixes: 62e79ef914 ("target/ppc: Remove static inline")
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220124191547.1008391-1-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: dc10da64e1f704bec8ed66f6a402d22589a3c4f9
https://github.com/qemu/qemu/commit/dc10da64e1f704bec8ed66f6a402d22589a3c4f9
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M hw/ppc/vof.c
M include/hw/ppc/vof.h
Log Message:
-----------
hw/ppc/vof: Add missing includes
vof.h requires "qom/object.h" for DECLARE_CLASS_CHECKERS(),
"exec/memory.h" for address_space_read/write(),
"exec/address-spaces.h" for address_space_memory
and more importantly "cpu.h" for target_ulong.
vof.c doesn't need "exec/ram_addr.h".
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220122003104.84391-1-f4bug@amsat.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 47822486f5e7d6dad8d9a2381d127a831a3c5c11
https://github.com/qemu/qemu/commit/47822486f5e7d6dad8d9a2381d127a831a3c5c11
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/helper.h
M target/ppc/mmu_helper.c
M target/ppc/translate.c
Log Message:
-----------
ppc/ppc405: Fix TLB flushing
Commit cd0c6f473532 did not take into account 405 CPUs when adding
support to batching of TCG tlb flushes. Set the TLB_NEED_LOCAL_FLUSH
flag when the SPR_40x_PID is set or a TLB updated.
Cc: Thomas Huth <thuth@redhat.com>
Cc: Christophe Leroy <christophe.leroy@csgroup.eu>
Cc: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Fixes: cd0c6f473532 ("ppc: Do some batching of TCG tlb flushes")
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220113180352.1234512-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 645d843ca55f0a7aa9be3ef19694d5a44b002f6e
https://github.com/qemu/qemu/commit/645d843ca55f0a7aa9be3ef19694d5a44b002f6e
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: 405: Rename MSR_POW to MSR_WE
Bit 13 is the Wait State Enable bit. Give it its proper name.
As far as I can see we don't do anything with MSR_POW for the 405, so
this change has no effect.
Suggested-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220118184448.852996-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 301e5d48b15d2846cabe0f5c7600860b35c58c12
https://github.com/qemu/qemu/commit/301e5d48b15d2846cabe0f5c7600860b35c58c12
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: 405: Add missing MSR_ME bit
The 405 MSR has the Machine Check Enable bit. We're making use of it
when dispatching Machine Check, so add the bit to the msr_mask.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220118184448.852996-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: e808c2ed07f25b93ed796dfe266a30f2236ad69a
https://github.com/qemu/qemu/commit/e808c2ed07f25b93ed796dfe266a30f2236ad69a
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Introduce powerpc_excp_40x
Introduce a new powerpc_excp function specific for 40x CPUs. This
commit copies powerpc_excp_legacy verbatim so the next one has a clean
diff.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220118184448.852996-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 495fc7ff9677edc31b97084fb17db91737ce4ea4
https://github.com/qemu/qemu/commit/495fc7ff9677edc31b97084fb17db91737ce4ea4
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Simplify powerpc_excp_40x
Differences from the generic powerpc_excp code:
- Not BookE, so some MSR bits are cleared at interrupt dispatch;
- No MSR_HV or MSR_LE;
- No power saving states;
- No Hypervisor Emulation Assistance;
- Not 64 bits;
- No System call vectored;
- No Interrupts Little Endian;
- No Alternate Interrupt Location.
Exceptions used:
POWERPC_EXCP_ALIGN
POWERPC_EXCP_CRITICAL
POWERPC_EXCP_DEBUG
POWERPC_EXCP_DSI
POWERPC_EXCP_DTLB
POWERPC_EXCP_EXTERNAL
POWERPC_EXCP_FIT
POWERPC_EXCP_ISI
POWERPC_EXCP_ITLB
POWERPC_EXCP_MCHECK
POWERPC_EXCP_PIT
POWERPC_EXCP_PROGRAM
POWERPC_EXCP_SYSCALL
POWERPC_EXCP_WDT
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220118184448.852996-5-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ba96828ec25f04fd6b0b93076be506fe5adc6f6d
https://github.com/qemu/qemu/commit/ba96828ec25f04fd6b0b93076be506fe5adc6f6d
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 405: Critical exceptions cleanup
In powerpc_excp_40x the Critical exception is now for 405 only, so we
can remove the BookE and G2 blocks.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220118184448.852996-6-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2149e6518032e2209c7520bda6aa38b98850def6
https://github.com/qemu/qemu/commit/2149e6518032e2209c7520bda6aa38b98850def6
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 405: Machine check exception cleanup
powerpc_excp_40x applies only to the 405, so remove HV code and
references to BookE.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220118184448.852996-7-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9026e99c894a85774b8fdf4bd32a2233863fc2f8
https://github.com/qemu/qemu/commit/9026e99c894a85774b8fdf4bd32a2233863fc2f8
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 405: External exception cleanup
405 has no MSR_HV and EPR is BookE only so we can remove it all.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220118184448.852996-8-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 8428cdb245099dcf03c32e1b66f530ada65a6e83
https://github.com/qemu/qemu/commit/8428cdb245099dcf03c32e1b66f530ada65a6e83
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 405: System call exception cleanup
There's no sc 1.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220118184448.852996-9-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 66b5ad561552c5c77058502ea3c7f04316937b64
https://github.com/qemu/qemu/commit/66b5ad561552c5c77058502ea3c7f04316937b64
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 405: Alignment exception cleanup
There is no DSISR in the 405. It uses DEAR which we already set
earlier at ppc_cpu_do_unaligned_access.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au
Message-Id: <20220118184448.852996-10-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 4d8ac1d15ec34d0967c7e51e375e72c522c1e6b5
https://github.com/qemu/qemu/commit/4d8ac1d15ec34d0967c7e51e375e72c522c1e6b5
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 405: Debug exception cleanup
The current Debug exception dispatch is the BookE one, so it is
different from the 405. We effectively don't support the 405 Debug
exception.
This patch removes the BookE code and moves the DEBUG into the "not
implemented" block.
Note that there is in theory a functional change here since we now
abort when a Debug exception happens. However, given how it was never
implemented, I don't believe this to have ever been dispatched for the
405.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220118184448.852996-11-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f9911e1e5513ebf661ae871ae31269a9a1cfabdc
https://github.com/qemu/qemu/commit/f9911e1e5513ebf661ae871ae31269a9a1cfabdc
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 405: Data Storage exception cleanup
The 405 has no DSISR or DAR, so convert the trace entry to
use ESR and DEAR instead.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg : - changed registers to ESR and DEAR.
- updated commit log ]
Message-Id: <20220118184448.852996-12-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 35f579f5c21682311039f84e2e81254937e6ff78
https://github.com/qemu/qemu/commit/35f579f5c21682311039f84e2e81254937e6ff78
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 405: Instruction storage interrupt cleanup
The 405 ISI does not set SRR1 with any exception syndrome bits, only a
clean copy of the MSR.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg : Fixed removal which was done in the wrong routine ]
Message-Id: <20220118184448.852996-13-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 64e62cfbec19ed22d097645219bdddb55df6f562
https://github.com/qemu/qemu/commit/64e62cfbec19ed22d097645219bdddb55df6f562
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 405: Program exception cleanup
The 405 Program Interrupt does not set SRR1 with any diagnostic bits,
just a clean copy of the MSR.
We're using the BookE Exception Syndrome Register which is different
from the 405.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: restored SPR_40x_ESR settings ]
Message-Id: <20220118184448.852996-14-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 1afe57802ab0127b31b323be171ba9c943a04133
https://github.com/qemu/qemu/commit/1afe57802ab0127b31b323be171ba9c943a04133
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 405: Watchdog timer exception cleanup
Remove references to BookE.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220118184448.852996-15-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9f338e4da17a73cd1b78bbef02f797d7edfd133a
https://github.com/qemu/qemu/commit/9f338e4da17a73cd1b78bbef02f797d7edfd133a
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Introduce powerpc_excp_books
Introduce a new powerpc_excp function specific for BookS CPUs. This
commit copies powerpc_excp_legacy verbatim so the next one has a clean
diff.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220124184605.999353-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 30c4e4269c168187f4f681e7b87db5333fd0603e
https://github.com/qemu/qemu/commit/30c4e4269c168187f4f681e7b87db5333fd0603e
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Simplify powerpc_excp_books
Differences from the generic powerpc_excp code:
- Not BookE, so some MSR bits are cleared at interrupt dispatch;
- Always uses HV_EMU if the CPU has MSR_HV;
- Exceptions always delivered in 64 bit.
Exceptions used:
POWERPC_EXCP_ALIGN
POWERPC_EXCP_DECR
POWERPC_EXCP_DSEG
POWERPC_EXCP_DSI
POWERPC_EXCP_EXTERNAL
POWERPC_EXCP_FPU
POWERPC_EXCP_FU
POWERPC_EXCP_HDECR
POWERPC_EXCP_HDSI
POWERPC_EXCP_HISI
POWERPC_EXCP_HVIRT
POWERPC_EXCP_HV_EMU
POWERPC_EXCP_HV_FU
POWERPC_EXCP_ISEG
POWERPC_EXCP_ISI
POWERPC_EXCP_MAINT
POWERPC_EXCP_MCHECK
POWERPC_EXCP_PERFM
POWERPC_EXCP_PROGRAM
POWERPC_EXCP_RESET
POWERPC_EXCP_SDOOR_HV
POWERPC_EXCP_SYSCALL
POWERPC_EXCP_SYSCALL_VECTORED
POWERPC_EXCP_THERM
POWERPC_EXCP_TRACE
POWERPC_EXCP_VPU
POWERPC_EXCP_VPUA
POWERPC_EXCP_VSXU
POWERPC_EXCP_HV_MAINT
POWERPC_EXCP_SDOOR
(I added the two above that were not being considered. They used to be
"Invalid exception". Now they become "Unimplemented exception" which
is more accurate.)
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220124184605.999353-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 58a02119f39581409444c31e04d6b8b2c15e6f8e
https://github.com/qemu/qemu/commit/58a02119f39581409444c31e04d6b8b2c15e6f8e
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: books: Machine Check exception cleanup
powerpc_excp_books is BookS only, so remove 40x and BookE code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220124184605.999353-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 67baff7715b3c1a2beb7df7af615eb3f132b9d13
https://github.com/qemu/qemu/commit/67baff7715b3c1a2beb7df7af615eb3f132b9d13
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: books: External interrupt cleanup
Since this is now BookS only, we can simplify the code a bit and check
has_hv_mode instead of enumerating the exception models. LPES0 does
not make sense if there is no MSR_HV.
Note that QEMU does not support HV mode on 970 and POWER5+ so we don't
set MSR_HV in msr_mask.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220124184605.999353-5-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: aca2b93fd7edd00d70bf51bf01428e8f2b6456e0
https://github.com/qemu/qemu/commit/aca2b93fd7edd00d70bf51bf01428e8f2b6456e0
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: books: Program exception cleanup
Remove setting of BookE registers.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220124184605.999353-6-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 52926b0debd4aeced56c1560a4ff77b56547df22
https://github.com/qemu/qemu/commit/52926b0debd4aeced56c1560a4ff77b56547df22
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Introduce powerpc_excp_74xx
Introduce a new powerpc_excp function specific for PowerPC 74xx
CPUs. This commit copies powerpc_excp_legacy verbatim so the next one
has a clean diff.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220127201116.1154733-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 1f6faf8b1451c41add592427c573ca76817aceec
https://github.com/qemu/qemu/commit/1f6faf8b1451c41add592427c573ca76817aceec
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Simplify powerpc_excp_74xx
Differences from the generic powerpc_excp code:
- Not BookE, so some MSR bits are cleared at interrupt dispatch;
- No MSR_HV;
- No power saving states;
- No Hypervisor Emulation Assistance;
- Not 64 bits;
- No System call vectored;
- No Alternate Interrupt Location.
Exceptions used:
POWERPC_EXCP_ALIGN
POWERPC_EXCP_DECR
POWERPC_EXCP_DSI
POWERPC_EXCP_EXTERNAL
POWERPC_EXCP_FPU
POWERPC_EXCP_IABR
POWERPC_EXCP_ISI
POWERPC_EXCP_MCHECK
POWERPC_EXCP_PERFM
POWERPC_EXCP_PROGRAM
POWERPC_EXCP_RESET
POWERPC_EXCP_SMI
POWERPC_EXCP_SYSCALL
POWERPC_EXCP_THERM
POWERPC_EXCP_TRACE
POWERPC_EXCP_VPU
POWERPC_EXCP_VPUA
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220127201116.1154733-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 3fbb46409f012aea9c1443ae4bd9f49d4fcabd75
https://github.com/qemu/qemu/commit/3fbb46409f012aea9c1443ae4bd9f49d4fcabd75
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 74xx: Machine Check exception cleanup
The 74xx don't have an MSR_HV.
Also remove 40x and BookE code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220127201116.1154733-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 12e8042698a0682ff87909f513345b6d52c3de2e
https://github.com/qemu/qemu/commit/12e8042698a0682ff87909f513345b6d52c3de2e
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 74xx: External interrupt cleanup
The 74xx don't have MSR_HV so all the LPES0 logic can be removed.
Also remove the BookE IRQ code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220127201116.1154733-5-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 0ea2a65fe811700d3be94150b5a83af2ee828c91
https://github.com/qemu/qemu/commit/0ea2a65fe811700d3be94150b5a83af2ee828c91
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 74xx: Program exception cleanup
Remove the BookE ESR setting.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220127201116.1154733-6-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: bca2c6d9e09177c5a6959c3c372dab8211f39404
https://github.com/qemu/qemu/commit/bca2c6d9e09177c5a6959c3c372dab8211f39404
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 74xx: System Call exception cleanup
Remove the BookE code and add a comment explaining why we need to keep
hypercall support even though this CPU does not have a hypervisor
mode.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220127201116.1154733-7-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 91a51fecef20ba4ee659a68a55b2b556f070908d
https://github.com/qemu/qemu/commit/91a51fecef20ba4ee659a68a55b2b556f070908d
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 74xx: System Reset interrupt cleanup
The whole power saving states logic seems to be dependent on HV mode,
which don't exist for 74xx so I'm removing it all and leaving the
abort message.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220127201116.1154733-8-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f82db77761806613a62f622db9c1ca613ae1e6ed
https://github.com/qemu/qemu/commit/f82db77761806613a62f622db9c1ca613ae1e6ed
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: 74xx: Set SRRs directly in exception code
The 74xx does not have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220127201116.1154733-9-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 4537d62dcece45183632298272abfb4859418cc0
https://github.com/qemu/qemu/commit/4537d62dcece45183632298272abfb4859418cc0
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-01-28 (Fri, 28 Jan 2022)
Changed paths:
M target/ppc/cpu-models.c
M target/ppc/cpu-models.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/helper.h
M target/ppc/int_helper.c
R target/ppc/mfrom_table.c.inc
R target/ppc/mfrom_table_gen.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Remove support for the PowerPC 602 CPU
The 602 was derived from the PowerPC 603, for the gaming market it
seems. It was hardly used and no firmware supporting the CPU could be
found. Drop support.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 804b30d25f8d70dc2dea951883ea92235274a50c
https://github.com/qemu/qemu/commit/804b30d25f8d70dc2dea951883ea92235274a50c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-31 (Mon, 31 Jan 2022)
Changed paths:
M hw/intc/pnv_xive.c
M hw/pci-host/pnv_phb3.c
M hw/pci-host/pnv_phb4.c
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_vof.c
M hw/ppc/vof.c
M include/hw/ppc/vof.h
M target/ppc/cpu-models.c
M target/ppc/cpu-models.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/helper.h
M target/ppc/helper_regs.c
M target/ppc/int_helper.c
R target/ppc/mfrom_table.c.inc
R target/ppc/mfrom_table_gen.c
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
M target/ppc/translate.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220130' into
staging
ppc 7.0 queue:
* Exception and TLB fixes for the 405 CPU (Fabiano and Cedric)
* spapr fixes (Alexey and Daniel)
* PowerNV PHB3/4 fixes (Frederic and Daniel)
* PowerNV XIVE improvements (Cedric)
* 603 CPUs fixes (Christophe)
* Book-E exception fixes (Vitaly)
* Misc compile issues (Philippe and Fabiano)
* Exception model rework for the BookS CPUs (Fabiano)
* Exception model rework for the 74xx CPUs (Fabiano)
* Removal of 602 CPUs
# gpg: Signature made Sun 30 Jan 2022 17:42:23 GMT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* remotes/legoater/tags/pull-ppc-20220130: (41 commits)
target/ppc: Remove support for the PowerPC 602 CPU
target/ppc: 74xx: Set SRRs directly in exception code
target/ppc: 74xx: System Reset interrupt cleanup
target/ppc: 74xx: System Call exception cleanup
target/ppc: 74xx: Program exception cleanup
target/ppc: 74xx: External interrupt cleanup
target/ppc: 74xx: Machine Check exception cleanup
target/ppc: Simplify powerpc_excp_74xx
target/ppc: Introduce powerpc_excp_74xx
target/ppc: books: Program exception cleanup
target/ppc: books: External interrupt cleanup
target/ppc: books: Machine Check exception cleanup
target/ppc: Simplify powerpc_excp_books
target/ppc: Introduce powerpc_excp_books
target/ppc: 405: Watchdog timer exception cleanup
target/ppc: 405: Program exception cleanup
target/ppc: 405: Instruction storage interrupt cleanup
target/ppc: 405: Data Storage exception cleanup
target/ppc: 405: Debug exception cleanup
target/ppc: 405: Alignment exception cleanup
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/bfc3db5cf64a...804b30d25f8d