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[Qemu-commits] [qemu/qemu] 95ea96: hw/arm/virt: KVM: Enable PAuth when s
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 95ea96: hw/arm/virt: KVM: Enable PAuth when supported by t... |
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Date: |
Thu, 20 Jan 2022 13:18:50 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 95ea96e8b1610f2d1bfa2abd0d12c40d647e563d
https://github.com/qemu/qemu/commit/95ea96e8b1610f2d1bfa2abd0d12c40d647e563d
Author: Marc Zyngier <maz@kernel.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M docs/system/arm/cpu-features.rst
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/kvm64.c
Log Message:
-----------
hw/arm/virt: KVM: Enable PAuth when supported by the host
Add basic support for Pointer Authentication when running a KVM
guest and that the host supports it, loosely based on the SVE
support.
Although the feature is enabled by default when the host advertises
it, it is possible to disable it by setting the 'pauth=off' CPU
property. The 'pauth' comment is removed from cpu-features.rst,
as it is now common to both TCG and KVM.
Tested on an Apple M1 running 5.16-rc6.
Cc: Eric Auger <eric.auger@redhat.com>
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220107150154.2490308-1-maz@kernel.org
[PMM: fixed indentation]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9adfbf1b6116125d32d5b1608781a9935e517afd
https://github.com/qemu/qemu/commit/9adfbf1b6116125d32d5b1608781a9935e517afd
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/arm/Kconfig
M hw/audio/Kconfig
Log Message:
-----------
hw: Move MARVELL_88W8618 Kconfig from audio/ to arm/
The Marvell 88W8618 is a system-on-chip with an ARM core.
We implement its audio codecs and network interface.
Homogeneous SoC Kconfig are usually defined in the hw/$ARCH
directory. Move it there.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220107184429.423572-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8ede0245e210075f6272b6c91cde648a01003676
https://github.com/qemu/qemu/commit/8ede0245e210075f6272b6c91cde648a01003676
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/arm/musicpal.c
Log Message:
-----------
hw/arm/musicpal: Fix coding style of code related to MV88W8618 device
We are going to move this code, so fix its style first to avoid:
ERROR: spaces required around that '/' (ctx:VxV)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220107184429.423572-3-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6d81f4887f66995ca94fce5f896b26339a537bd9
https://github.com/qemu/qemu/commit/6d81f4887f66995ca94fce5f896b26339a537bd9
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M MAINTAINERS
M hw/arm/musicpal.c
M hw/net/meson.build
A hw/net/mv88w8618_eth.c
A include/hw/net/mv88w8618_eth.h
Log Message:
-----------
hw/net: Move MV88W8618 network device out of hw/arm/ directory
The Marvell 88W8618 network device is hidden in the Musicpal
machine. Move it into a new unit file under the hw/net/ directory.
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220107184429.423572-4-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d55c316f910edcffbda6159053dfd59c7af02042
https://github.com/qemu/qemu/commit/d55c316f910edcffbda6159053dfd59c7af02042
Author: Yanan Wang <wangyanan55@huawei.com>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/arm/virt.c
M qemu-options.hx
Log Message:
-----------
hw/arm/virt: Support CPU cluster on ARM virt machine
ARM64 machines like Kunpeng Family Server Chips have a level
of hardware topology in which a group of CPU cores share L3
cache tag or L2 cache. For example, Kunpeng 920 typically
has 6 or 8 clusters in each NUMA node (also represent range
of CPU die), and each cluster has 4 CPU cores. All clusters
share L3 cache data, but CPU cores in each cluster share a
local L3 tag.
Running a guest kernel with Cluster-Aware Scheduling on the
Hosts which have physical clusters, if we can design a vCPU
topology with cluster level for guest kernel and then have
a dedicated vCPU pinning, the guest will gain scheduling
performance improvement from cache affinity of CPU cluster.
So let's enable the support for this new parameter on ARM
virt machines. After this patch, we can define a 4-level
CPU hierarchy like: cpus=*,maxcpus=*,sockets=*,clusters=*,
cores=*,threads=*.
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20220107083232.16256-2-wangyanan55@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 28a60a59c06a13cb8dbbdbc06029f3d2031eb45d
https://github.com/qemu/qemu/commit/28a60a59c06a13cb8dbbdbc06029f3d2031eb45d
Author: Yanan Wang <wangyanan55@huawei.com>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Support cluster level in DT cpu-map
Support one cluster level between core and physical package in the
cpu-map of Arm/virt devicetree. This is also consistent with Linux
Doc "Documentation/devicetree/bindings/cpu/cpu-topology.txt".
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20220107083232.16256-3-wangyanan55@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 11b9eb1b8a96510508178746b258810392849b20
https://github.com/qemu/qemu/commit/11b9eb1b8a96510508178746b258810392849b20
Author: Yanan Wang <wangyanan55@huawei.com>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/acpi/aml-build.c
Log Message:
-----------
hw/acpi/aml-build: Improve scalability of PPTT generation
Use g_queue APIs to reduce the nested loops and code indentation
with the processor hierarchy levels increasing. Consenquently,
it's more scalable to add new topology level to build_pptt.
No functional change intended.
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20220107083232.16256-4-wangyanan55@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 291f6dd566cf1158cbdb90e282c89adbb2d2a875
https://github.com/qemu/qemu/commit/291f6dd566cf1158cbdb90e282c89adbb2d2a875
Author: Yanan Wang <wangyanan55@huawei.com>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi/bios-tables-test: Allow changes to virt/PPTT file
List test/data/acpi/virt/PPTT as the expected files allowed to
be changed in tests/qtest/bios-tables-test-allowed-diff.h
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: Ani Sinha <ani@anisinha.ca>
Message-id: 20220107083232.16256-5-wangyanan55@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 88d0278aa7f5c882d8a485788ab4bae4702099b8
https://github.com/qemu/qemu/commit/88d0278aa7f5c882d8a485788ab4bae4702099b8
Author: Yanan Wang <wangyanan55@huawei.com>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/acpi/aml-build.c
Log Message:
-----------
hw/acpi/aml-build: Support cluster level in PPTT generation
Support CPU cluster topology level in generation of ACPI
Processor Properties Topology Table (PPTT).
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20220107083232.16256-6-wangyanan55@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3cda85b20308a92faa1e6e66435441735f313881
https://github.com/qemu/qemu/commit/3cda85b20308a92faa1e6e66435441735f313881
Author: Yanan Wang <wangyanan55@huawei.com>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M tests/data/acpi/virt/PPTT
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi/bios-table-test: Update expected virt/PPTT file
Run ./tests/data/acpi/rebuild-expected-aml.sh from build directory
to update PPTT binary. Also empty bios-tables-test-allowed-diff.h.
The disassembled differences between actual and expected PPTT:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200528 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/virt/PPTT, Tue Jan 4 12:51:11 2022
+ * Disassembly of /tmp/aml-2ZGOF1, Tue Jan 4 12:51:11 2022
*
* ACPI Data Table [PPTT]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "PPTT" [Processor Properties
Topology Table]
-[004h 0004 4] Table Length : 0000004C
+[004h 0004 4] Table Length : 00000060
[008h 0008 1] Revision : 02
-[009h 0009 1] Checksum : A8
+[009h 0009 1] Checksum : 48
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 1] Subtable Type : 00 [Processor Hierarchy Node]
[025h 0037 1] Length : 14
[026h 0038 2] Reserved : 0000
[028h 0040 4] Flags (decoded below) : 00000001
Physical package : 1
ACPI Processor ID valid : 0
Processor is a thread : 0
Node is a leaf : 0
Identical Implementation : 0
[02Ch 0044 4] Parent : 00000000
[030h 0048 4] ACPI Processor ID : 00000000
[034h 0052 4] Private Resource Number : 00000000
[038h 0056 1] Subtable Type : 00 [Processor Hierarchy Node]
[039h 0057 1] Length : 14
[03Ah 0058 2] Reserved : 0000
-[03Ch 0060 4] Flags (decoded below) : 0000000A
+[03Ch 0060 4] Flags (decoded below) : 00000000
Physical package : 0
- ACPI Processor ID valid : 1
+ ACPI Processor ID valid : 0
Processor is a thread : 0
- Node is a leaf : 1
+ Node is a leaf : 0
Identical Implementation : 0
[040h 0064 4] Parent : 00000024
[044h 0068 4] ACPI Processor ID : 00000000
[048h 0072 4] Private Resource Number : 00000000
-Raw Table Data: Length 76 (0x4C)
+[04Ch 0076 1] Subtable Type : 00 [Processor Hierarchy Node]
+[04Dh 0077 1] Length : 14
+[04Eh 0078 2] Reserved : 0000
+[050h 0080 4] Flags (decoded below) : 0000000A
+ Physical package : 0
+ ACPI Processor ID valid : 1
+ Processor is a thread : 0
+ Node is a leaf : 1
+ Identical Implementation : 0
+[054h 0084 4] Parent : 00000038
+[058h 0088 4] ACPI Processor ID : 00000000
+[05Ch 0092 4] Private Resource Number : 00000000
+
+Raw Table Data: Length 96 (0x60)
- 0000: 50 50 54 54 4C 00 00 00 02 A8 42 4F 43 48 53 20 // PPTTL.....BOCHS
+ 0000: 50 50 54 54 60 00 00 00 02 48 42 4F 43 48 53 20 // PPTT`....HBOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 00 14 00 00 01 00 00 00 00 00 00 00 // ................
- 0030: 00 00 00 00 00 00 00 00 00 14 00 00 0A 00 00 00 // ................
- 0040: 24 00 00 00 00 00 00 00 00 00 00 00 // $...........
+ 0030: 00 00 00 00 00 00 00 00 00 14 00 00 00 00 00 00 // ................
+ 0040: 24 00 00 00 00 00 00 00 00 00 00 00 00 14 00 00 // $...............
+ 0050: 0A 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 // ....8...........
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Reviewed-by: Ani Sinha <ani@anisinha.ca>
Message-id: 20220107083232.16256-7-wangyanan55@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 87f14eaa5198373e8716d6e71ad10d48ea2e7ec6
https://github.com/qemu/qemu/commit/87f14eaa5198373e8716d6e71ad10d48ea2e7ec6
Author: Lucas Ramage <lucas.ramage@infinite-omicron.com>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
R docs/can.txt
M docs/system/device-emulation.rst
A docs/system/devices/can.rst
Log Message:
-----------
docs/can: convert to restructuredText
Buglink: https://gitlab.com/qemu-project/qemu/-/issues/527
Signed-off-by: Lucas Ramage <lucas.ramage@infinite-omicron.com>
Message-id: 20220105205628.5491-1-oxr463@gmx.us
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: Move to docs/system/devices/ rather than top-level;
fix a pre-existing typo in passing]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1263615efe51e5f1f38f4818f0de88abc33b49a6
https://github.com/qemu/qemu/commit/1263615efe51e5f1f38f4818f0de88abc33b49a6
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/virtio/virtio-mem.c
Log Message:
-----------
virtio-mem: Correct default THP size for ARM64
The default block size is same as to the THP size, which is either
retrieved from "/sys/kernel/mm/transparent_hugepage/hpage_pmd_size"
or hardcoded to 2MB. There are flaws in both mechanisms and this
intends to fix them up.
* When "/sys/kernel/mm/transparent_hugepage/hpage_pmd_size" is
used to getting the THP size, 32MB and 512MB are valid values
when we have 16KB and 64KB page size on ARM64.
* When the hardcoded THP size is used, 2MB, 32MB and 512MB are
valid values when we have 4KB, 16KB and 64KB page sizes on
ARM64.
Co-developed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-id: 20220111063329.74447-2-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b1b87327a903e298b3b4c79da0beed31b57fb594
https://github.com/qemu/qemu/commit/b1b87327a903e298b3b4c79da0beed31b57fb594
Author: Gavin Shan <gshan@redhat.com>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/arm/Kconfig
M hw/arm/virt.c
M hw/virtio/virtio-mem.c
Log Message:
-----------
hw/arm/virt: Support for virtio-mem-pci
This supports virtio-mem-pci device on "virt" platform, by simply
following the implementation on x86.
* This implements the hotplug handlers to support virtio-mem-pci
device hot-add, while the hot-remove isn't supported as we have
on x86.
* The block size is 512MB on ARM64 instead of 128MB on x86.
* It has been passing the tests with various combinations like 64KB
and 4KB page sizes on host and guest, different memory device
backends like normal, transparent huge page and HugeTLB, plus
migration.
Co-developed-by: David Hildenbrand <david@redhat.com>
Co-developed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-id: 20220111063329.74447-3-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a66a24585fae7036dc2f358c9addd1630be5c50c
https://github.com/qemu/qemu/commit/a66a24585fae7036dc2f358c9addd1630be5c50c
Author: Petr Pavlu <petr.pavlu@suse.com>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/intc/arm_gic.c
Log Message:
-----------
hw/intc/arm_gic: Implement read of GICC_IIDR
Implement support for reading GICC_IIDR. This register is used by the
Linux kernel to recognize that GICv2 with GICC_APRn is present.
Signed-off-by: Petr Pavlu <petr.pavlu@suse.com>
Message-id: 20220113151916.17978-2-ppavlu@suse.cz
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5e66daec9ef0cd0107ba30225e23224c66ed24f3
https://github.com/qemu/qemu/commit/5e66daec9ef0cd0107ba30225e23224c66ed24f3
Author: Petr Pavlu <petr.pavlu@suse.com>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/intc/arm_gic.c
Log Message:
-----------
hw/intc/arm_gic: Allow reset of the running priority
When running Linux on a machine with GICv2, the kernel can crash while
processing an interrupt and can subsequently start a kdump kernel from
the active interrupt handler. In such a case, the crashed kernel might
not gracefully signal the end of interrupt to the GICv2 hardware. The
kdump kernel will however try to reset the GIC state on startup to get
the controller into a sane state, in particular the kernel writes ones
to GICD_ICACTIVERn and wipes out GICC_APRn to make sure that no
interrupt is active.
The patch adds a logic to recalculate the running priority when
GICC_APRn/GICC_NSAPRn is written which makes sure that the mentioned
reset works with the GICv2 emulation in QEMU too and the kdump kernel
starts receiving interrupts.
The described scenario can be reproduced on an AArch64 QEMU virt machine
with a kdump-enabled Linux system by using the softdog module. The kdump
kernel will hang at some point because QEMU still thinks the running
priority is that of the timer interrupt and asserts no new interrupts to
the system:
$ modprobe softdog soft_margin=10 soft_panic=1
$ cat > /dev/watchdog
[Press Enter to start the watchdog, wait for its timeout and observe
that the kdump kernel hangs on startup.]
Signed-off-by: Petr Pavlu <petr.pavlu@suse.com>
Message-id: 20220113151916.17978-3-ppavlu@suse.cz
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c8f008c40fb9dc35bc0fdcd52d747c920d614725
https://github.com/qemu/qemu/commit/c8f008c40fb9dc35bc0fdcd52d747c920d614725
Author: Marc Zyngier <maz@kernel.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M include/hw/arm/virt.h
Log Message:
-----------
hw/arm/virt: Add a control for the the highmem PCIe MMIO
Just like we can control the enablement of the highmem PCIe ECAM
region using highmem_ecam, let's add a control for the highmem
PCIe MMIO region.
Similarily to highmem_ecam, this region is disabled when highmem
is off.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20220114140741.1358263-2-maz@kernel.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a63618b147443de2485fb93705e21879b25c64c2
https://github.com/qemu/qemu/commit/a63618b147443de2485fb93705e21879b25c64c2
Author: Marc Zyngier <maz@kernel.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M include/hw/arm/virt.h
Log Message:
-----------
hw/arm/virt: Add a control for the the highmem redistributors
Just like we can control the enablement of the highmem PCIe region
using highmem_ecam, let's add a control for the highmem GICv3
redistributor region.
Similarily to highmem_ecam, these redistributors are disabled when
highmem is off.
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20220114140741.1358263-3-maz@kernel.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0152b169ce163b99660b80a8ed6664707e889052
https://github.com/qemu/qemu/commit/0152b169ce163b99660b80a8ed6664707e889052
Author: Marc Zyngier <maz@kernel.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Honor highmem setting when computing the memory map
Even when the VM is configured with highmem=off, the highest_gpa
field includes devices that are above the 4GiB limit.
Similarily, nothing seem to check that the memory is within
the limit set by the highmem=off option.
This leads to failures in virt_kvm_type() on systems that have
a crippled IPA range, as the reported IPA space is larger than
what it should be.
Instead, honor the user-specified limit to only use the devices
at the lowest end of the spectrum, and fail if we have memory
crossing the 4GiB limit.
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Message-id: 20220114140741.1358263-4-maz@kernel.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3715c251cc781b263fbd7f7c535fde7a4da401c3
https://github.com/qemu/qemu/commit/3715c251cc781b263fbd7f7c535fde7a4da401c3
Author: Marc Zyngier <maz@kernel.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Use the PA range to compute the memory map
The highmem attribute is nothing but another way to express the
PA range of a VM. To support HW that has a smaller PA range then
what QEMU assumes, pass this PA range to the virt_set_memmap()
function, allowing it to correctly exclude highmem devices
if they are outside of the PA range.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20220114140741.1358263-5-maz@kernel.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d9afe24c29a0985b29d7535b2f1615affbd1a888
https://github.com/qemu/qemu/commit/d9afe24c29a0985b29d7535b2f1615affbd1a888
Author: Marc Zyngier <maz@kernel.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Disable highmem devices that don't fit in the PA range
In order to only keep the highmem devices that actually fit in
the PA range, check their location against the range and update
highest_gpa if they fit. If they don't, mark them as disabled.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20220114140741.1358263-6-maz@kernel.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2dcb74e5c271b9bb581013b949e4ef3bb3f6969b
https://github.com/qemu/qemu/commit/2dcb74e5c271b9bb581013b949e4ef3bb3f6969b
Author: Marc Zyngier <maz@kernel.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Drop superfluous checks against highmem
Now that the devices present in the extended memory map are checked
against the available PA space and disabled when they don't fit,
there is no need to keep the same checks against highmem, as
highmem really is a shortcut for the PA space being 32bit.
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Message-id: 20220114140741.1358263-7-maz@kernel.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0419e6a867f9cbb4edc819b5d278a33f441b6051
https://github.com/qemu/qemu/commit/0419e6a867f9cbb4edc819b5d278a33f441b6051
Author: Patrick Venture <venture@google.com>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/arm/npcm7xx_boards.c
Log Message:
-----------
hw/arm: kudo add lm75s behind bus 1 switch at 75
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Patrick Venture <venture@google.com>
Message-id: 20220111172338.1525587-1-venture@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 119df56bf059431190ed5509f6e3e459d7892723
https://github.com/qemu/qemu/commit/119df56bf059431190ed5509f6e3e459d7892723
Author: Troy Lee <troy_lee@aspeedtech.com>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
A hw/misc/aspeed_i3c.c
M hw/misc/meson.build
M hw/misc/trace-events
A include/hw/misc/aspeed_i3c.h
Log Message:
-----------
hw/misc/aspeed_i3c.c: Introduce a dummy AST2600 I3C model.
Aspeed 2600 SDK enables I3C support by default. The I3C driver will try
to reset the device controller and set it up through device address table
register. This dummy model responds to these registers with default values
as listed in the ast2600v10 datasheet chapter 54.2.
This avoids a guest machine kernel panic due to referencing an
invalid kernel address if the device address table register isn't
set correctly.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Reviewed-by: Graeme Gregory <quic_ggregory@quicinc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Graeme Gregory <quic_ggregory@quicinc.com>
Message-id: 20220111084546.4145785-2-troy_lee@aspeedtech.com
[PMM: tidied commit message; fixed format strings]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3222165dcb7ec2d390e400d5c886d67b582f37d7
https://github.com/qemu/qemu/commit/3222165dcb7ec2d390e400d5c886d67b582f37d7
Author: Troy Lee <troy_lee@aspeedtech.com>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/arm/aspeed_ast2600.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed: Add the i3c device to the AST2600 SoC
Add the new i3c device to the AST2600 SoC.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Reviewed-by: Graeme Gregory <quic_ggregory@quicinc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Graeme Gregory <quic_ggregory@quicinc.com>
Message-id: 20220111084546.4145785-3-troy_lee@aspeedtech.com
[PMM: tidied commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8f809f699251dcf28811b9693a196ff02367d7d6
https://github.com/qemu/qemu/commit/8f809f699251dcf28811b9693a196ff02367d7d6
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc/arm_gicv3_its: Fix event ID bounds checks
In process_its_cmd() and process_mapti() we must check the
event ID against a limit defined by the size field in the DTE,
which specifies the number of ID bits minus one. Convert
this code to our num_foo convention:
* change the variable names
* use uint64_t and 1ULL when calculating the number
of valid event IDs, because DTE.SIZE is 5 bits and
so num_eventids may be up to 2^32
* fix the off-by-one error in the comparison
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20220111171048.3545974-2-peter.maydell@linaro.org
Commit: 905720f18d77e9ca8737d3ff047cad9079cbde6d
https://github.com/qemu/qemu/commit/905720f18d77e9ca8737d3ff047cad9079cbde6d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc/arm_gicv3_its: Convert int ID check to num_intids convention
The bounds check on the number of interrupt IDs is correct, but
doesn't match our convention; change the variable name, initialize it
to the 2^n value rather than (2^n)-1, and use >= instead of > in the
comparison.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20220111171048.3545974-3-peter.maydell@linaro.org
Commit: 7d62b2dcdb04fa625abb6600dbffd4464c3e4a85
https://github.com/qemu/qemu/commit/7d62b2dcdb04fa625abb6600dbffd4464c3e4a85
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc/arm_gicv3_its: Fix handling of process_its_cmd() return value
process_its_cmd() returns a bool, like all the other process_ functions.
However we were putting its return value into 'res', not 'result',
which meant we would ignore it when deciding whether to continue
or stall the command queue. Fix the typo.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220111171048.3545974-4-peter.maydell@linaro.org
Commit: f0b4b2a28c4ab26505f13f07da07190387f848a4
https://github.com/qemu/qemu/commit/f0b4b2a28c4ab26505f13f07da07190387f848a4
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc/arm_gicv3_its: Don't use data if reading command failed
In process_cmdq(), we read 64 bits of the command packet, which
contain the command identifier, which we then switch() on to dispatch
to an appropriate sub-function. However, if address_space_ldq_le()
reports a memory transaction failure, we still read the command
identifier out of the data and switch() on it. Restructure the code
so that we stop immediately (stalling the command queue) in this
case.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220111171048.3545974-5-peter.maydell@linaro.org
Commit: ef011555da8bcabd74ebd79f6a4e1c2ec763efd0
https://github.com/qemu/qemu/commit/ef011555da8bcabd74ebd79f6a4e1c2ec763efd0
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc/arm_gicv3_its: Use enum for return value of process_* functions
When an ITS detects an error in a command, it has an
implementation-defined (CONSTRAINED UNPREDICTABLE) choice of whether
to ignore the command, proceeding to the next one in the queue, or to
stall the ITS command queue, processing nothing further. The
behaviour required when the read of the command packet from memory
fails is less clearly documented, but the same set of choices as for
command errors seem reasonable.
The intention of the QEMU implementation, as documented in the
comments, is that if we encounter a memory error reading the command
packet or one of the various data tables then we should stall, but
for command parameter errors we should ignore the queue and continue.
However, we don't actually do this. To get the desired behaviour,
the various process_* functions need to return true to cause
process_cmdq() to advance to the next command and keep processing,
and false to stall command processing. What they mostly do is return
false for any kind of error.
To make the code clearer, replace the 'bool' return from the process_
functions with an enum which may be either CMD_STALL or CMD_CONTINUE.
In this commit no behaviour changes; in subsequent commits we will
adjust the error-return paths for the process_ functions one by one.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220111171048.3545974-6-peter.maydell@linaro.org
Commit: 593a7cc2d38544040ed79c28b3b027420ec84c40
https://github.com/qemu/qemu/commit/593a7cc2d38544040ed79c28b3b027420ec84c40
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc/arm_gicv3_its: Fix return codes in process_its_cmd()
Fix process_its_cmd() to consistently return CMD_STALL for
memory errors and CMD_CONTINUE for parameter errors, as
we claim in the comments that we do.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220111171048.3545974-7-peter.maydell@linaro.org
Commit: be0ed8fb7fd4df3f6e09bb33c619e62a80410380
https://github.com/qemu/qemu/commit/be0ed8fb7fd4df3f6e09bb33c619e62a80410380
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc/arm_gicv3_its: Refactor process_its_cmd() to reduce nesting
Refactor process_its_cmd() so that it consistently uses
the structure
do thing;
if (error condition) {
return early;
}
do next thing;
rather than doing some of the work nested inside if (not error)
code blocks.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220111171048.3545974-8-peter.maydell@linaro.org
Commit: 0241f7316073f5e66b560195c36e719e369947d0
https://github.com/qemu/qemu/commit/0241f7316073f5e66b560195c36e719e369947d0
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc/arm_gicv3_its: Fix return codes in process_mapti()
Fix process_mapti() to consistently return CMD_STALL for memory
errors and CMD_CONTINUE for parameter errors, as we claim in the
comments that we do.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220111171048.3545974-9-peter.maydell@linaro.org
Commit: f66751961468813ba6a13de1510c448769b6979a
https://github.com/qemu/qemu/commit/f66751961468813ba6a13de1510c448769b6979a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc/arm_gicv3_its: Fix return codes in process_mapc()
Fix process_mapc() to consistently return CMD_STALL for memory
errors and CMD_CONTINUE for parameter errors, as we claim in the
comments that we do.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220111171048.3545974-10-peter.maydell@linaro.org
Commit: 00d46e72e97ddb5651f62b6eead658a431c58bc6
https://github.com/qemu/qemu/commit/00d46e72e97ddb5651f62b6eead658a431c58bc6
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc/arm_gicv3_its: Fix return codes in process_mapd()
Fix process_mapd() to consistently return CMD_STALL for memory
errors and CMD_CONTINUE for parameter errors, as we claim in the
comments that we do.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220111171048.3545974-11-peter.maydell@linaro.org
Commit: d050f80f8c9b4e535bf2f20d5a400c231e7a5838
https://github.com/qemu/qemu/commit/d050f80f8c9b4e535bf2f20d5a400c231e7a5838
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc/arm_gicv3_its: Factor out "find address of table entry" code
The ITS has several tables which all share a similar format,
described by the TableDesc struct: the guest may configure them
to be a single-level table or a two-level table. Currently we
open-code the process of finding the table entry in all the
functions which read or write the device table or the collection
table. Factor out the "get the address of the table entry"
logic into a new function, so that the code which needs to
read or write a table entry only needs to call table_entry_addr()
and then perform a suitable load or store to that address.
Note that the error handling is slightly complicated because
we want to handle two cases differently:
* failure to read the L1 table entry should end up causing
a command stall, like other kinds of DMA error
* an L1 table entry that says there is no L2 table for this
index (ie whose valid bit is 0) must result in us treating
the table entry as not-valid on read, and discarding
writes (this is mandated by the spec)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20220111171048.3545974-12-peter.maydell@linaro.org
Commit: b13148d91805143aba3e0b4441e760b9bea03b8c
https://github.com/qemu/qemu/commit/b13148d91805143aba3e0b4441e760b9bea03b8c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc/arm_gicv3_its: Check indexes before use, not after
In a few places in the ITS command handling functions, we were
doing the range-check of an event ID or device ID only after using
it as a table index; move the checks to before the uses.
This misordering wouldn't have very bad effects because the
tables are in guest memory anyway.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20220111171048.3545974-13-peter.maydell@linaro.org
Commit: 58b88779f00707b6231d827637b5a3d498f9fe28
https://github.com/qemu/qemu/commit/58b88779f00707b6231d827637b5a3d498f9fe28
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc/arm_gicv3_its: Range-check ICID before indexing into collection table
In process_its_cmd(), we read an ICID out of the interrupt table
entry, and then use it as an index into the collection table. Add a
check that it is within range for the collection table first.
This check is not strictly necessary, because:
* we range check the ICID from the guest before writing it into
the interrupt table entry, so the the only way to get an
out of range ICID in process_its_cmd() is if a badly-behaved
guest is writing directly to the interrupt table memory
* the collection table is in guest memory, so QEMU won't fall
over if we read off the end of it
However, it seems clearer to include the check.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20220111171048.3545974-14-peter.maydell@linaro.org
Commit: b9d383ab797f54ae5fa8746117770709921dc529
https://github.com/qemu/qemu/commit/b9d383ab797f54ae5fa8746117770709921dc529
Author: Philippe Mathieu-Daudé <philmd@redhat.com>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M hw/intc/arm_gicv3_redist.c
Log Message:
-----------
hw/intc/arm_gicv3: Check for !MEMTX_OK instead of MEMTX_ERROR
Quoting Peter Maydell:
"These MEMTX_* aren't from the memory transaction
API functions; they're just being used by gicd_readl() and
friends as a way to indicate a success/failure so that the
actual MemoryRegionOps read/write fns like gicv3_dist_read()
can log a guest error."
We are going to introduce more MemTxResult bits, so it is
safer to check for !MEMTX_OK rather than MEMTX_ERROR.
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2c89b5af5e72ab8c9d544c6e30399528b2238827
https://github.com/qemu/qemu/commit/2c89b5af5e72ab8c9d544c6e30399528b2238827
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-01-20 (Thu, 20 Jan 2022)
Changed paths:
M MAINTAINERS
R docs/can.txt
M docs/system/arm/cpu-features.rst
M docs/system/device-emulation.rst
A docs/system/devices/can.rst
M hw/acpi/aml-build.c
M hw/arm/Kconfig
M hw/arm/aspeed_ast2600.c
M hw/arm/musicpal.c
M hw/arm/npcm7xx_boards.c
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M hw/audio/Kconfig
M hw/intc/arm_gic.c
M hw/intc/arm_gicv3_its.c
M hw/intc/arm_gicv3_redist.c
A hw/misc/aspeed_i3c.c
M hw/misc/meson.build
M hw/misc/trace-events
M hw/net/meson.build
A hw/net/mv88w8618_eth.c
M hw/virtio/virtio-mem.c
M include/hw/arm/aspeed_soc.h
M include/hw/arm/virt.h
A include/hw/misc/aspeed_i3c.h
A include/hw/net/mv88w8618_eth.h
M qemu-options.hx
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/kvm64.c
M tests/data/acpi/virt/PPTT
Log Message:
-----------
Merge remote-tracking branch
'remotes/pmaydell/tags/pull-target-arm-20220120-1' into staging
target-arm:
* hw/intc/arm_gicv3_its: Fix various minor bugs
* hw/arm/aspeed: Add the i3c device to the AST2600 SoC
* hw/arm: kudo: add lm75s behind bus 1 switch at 75
* hw/arm/virt: Fix support for running guests on hosts
with restricted IPA ranges
* hw/intc/arm_gic: Allow reset of the running priority
* hw/intc/arm_gic: Implement read of GICC_IIDR
* hw/arm/virt: Support for virtio-mem-pci
* hw/arm/virt: Support CPU cluster on ARM virt machine
* docs/can: convert to restructuredText
* hw/net: Move MV88W8618 network device out of hw/arm/ directory
* hw/arm/virt: KVM: Enable PAuth when supported by the host
# gpg: Signature made Thu 20 Jan 2022 16:12:12 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20220120-1: (38 commits)
hw/intc/arm_gicv3: Check for !MEMTX_OK instead of MEMTX_ERROR
hw/intc/arm_gicv3_its: Range-check ICID before indexing into collection table
hw/intc/arm_gicv3_its: Check indexes before use, not after
hw/intc/arm_gicv3_its: Factor out "find address of table entry" code
hw/intc/arm_gicv3_its: Fix return codes in process_mapd()
hw/intc/arm_gicv3_its: Fix return codes in process_mapc()
hw/intc/arm_gicv3_its: Fix return codes in process_mapti()
hw/intc/arm_gicv3_its: Refactor process_its_cmd() to reduce nesting
hw/intc/arm_gicv3_its: Fix return codes in process_its_cmd()
hw/intc/arm_gicv3_its: Use enum for return value of process_* functions
hw/intc/arm_gicv3_its: Don't use data if reading command failed
hw/intc/arm_gicv3_its: Fix handling of process_its_cmd() return value
hw/intc/arm_gicv3_its: Convert int ID check to num_intids convention
hw/intc/arm_gicv3_its: Fix event ID bounds checks
hw/arm/aspeed: Add the i3c device to the AST2600 SoC
hw/misc/aspeed_i3c.c: Introduce a dummy AST2600 I3C model.
hw/arm: kudo add lm75s behind bus 1 switch at 75
hw/arm/virt: Drop superfluous checks against highmem
hw/arm/virt: Disable highmem devices that don't fit in the PA range
hw/arm/virt: Use the PA range to compute the memory map
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/47fa1ad5349b...2c89b5af5e72