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[Qemu-commits] [qemu/qemu] 0fbb5d: target/riscv/pmp: fix no pmp illegal
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 0fbb5d: target/riscv/pmp: fix no pmp illegal intrs |
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Date: |
Sat, 08 Jan 2022 09:37:30 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 0fbb5d2d3c9ded9fbd3f6f993974cc5e88e28912
https://github.com/qemu/qemu/commit/0fbb5d2d3c9ded9fbd3f6f993974cc5e88e28912
Author: Nikita Shubin <n.shubin@yadro.com>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv/pmp: fix no pmp illegal intrs
As per the privilege specification, any access from S/U mode should fail
if no pmp region is configured and pmp is present, othwerwise access
should succeed.
Fixes: d102f19a208 (target/riscv/pmp: Raise exception if no PMP entry is
configured)
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211214092659.15709-1-nikita.shubin@maquefel.me
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 6fd3f397cad0867feec484a13f2656dbf736c76c
https://github.com/qemu/qemu/commit/6fd3f397cad0867feec484a13f2656dbf736c76c
Author: Jim Shu <jim.shu@sifive.com>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M hw/dma/sifive_pdma.c
Log Message:
-----------
hw/dma: sifive_pdma: support high 32-bit access of 64-bit register
Real PDMA supports high 32-bit read/write memory access of 64-bit
register.
The following result is PDMA tested in U-Boot on Unmatched board:
1. Real PDMA allows high 32-bit read/write to 64-bit register.
=> mw.l 0x3000000 0x0 <= Disclaim channel 0
=> mw.l 0x3000000 0x1 <= Claim channel 0
=> mw.l 0x3000010 0x80000000 <= Write low 32-bit NextDest
(NextDest = 0x280000000)
=> mw.l 0x3000014 0x2 <= Write high 32-bit NextDest
=> md.l 0x3000010 1 <= Dump low 32-bit NextDest
03000010: 80000000
=> md.l 0x3000014 1 <= Dump high 32-bit NextDest
03000014: 00000002
=> mw.l 0x3000018 0x80001000 <= Write low 32-bit NextSrc (NextSrc
= 0x280001000)
=> mw.l 0x300001c 0x2 <= Write high 32-bit NextSrc
=> md.l 0x3000018 1 <= Dump low 32-bit NextSrc
03000010: 80001000
=> md.l 0x300001c 1 <= Dump high 32-bit NextSrc
03000014: 00000002
2. PDMA transfer from 0x280001000 to 0x280000000 is OK.
=> mw.q 0x3000008 0x4 <= NextBytes = 4
=> mw.l 0x3000004 0x22000000 <= wsize = rsize = 2 (2^2 = 4 bytes)
=> mw.l 0x280000000 0x87654321 <= Fill test data to dst
=> mw.l 0x280001000 0x12345678 <= Fill test data to src
=> md.l 0x280000000 1; md.l 0x280001000 1 <= Dump src/dst memory contents
280000000: 87654321 !Ce.
280001000: 12345678 xV4.
=> md.l 0x3000000 8 <= Dump PDMA status
03000000: 00000001 22000000 00000004 00000000 ......."........
03000010: 80000000 00000002 80001000 00000002 ................
=> mw.l 0x3000000 0x3 <= Set channel 0 run and claim bits
=> md.l 0x3000000 8 <= Dump PDMA status
03000000: 40000001 22000000 00000004 00000000 ...@..."........
03000010: 80000000 00000002 80001000 00000002 ................
=> md.l 0x280000000 1; md.l 0x280001000 1 <= Dump src/dst memory contents
280000000: 12345678 xV4.
280001000: 12345678 xV4.
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20220104063408.658169-2-jim.shu@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e6b0408a1728c001a0cc0568b9daae5f92e239ee
https://github.com/qemu/qemu/commit/e6b0408a1728c001a0cc0568b9daae5f92e239ee
Author: Jim Shu <jim.shu@sifive.com>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M hw/dma/sifive_pdma.c
Log Message:
-----------
hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers
It's obvious that PDMA supports 64-bit access of 64-bit registers, and
in previous commit, we confirm that PDMA supports 32-bit access of
both 32/64-bit registers. Thus, we configure 32/64-bit memory access
of PDMA registers as valid in general.
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20220104063408.658169-3-jim.shu@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 83b92b8efca6634406361d62dbf9d3e8369a2a20
https://github.com/qemu/qemu/commit/83b92b8efca6634406361d62dbf9d3e8369a2a20
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M hw/intc/sifive_plic.c
Log Message:
-----------
hw/intc: sifive_plic: Add a reset function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220105213937.1113508-2-alistair.francis@opensource.wdc.com>
Commit: fb926d57cc56499523f1559f58371e09198ed75e
https://github.com/qemu/qemu/commit/fb926d57cc56499523f1559f58371e09198ed75e
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M hw/intc/sifive_plic.c
Log Message:
-----------
hw/intc: sifive_plic: Cleanup the write function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220105213937.1113508-3-alistair.francis@opensource.wdc.com>
Commit: b79e1c76c02dd01a203028c4482d975480b97f16
https://github.com/qemu/qemu/commit/b79e1c76c02dd01a203028c4482d975480b97f16
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M hw/intc/sifive_plic.c
Log Message:
-----------
hw/intc: sifive_plic: Cleanup the read function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220105213937.1113508-4-alistair.francis@opensource.wdc.com>
Commit: 41bcc44a2517b5775a94c5c9b2a1014be8b19235
https://github.com/qemu/qemu/commit/41bcc44a2517b5775a94c5c9b2a1014be8b19235
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M hw/intc/sifive_plic.c
Log Message:
-----------
hw/intc: sifive_plic: Cleanup remaining functions
We can remove the original sifive_plic_irqs_pending() function and
instead just use the sifive_plic_claim() function (renamed to
sifive_plic_claimed()) to determine if any interrupts are pending.
This requires move the side effects outside of sifive_plic_claimed(),
but as they are only invoked once that isn't a problem.
We have also removed all of the old #ifdef debugging logs, so let's
cleanup the last remaining debug function while we are here.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220105213937.1113508-5-alistair.francis@opensource.wdc.com>
Commit: 6ca7155a8c8d88e5372f0ba337c33e86edbcb295
https://github.com/qemu/qemu/commit/6ca7155a8c8d88e5372f0ba337c33e86edbcb295
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Mark the Hypervisor extension as non experimental
The Hypervisor spec is now frozen, so remove the experimental tag.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220105213937.1113508-6-alistair.francis@opensource.wdc.com>
Commit: 07cb270a9ac914431577321b0e3e99d79cf56254
https://github.com/qemu/qemu/commit/07cb270a9ac914431577321b0e3e99d79cf56254
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Enable the Hypervisor extension by default
Let's enable the Hypervisor extension by default. This doesn't affect
named CPUs (such as lowrisc-ibex or sifive-u54) but does enable the
Hypervisor extensions by default for the virt machine.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220105213937.1113508-7-alistair.francis@opensource.wdc.com>
Commit: 8f972e5b4beeeb35b15f75499d18a8cc5a320ce7
https://github.com/qemu/qemu/commit/8f972e5b4beeeb35b15f75499d18a8cc5a320ce7
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M hw/riscv/microchip_pfsoc.c
M hw/riscv/opentitan.c
M hw/riscv/sifive_e.c
M hw/riscv/sifive_u.c
Log Message:
-----------
hw/riscv: Use error_fatal for SoC realisation
When realising the SoC use error_fatal instead of error_abort as the
process can fail and report useful information to the user.
Currently a user can see this:
$ ../qemu/bld/qemu-system-riscv64 -M sifive_u -S -monitor stdio -display
none -drive if=pflash
QEMU 6.1.93 monitor - type 'help' for more information
(qemu) Unexpected error in sifive_u_otp_realize() at
../hw/misc/sifive_u_otp.c:229:
qemu-system-riscv64: OTP drive size < 16K
Aborted (core dumped)
Which this patch addresses
Reported-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220105213937.1113508-8-alistair.francis@opensource.wdc.com>
Commit: d4452c692488228e6dce193f4f98ac762588d96a
https://github.com/qemu/qemu/commit/d4452c692488228e6dce193f4f98ac762588d96a
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M include/hw/riscv/virt.h
Log Message:
-----------
hw/riscv: virt: Allow support for 32 cores
Linux supports up to 32 cores for both 32-bit and 64-bit RISC-V, so
let's set that as the maximum for the virt board.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/435
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220105213937.1113508-9-alistair.francis@opensource.wdc.com>
Commit: b3e0204968d4e5cc556aa5e09078dedbd1eee4a3
https://github.com/qemu/qemu/commit/b3e0204968d4e5cc556aa5e09078dedbd1eee4a3
Author: Bin Meng <bmeng.cn@gmail.com>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
M pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
M pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
M pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
M roms/opensbi
Log Message:
-----------
roms/opensbi: Upgrade from v0.9 to v1.0
Upgrade OpenSBI from v0.9 to v1.0 and the pre-built bios images.
The v1.0 release includes the following commits:
ec5274b platform: implement K210 system reset
5487cf0 include: sbi: Simplify HSM state define names
8df1f9a lib: sbi: Use SBI_HSM_STATE_xyz defines instead of SBI_STATE_xyz defines
7c867fd lib: sbi: Rename sbi_hsm_hart_started_mask() function
638c948 lib: sbi: Remove redundant sbi_hsm_hart_started() function
ca864a9 lib: sbi: Fix error codes returned by HSM start() and stop() functions
6290a22 include: sbi: Add HSM suspend related defines
4b05df6 lib: sbi: Add sbi_hart_reinit() function
807d71c include: sbi: Add hart_suspend() platform callback
7475689 lib: sbi: Implement SBI HSM suspend function
b9cf617 include: sbi: Upgrade SBI implementation version to v0.3
50d4fde lib: Remove redundant sbi_platform_ipi_clear() calls
ff5bd94 include: sbi: SBI function IDs for RFENCE extension
22d8ee9 firmware: Use lla to access all global symbols
0f20e8a firmware: Support position independent execution
ddad02d lib: sbi: illegal CSR 0x306 access in hpm_allowed()
bfc85c7 include: headers: Replace __ASSEMBLY__ with __ASSEMBLER__
9190ad1 lib/utils: Support the official clint DT bindings
ca3f358 lib/utils: Drop the 'compat' parameter of fdt_plic_fixup()
4edc822 lib/utils: Support fixing up the official DT bindings of PLIC
4ef2f5d firware: optimize the exception exit code
3d8a952 lib: fix csr detect support
e71a7c1 firmware: Remove redundant add instruction from trap restore path
d4a94ea include: types: Add __aligned(x) to define the minimum alignement
d0e406f include: sbi: Allow direct initialization via SPIN_LOCK_INIT()
4d8e2f1 lib: sbi: Replace test-and-set locks by ticket locks
70ffc3e lib: sbi: fix atomic_add_return
27a16b1 docs: fix link to OpenPiton documentation
b1df1ac lib: sbi: Domains can be registered only before finalizing domains
7495bce lib: sbi: Add sbi_domain_memregion_init() API
4dc0001 lib: sbi: Add sbi_domain_root_add_memregion() API
8b56980 lib: utils/sys: Add CLINT memregion in the root domain
fc37c97 lib: sbi: Make the root domain instance global variable
e7e4bcd lib: utils: Copy over restricted root domain memregions to FDT domains
f41196a lib: sbi: Make sbi_domain_memregion_initfw() a local function
c5d0645 lib: utils: Implement "64bit-mmio" property parsing
49e422c lib: utils: reset: Add T-HEAD sample platform reset driver
0d56293 lib: sbi: Fix sbi_domain_root_add_memregion() for merging memregions
bf3ef53 firmware: Enable FW_PIC by default
1db8436 platform: Remove platform/thead
6d1642f docs: generic: Add T-HEAD C9xx series processors
a3689db lib: sbi: Remove domains_root_regions() platform callback
068ca08 lib: sbi: Simplify console platform operations
559a8f1 lib: sbi: Simplify timer platform operations
dc39c7b lib: sbi: Simplify ipi platform operations
043d088 lib: sbi: Simplify system reset platform operations
a84a1dd lib: sbi: Simplify HSM platform operations
e9a27ab lib: sbi: Show devices provided by platform in boot prints
632e27b docs/platform: sifive_fu540: Update U-Boot defconfig name
117fb6d lib: utils/serial: Add support for Gaisler APBUART
552f53f docs: platform: Sort platform names
d4177e7 docs: platform: Describe sifive_fu540 as supported generic platform
26998f3 platform: Remove sifive/fu540 platform
f90c4c2 lib: sbi: Have spinlock checks return bool
e822b75 lib: utils/serial: Support Synopsys DesignWare APB UART
6139ab2 Makefile: unconditionally disable SSP
c9ef2bc lib: utils: Add strncpy macro to libfdt_env.h
ee7c2b2 lib: utils/fdt: Don't use sbi_string functions
fe92347 lib: utils/fdt: Replace strcmp with strncmp
b2dbbc0 lib: Check region base for merging in sbi_domain_root_add_memregion()
54d7def lib: utils: Try other FDT drivers when we see SBI_ENODEV
d9ba653 docs: debugging OpenSBI
66c4fca lib: utils: consider ':' in stdout-path
f30b189 lib: sbi_scratch: remove owner from sbi_scratch_alloc_offset
a03ea2e platform: andes/ae350: Cosmetic fixes in plicsw.c
b32fac4 docs/platform: andes-ae350: Fix missing spaces
de446cc platform: andes/ae350: Drop plicsw_get_pending()
434198e platform: andes/ae350: Drop plicsw_ipi_sync()
1da3d80 lib: sbi_scratch: zero out scratch memory on all harts
360ab88 lib: utils: missing initialization in thead_reset_init
79f9b42 lib: sbi: Fix GET_F64_REG inline assembly
eb90e0a lib: utils/libfdt: Upgrade to v1.6.1 release
cdcf907 lib: sign conflict in sbi_tlb_entry_process()
9901794 lib: sign conflict in wake_coldboot_harts()
11c345f lib: simplify sbi_fifo_inplace_update()
4519e29 lib: utils/timer: Add ACLINT MTIMER library
5a049fe lib: utils/ipi: Add ACLINT MSWI library
bd5d208 lib: utils: Add FDT parsing API common for both ACLINT and CLINT
56fc5f7 lib: utils/ipi: Add FDT based ACLINT MSWI IPI driver
03d6bb5 lib: utils/timer: Add FDT based ACLINT MTIMER driver
a731c7e platform: Replace CLINT library usage with ACLINT library
b7f2cd2 lib: utils: reset: unify naming of 'sifive_test' device
197e089 docs/platform: thead-c9xx: Remove FW_PIC=y
17e23b6 platform: generic: Terminate platform.name with null
3e8b31a docs: Add device tree bindings for SBI PMU extension
fde28fa lib: sbi: Detect mcountinihibit support at runtime
d3a96cc lib: sbi: Remove stray '\' character
0829f2b lib: sbi: Detect number of bits implemented in mhpmcounter
9c9b4ad lib: sbi: Disable m/scounteren & enable mcountinhibit
41ae63c include: Add a list empty check function
fd9116b lib: sbi: Remove redundant boot time print statement
49966db lib: sbi: Use csr_read/write_num to read/update PMU counters
e7cc7a3 lib: sbi: Add PMU specific platform hooks
13d40f2 lib: sbi: Add PMU support
ae72ec0 utils: fdt: Add fdt helper functions to parse PMU DT nodes
37f9b0f lib: sbi: Implement SBI PMU extension
764a17d lib: sbi: Implement firmware counters
ec1b8bb lib: sbi: Improve TLB function naming
0e12aa8 platform: generic: Add PMU support
14c7f71 firmware: Minor optimization in _scratch_init()
dafaa0f docs: Correct a typo in platform_guide.md
abfce9b docs: Make <xyz> visible in the rendered platform guide
dcb756b firmware: Remove the sanity checks in fw_save_info()
b88b366 firmware: Define a macro for version of struct fw_dynamic_info
a76ac44 lib: sbi: Fix sbi_pmu_exit() for systems not having MCOUNTINHIBIT csr
7f1be8a fw_base: Don't mark fw_platform_init as both global and weak
397afe5 fw_base: Put data in .data rather than .text
a3d328a firmware: Explicitly pass -pie to the linker, not just the driver
09ad811 firmware: Only default FW_PIC to y if supported
2942777 Makefile: Support building with Clang and LLVM binutils
17729d4 lib: utils: Drop dependency on libgcc by importing part of FreeBSD's
libquad
e931f38 lib: utils/fdt: Add fdt_parse_phandle_with_args() API
36b8eff lib: utils/gpio: Add generic GPIO configuration library
c14f1fe lib: utils/gpio: Add simple FDT based GPIO framework
4c3df2a lib: utils/gpio: Add minimal SiFive GPIO driver
e3d6919 lib: utils/reset: Add generic GPIO reset driver
7210e90 firmware: use __SIZEOF_LONG__ for field offsets in fw_dynamic.h
f3a8f60 include: types: Use __builtin_offsetof when supported
8a1475b firmware: Remove the unhelpful alignment codes before fdt relocation
a4555e5 docs: Document parameters passed to firmware and alignment requirement
2c74dc3 docs: Document FW_PIC compile time option
81eb708 README: Update toolchain information
9890391 Makefile: Manually forward RELAX_FLAG to the assembler when linking
with LLD
74db0ac firmware: use _fw_start for load address
217d5e4 generic: fu740: add workaround for CIP-1200 errata
ce03c88 lib: utils: remove unused variable in fdt_reset_init
e928472 lib: utils: support both of gpio-poweroff, gpio-reset
d244f3d lib: sbi: Fix bug in strncmp function when count is 0
47a4765 lib: utils/fdt: Change addr and size to uint64_t
e0d1b9d lib: utils/timer: Allow separate base addresses for MTIME and MTIMECMP
7a3a0cc lib: utils: Extend fdt_get_node_addr_size() for multiple register sets
f3a0eb8 lib: utils/fdt: Extend fdt_parse_aclint_node() function
b35f782 lib: utils/timer: Allow ACLINT MTIMER supporting only 32-bit MMIO
7aa6c9a lib: utils/timer: Simplify MTIMER synchronization
33eac76 lib: sbi: Fix bug in sbi_ecall_rfence that misses checking
ee27437 lib: sbi_trap: Restore redirect for access faults
b1d3e91 payloads/test: Add support for SBI v0.2 ecalls
bd316e2 lib: sbi: Correct typo in faults delegation CSR name
c262306 lib: sbi: protect dprintf output with spinlock
1718b16 lib: sbi: Checking fifo validness in sbi_fifo_is_empty and is_full
bd35521 lib: sbi: Refine the way to construct platform features
0274a96 lib: utils/reset: Sort fdt_reset driver list
395ff7e lib: utils/reset: Add a sunxi watchdog reset driver
3477f08 lib: sbi: fix ctz bug
12753d2 lib: sbi: add some macros to detect BUG at runtime
51113fe lib: sbi: Add BUG() macro for csr_read/write_num() and misa_string()
72154f4 lib: utils/fdt: Add fdt_parse_timebase_frequency() function
12e7af9 lib: sbi: Add timer frequency to struct sbi_timer_device
6355155 lib: sbi: Print timer frequency at boot time
9d0ab35 lib: sbi: Add generic timer delay loop function
fa59dd3 lib: utils/reset: use sbi_timer_mdelay() in gpio reset driver
754d511 lib: utils: identify supported GPIO reset methods
516161c lib: sbi: convert reset to list
9283d50 lib: sbi: add priority for reset handler
c38973e lib: sbi: Save context for all non-retentive suspend types
67cbbcb lib: sbi: system reset with invalid parameters
422eda4 Makefile: Add build time and compiler info string
78c2b19 lib: utils/irqchip: Automatically delegate T-HEAD PLIC access
309e8bd lib: utils/reset: Register separate GPIO system reset devices
723aa88 lib: sbi: Refine addr format in sbi_printf
c891acc include: sbi_utils: Introduce an helper to get fdt base address
013ba4e lib: sbi: Fix GPA passed to __sbi_hfence_gvma_xyz() functions
0979ffd lib: utils/gpio: use list for drivers
2fe2f55 lib: sbi: move sbi_boot_print_general()
57f094e platform: generic: move fdt_reset_init to final_init
be245ac lib: sbi: error handling in fdt_reset_init()
a74daf2 riscv: Add new CSRs introduced by Sscofpmf[1] extension
7084ad9 lib: sbi: Update csr_read/write_num for PMU
867c653 lib: sbi: Detect Sscofpmf extension at run time
9134c36 lib: sbi: Delegate PMU counter overflow interrupt to S mode
730f01b lib: sbi: Support sscofpmf extension in OpenSBI
2363f95 lib: sbi: Always enable access for all counters
0c304b6 lib: sbi: Allow programmable counters to monitor cycle/instret events
1e14732 lib: sbi: Reset the mhpmevent value upon counter reset
b628cfd lib: sbi: Counter info width should be zero indexed
b28f070 lib: sbi: Enable PMU extension for platforms without mcountinhibit
15906a3 lib: utils: Rename the prefix in PMU DT properties
b8845e4 lib: sbi: Fix initial value mask while updating the counters
31fe5a7 lib: sbi: Fix PMP address bits detection
94eba23 lib: utils/reset: add priority to gpio reset
1d462e0 lib: utils/reset: separate driver init func
2c964a2 lib: utils/i2c: Add generic I2C configuration library
6ca6bca lib: utils/i2c: Add simple FDT based I2C framework
13a1158 lib: utils/i2c: Add minimal SiFive I2C driver
f374496 platform: sifive_fu740: add platform reset driver
d335a17 lib: sbi: clear pmpcfg.A before setting in pmp_set()
52af6e4 lib: utils: Add LiteX UART support
22d556d lib: sbi: Fix spelling of "address" in sbi_domain.c
7a22c78 lib: sbi: Fix missing space
7e77706 lib: sbi: Resolve the uninitialized complaint in sbi_pmu
14faee6 lib: sbi: Improve fatal error handling
2428987 lib: pmu: support the event ID encoded by a bitmap.
66fbcc0 docs/platform: spike: Enhance Spike examples
460041c lib: pmu: check SSCOF before masking
69d7e53 Makefile: Fix -msave-restore compile warning with CLANG-10 (or lower)
d249d65 lib: sbi: Fix compile errors using -Os option
f270359 Makefile: Improve the method to disable -m(no-)save-restore option
2082153 lib: sbi: simplify pmp_set(), pmp_get()
d30bde3 firmware: Move memcpy/memset mapping to fw_base.S
48f91ee include: Bump-up version to 1.0
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 629ccdaa4e43c39d38d67b5ba1cec2bbedb6104d
https://github.com/qemu/qemu/commit/629ccdaa4e43c39d38d67b5ba1cec2bbedb6104d
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening
fp insns
Vector widening floating-point instructions should use
require_scale_rvf() instead of require_rvf() to check whether RVF/RVD is
enabled.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220105022247.21131-2-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 91cade44cd49e23114c3101ef22d8a0b370523ae
https://github.com/qemu/qemu/commit/91cade44cd49e23114c3101ef22d8a0b370523ae
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening
fp/int type-convert insns
vfwcvt.xu.f.v, vfwcvt.x.f.v, vfwcvt.rtz.xu.f.v and vfwcvt.rtz.x.f.v
convert single-width floating-point to double-width integer.
Therefore, should use require_rvf() to check whether RVF/RVD is enabled.
vfwcvt.f.xu.v, vfwcvt.f.x.v convert single-width integer to double-width
floating-point, and vfwcvt.f.f.v convert double-width floating-point to
single-width floating-point. Therefore, should use require_scale_rvf() to
check whether RVF/RVD is enabled.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220105022247.21131-3-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 79e6176ea09c7615966d3ed05be0d40dc9de249f
https://github.com/qemu/qemu/commit/79e6176ea09c7615966d3ed05be0d40dc9de249f
Author: Frank Chang <frank.chang@sifive.com>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing
fp/int type-convert insns
vfncvt.f.xu.w, vfncvt.f.x.w convert double-width integer to single-width
floating-point. Therefore, should use require_rvf() to check whether
RVF/RVD is enabled.
vfncvt.f.f.w, vfncvt.rod.f.f.w convert double-width floating-point to
single-width integer. Therefore, should use require_scale_rvf() to check
whether RVF/RVD is enabled.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220105022247.21131-4-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: dfdb46a3765bdab40a0b36722b4828d52ea8de96
https://github.com/qemu/qemu/commit/dfdb46a3765bdab40a0b36722b4828d52ea8de96
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Fix position of 'experimental' comment
When commit 0643c12e4b dropped the 'x-' prefix for Zb[abcs] and set
them to be enabled by default, the comment about experimental
extensions was kept in place above them. This moves it down a few
lines to only cover experimental extensions.
References: 0643c12e4b ("target/riscv: Enable bitmanip Zb[abcs] instructions")
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106134020.1628889-1-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fc313c64345453c7a668d765610dfd7135e21a98
https://github.com/qemu/qemu/commit/fc313c64345453c7a668d765610dfd7135e21a98
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/ldst_common.c.inc
M accel/tcg/user-exec.c
M include/exec/memop.h
M include/tcg/tcg-op.h
M target/alpha/translate.c
M target/arm/helper-a64.c
M target/arm/translate-a32.h
M target/arm/translate-a64.c
M target/arm/translate-neon.c
M target/arm/translate-sve.c
M target/arm/translate-vfp.c
M target/arm/translate.c
M target/cris/translate.c
M target/hppa/translate.c
M target/i386/tcg/mem_helper.c
M target/i386/tcg/translate.c
M target/m68k/op_helper.c
M target/mips/tcg/micromips_translate.c.inc
M target/mips/tcg/translate.c
M target/mips/tcg/tx79_translate.c
M target/ppc/translate.c
M target/ppc/translate/fixedpoint-impl.c.inc
M target/ppc/translate/fp-impl.c.inc
M target/ppc/translate/vsx-impl.c.inc
M target/riscv/insn_trans/trans_rva.c.inc
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvh.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/s390x/tcg/insn-data.def
M target/s390x/tcg/mem_helper.c
M target/s390x/tcg/translate.c
M target/s390x/tcg/translate_vx.c.inc
M target/sh4/translate.c
M target/sparc/translate.c
M target/tricore/translate.c
M target/xtensa/translate.c
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci.c
Log Message:
-----------
exec/memop: Adding signedness to quad definitions
Renaming defines for quad in their various forms so that their signedness is
now explicit.
Done using git grep as suggested by Philippe, with a bit of hand edition to
keep assignments aligned.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c7f9dd546510a27c77e8e90e4fb527bf830853fb
https://github.com/qemu/qemu/commit/c7f9dd546510a27c77e8e90e4fb527bf830853fb
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M include/exec/memop.h
Log Message:
-----------
exec/memop: Adding signed quad and octo defines
Adding defines to handle signed 64-bit and unsigned 128-bit quantities in
memory accesses.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-3-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e9d07601f6c412ef03e00b03d13ae22488be0bbe
https://github.com/qemu/qemu/commit/e9d07601f6c412ef03e00b03d13ae22488be0bbe
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M include/qemu/int128.h
A util/int128.c
M util/meson.build
Log Message:
-----------
qemu/int128: addition of div/rem 128-bit operations
Addition of div and rem on 128-bit integers, using the 128/64->128 divu and
64x64->128 mulu in host-utils.
These operations will be used within div/rem helpers in the 128-bit riscv
target.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-4-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 344b4a82fc165798546dbf276c7b281899c177a0
https://github.com/qemu/qemu/commit/344b4a82fc165798546dbf276c7b281899c177a0
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/translate.c
Log Message:
-----------
target/riscv: additional macros to check instruction support
Given that the 128-bit version of the riscv spec adds new instructions, and
that some instructions that were previously only available in 64-bit mode
are now available for both 64-bit and 128-bit, we added new macros to check
for the processor mode during translation.
Although RV128 is a superset of RV64, we keep for now the RV64 only tests
for extensions other than RVI and RVM.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-5-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a1a3aac448cced3161cd0c8a49ac24cd5d58fe14
https://github.com/qemu/qemu/commit/a1a3aac448cced3161cd0c8a49ac24cd5d58fe14
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: separation of bitwise logic and arithmetic helpers
Introduction of a gen_logic function for bitwise logic to implement
instructions in which no propagation of information occurs between bits and
use of this function on the bitwise instructions.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-6-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2b5470843a6bf10bcc4431d81badec6bfe31f0a7
https://github.com/qemu/qemu/commit/2b5470843a6bf10bcc4431d81badec6bfe31f0a7
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/machine.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: array for the 64 upper bits of 128-bit registers
The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-7-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 332dab68785bba0381790fef94f4f433e8e806ea
https://github.com/qemu/qemu/commit/332dab68785bba0381790fef94f4f433e8e806ea
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M disas/riscv.c
M include/disas/dis-asm.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/gdbstub.c
Log Message:
-----------
target/riscv: setup everything for rv64 to support rv128 execution
This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
executables.
Still, there is no support for 128-bit insns at that stage so qemu fails
miserably (as expected) if launched with this option.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-8-frederic.petrot@univ-grenoble-alpes.fr
[ Changed by AF
- Rename CPU to "x-rv128"
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 76a361066f9a02b4dc587c0c62481f2ef8fbe524
https://github.com/qemu/qemu/commit/76a361066f9a02b4dc587c0c62481f2ef8fbe524
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvi.c.inc
Log Message:
-----------
target/riscv: moving some insns close to similar insns
lwu and ld are functionally close to the other loads, but were after the
stores in the source file.
Similarly, xor was away from or and and by two arithmetic functions, while
the immediate versions were nicely put together.
This patch moves the aforementioned loads after lhu, and xor above or,
where they more logically belong.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-9-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a2f827ff4f4486b8aa8fce180452463ec2b62f53
https://github.com/qemu/qemu/commit/a2f827ff4f4486b8aa8fce180452463ec2b62f53
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/insn16.decode
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: accessors to registers upper part and 128-bit load/store
Get function to retrieve the 64 top bits of a register, stored in the gprh
field of the cpu state. Set function that writes the 128-bit value at once.
The access to the gprh field can not be protected at compile time to make
sure it is accessed only in the 128-bit version of the processor because we
have no way to indicate that the misa_mxl_max field is const.
The 128-bit ISA adds ldu, lq and sq. We provide support for these
instructions. Note that (a) we compute only 64-bit addresses to actually
access memory, cowardly utilizing the existing address translation mechanism
of QEMU, and (b) we assume for now little-endian memory accesses.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-10-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 568f247f69f9297a7a8816f46ce74a265a96ca8d
https://github.com/qemu/qemu/commit/568f247f69f9297a7a8816f46ce74a265a96ca8d
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/translate.c
Log Message:
-----------
target/riscv: support for 128-bit bitwise instructions
The 128-bit bitwise instructions do not need any function prototype change
as the functions can be applied independently on the lower and upper part of
the registers.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-11-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 57c108b86461a050a58b1ca9d31fd6e4af32205c
https://github.com/qemu/qemu/commit/57c108b86461a050a58b1ca9d31fd6e4af32205c
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: support for 128-bit U-type instructions
Adding the 128-bit version of lui and auipc, and introducing to that end
a "set register with immediat" function to handle extension on 128 bits.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-12-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 6bf4bbed205127f3805e960a1213c2289db89114
https://github.com/qemu/qemu/commit/6bf4bbed205127f3805e960a1213c2289db89114
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: support for 128-bit shift instructions
Handling shifts for 32, 64 and 128 operation length for RV128, following the
general framework for handling various olens proposed by Richard.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-13-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7fd40f8679ceed388d82902e9be05ae136cf09cd
https://github.com/qemu/qemu/commit/7fd40f8679ceed388d82902e9be05ae136cf09cd
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvm.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: support for 128-bit arithmetic instructions
Addition of 128-bit adds and subs in their various sizes,
"set if less than"s and branches.
Refactored the code to have a comparison function used for both stls and
branches.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-14-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b3a5d1fbebab2098d0c3cdd3732c25f5cfbe5cbc
https://github.com/qemu/qemu/commit/b3a5d1fbebab2098d0c3cdd3732c25f5cfbe5cbc
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/cpu.h
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvm.c.inc
A target/riscv/m128_helper.c
M target/riscv/meson.build
Log Message:
-----------
target/riscv: support for 128-bit M extension
Mult are generated inline (using a cool trick pointed out by Richard), but
for div and rem, given the complexity of the implementation of these
instructions, we call helpers to produce their behavior. From an
implementation standpoint, the helpers return the low part of the results,
while the high part is temporarily stored in a dedicated field of cpu_env
that is used to update the architectural register in the generation wrapper.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-15-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2c64ab66c1cdb409ead121357b3e92f8f1800c03
https://github.com/qemu/qemu/commit/2c64ab66c1cdb409ead121357b3e92f8f1800c03
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/cpu.h
M target/riscv/machine.c
Log Message:
-----------
target/riscv: adding high part of some csrs
Adding the high part of a very minimal set of csr.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-16-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 961738ffea964daad464389b3f06dd5b245fdf3c
https://github.com/qemu/qemu/commit/961738ffea964daad464389b3f06dd5b245fdf3c
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/cpu.h
M target/riscv/csr.c
M target/riscv/helper.h
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: helper functions to wrap calls to 128-bit csr insns
Given the side effects they have, the csr instructions are realized as
helpers. We extend this existing infrastructure for 128-bit sized csr.
We return 128-bit values using the same approach as for div/rem.
Theses helpers all call a unique function that is currently a fallback
on the 64-bit version.
The trans_csrxx functions supporting 128-bit are yet to be implemented.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-17-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7934fdeee75c8d8ca02a396afc549e3f54303859
https://github.com/qemu/qemu/commit/7934fdeee75c8d8ca02a396afc549e3f54303859
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/insn_trans/trans_rvi.c.inc
Log Message:
-----------
target/riscv: modification of the trans_csrxx for 128-bit support
As opposed to the gen_arith and gen_shift generation helpers, the csr insns
do not have a common prototype, so the choice to generate 32/64 or 128-bit
helper calls is done in the trans_csrxx functions.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-18-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 457c360f9c72f86ac6dd57f46a016dd361aaf3f7
https://github.com/qemu/qemu/commit/457c360f9c72f86ac6dd57f46a016dd361aaf3f7
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: actual functions to realize crs 128-bit insns
The csrs are accessed through function pointers: we add 128-bit read
operations in the table for three csrs (writes fallback to the
64-bit version as the upper 64-bit information is handled elsewhere):
- misa, as mxl is needed for proper operation,
- mstatus and sstatus, to return sd
In addition, we also add read and write accesses to the machine and
supervisor scratch registers.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-19-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ea7b5d5af6c3f994b10caa80c7f41964678eb2bb
https://github.com/qemu/qemu/commit/ea7b5d5af6c3f994b10caa80c7f41964678eb2bb
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Set the opcode in DisasContext
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211220064916.107241-2-alistair.francis@opensource.wdc.com
Commit: 86d0c457396b1a789fe2740f7bd8d476ea426298
https://github.com/qemu/qemu/commit/86d0c457396b1a789fe2740f7bd8d476ea426298
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Fixup setting GVA
In preparation for adding support for the illegal instruction address
let's fixup the Hypervisor extension setting GVA logic and improve the
variable names.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211220064916.107241-3-alistair.francis@opensource.wdc.com
Commit: 48eaeb56debf91817dea00a2cd9c1f6c986eb531
https://github.com/qemu/qemu/commit/48eaeb56debf91817dea00a2cd9c1f6c986eb531
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2022-01-08 (Sat, 08 Jan 2022)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Implement the stval/mtval illegal instruction
The stval and mtval registers can optionally contain the faulting
instruction on an illegal instruction exception. This patch adds support
for setting the stval and mtval registers.
The RISC-V spec states that "The stval register can optionally also be
used to return the faulting instruction bits on an illegal instruction
exception...". In this case we are always writing the value on an
illegal instruction.
This doesn't match all CPUs (some CPUs won't write the data), but in
QEMU let's just populate the value on illegal instructions. This won't
break any guest software, but will provide more information to guests.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211220064916.107241-4-alistair.francis@opensource.wdc.com
Commit: afe33262585565b64df706c62b4b0f6e0ad30c71
https://github.com/qemu/qemu/commit/afe33262585565b64df706c62b4b0f6e0ad30c71
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-01-07 (Fri, 07 Jan 2022)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/ldst_common.c.inc
M accel/tcg/user-exec.c
M disas/riscv.c
M hw/dma/sifive_pdma.c
M hw/intc/sifive_plic.c
M hw/riscv/microchip_pfsoc.c
M hw/riscv/opentitan.c
M hw/riscv/sifive_e.c
M hw/riscv/sifive_u.c
M include/disas/dis-asm.h
M include/exec/memop.h
M include/hw/riscv/virt.h
M include/qemu/int128.h
M include/tcg/tcg-op.h
M pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
M pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
M pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
M pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
M roms/opensbi
M target/alpha/translate.c
M target/arm/helper-a64.c
M target/arm/translate-a32.h
M target/arm/translate-a64.c
M target/arm/translate-neon.c
M target/arm/translate-sve.c
M target/arm/translate-vfp.c
M target/arm/translate.c
M target/cris/translate.c
M target/hppa/translate.c
M target/i386/tcg/mem_helper.c
M target/i386/tcg/translate.c
M target/m68k/op_helper.c
M target/mips/tcg/micromips_translate.c.inc
M target/mips/tcg/translate.c
M target/mips/tcg/tx79_translate.c
M target/ppc/translate.c
M target/ppc/translate/fixedpoint-impl.c.inc
M target/ppc/translate/fp-impl.c.inc
M target/ppc/translate/vsx-impl.c.inc
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/gdbstub.c
M target/riscv/helper.h
M target/riscv/insn16.decode
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rva.c.inc
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/insn_trans/trans_rvd.c.inc
M target/riscv/insn_trans/trans_rvh.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvm.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
A target/riscv/m128_helper.c
M target/riscv/machine.c
M target/riscv/meson.build
M target/riscv/op_helper.c
M target/riscv/translate.c
M target/s390x/tcg/insn-data.def
M target/s390x/tcg/mem_helper.c
M target/s390x/tcg/translate.c
M target/s390x/tcg/translate_vx.c.inc
M target/sh4/translate.c
M target/sparc/translate.c
M target/tricore/translate.c
M target/xtensa/translate.c
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci.c
A util/int128.c
M util/meson.build
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu into
staging
Second RISC-V PR for QEMU 7.0
- Fix illegal instruction when PMP is disabled
- SiFive PDMA 64-bit support
- SiFive PLIC cleanups
- Mark Hypervisor extension as non experimental
- Enable Hypervisor extension by default
- Support 32 cores on the virt machine
- Corrections for the Vector extension
- Experimental support for 128-bit CPUs
- stval and mtval support for illegal instructions
# gpg: Signature made Fri 07 Jan 2022 09:50:11 PM PST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>"
[undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu: (37 commits)
target/riscv: Implement the stval/mtval illegal instruction
target/riscv: Fixup setting GVA
target/riscv: Set the opcode in DisasContext
target/riscv: actual functions to realize crs 128-bit insns
target/riscv: modification of the trans_csrxx for 128-bit support
target/riscv: helper functions to wrap calls to 128-bit csr insns
target/riscv: adding high part of some csrs
target/riscv: support for 128-bit M extension
target/riscv: support for 128-bit arithmetic instructions
target/riscv: support for 128-bit shift instructions
target/riscv: support for 128-bit U-type instructions
target/riscv: support for 128-bit bitwise instructions
target/riscv: accessors to registers upper part and 128-bit load/store
target/riscv: moving some insns close to similar insns
target/riscv: setup everything for rv64 to support rv128 execution
target/riscv: array for the 64 upper bits of 128-bit registers
target/riscv: separation of bitwise logic and arithmetic helpers
target/riscv: additional macros to check instruction support
qemu/int128: addition of div/rem 128-bit operations
exec/memop: Adding signed quad and octo defines
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/d70075373af5...afe332625855