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[Qemu-commits] [qemu/qemu] 316717: ppc/pnv: Change the maximum of PHB3 d
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 316717: ppc/pnv: Change the maximum of PHB3 devices for Po... |
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Date: |
Tue, 04 Jan 2022 07:24:11 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 316717feb32ae5dc64802d5c3a7d1e2beac9f155
https://github.com/qemu/qemu/commit/316717feb32ae5dc64802d5c3a7d1e2beac9f155
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Change the maximum of PHB3 devices for Power8NVL
The POWER8 processors with a NVLink logic unit have 4 PHB3 devices per
chip.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211222063817.1541058-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 81fbb57b7b0feee2db38c7416366f5cfc109bb9a
https://github.com/qemu/qemu/commit/81fbb57b7b0feee2db38c7416366f5cfc109bb9a
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M hw/pci-host/pnv_phb4.c
Log Message:
-----------
ppc/pnv: Remove PHB4 reset handler
The PHB4 reset handler was preparing ground for PHB5 to set
appropriately the device id. We don't need it for the PHB4 since the
device id is already set in the root port complex. PH5 will introduce
its own.
"device-id" property is now useless. It should be removed.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211222063817.1541058-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c42b9c8b33e4334ba623c72408da06e96ead6f2c
https://github.com/qemu/qemu/commit/c42b9c8b33e4334ba623c72408da06e96ead6f2c
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M hw/pci-host/pnv_phb4.c
M hw/pci-host/pnv_phb4_pec.c
M include/hw/pci-host/pnv_phb4.h
Log Message:
-----------
ppc/pnv: Remove the PHB4 "device-id" property
It's unused.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211222063817.1541058-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: dec4e2897ca97dea6318e50c1dabb65905e40d9c
https://github.com/qemu/qemu/commit/dec4e2897ca97dea6318e50c1dabb65905e40d9c
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M hw/pci-host/pnv_phb3.c
Log Message:
-----------
pnv_phb3.c: do not set 'root-bus' as bus name
All pnv-phb3-root-bus buses are being created as 'root-bus'. This
makes it impossible to, for example, add a pnv-phb3-root-port in
a specific root bus, since they all have the same name. By default
the device will be parented by the pnv-phb3 device that precedeced it in
the QEMU command line.
Moreover, this doesn't all for custom bus naming. Libvirt, for instance,
likes to name these buses as 'pcie.N', where 'N' is the index value of
the controller in the domain XML, by using the 'id' command line
attribute. At this moment this is also being ignored - the created root
bus will always be named 'root-bus'.
This patch fixes both scenarios by removing the 'root-bus' name from the
pci_register_root_bus() call. If an "id" is provided, use that.
Otherwise use 'NULL' as bus name. The 'NULL' value will be handled in
qbus_init_internal() and it will defaulted as lowercase bus type + the
global bus_id value.
After this path we can define the bus name by using the 'id' attribute:
qemu-system-ppc64 -m 4G -machine powernv8,accel=tcg \
-device pnv-phb3,chip-id=0,index=1,id=pcie.0
dev: pnv-phb3, id "pcie.0"
index = 1 (0x1)
chip-id = 0 (0x0)
x-config-reg-migration-enabled = true
bypass-iommu = false
bus: pcie.0
type pnv-phb3-root-bus
And without an 'id' we will have the following default:
qemu-system-ppc64 -m 4G -machine powernv8,accel=tcg \
-device pnv-phb3,chip-id=0,index=1
dev: pnv-phb3, id ""
index = 1 (0x1)
chip-id = 0 (0x0)
x-config-reg-migration-enabled = true
bypass-iommu = false
bus: pnv-phb3-root-bus.0
type pnv-phb3-root-bus
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211228193806.1198496-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9747d061cab131efd1dcaa321848e5d8b48992b3
https://github.com/qemu/qemu/commit/9747d061cab131efd1dcaa321848e5d8b48992b3
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M hw/pci-host/pnv_phb4.c
Log Message:
-----------
pnv_phb4.c: do not set 'root-bus' as bus name
This change has the same motivation as the one done for pnv-phb3-root-bus
buses previously. Defaulting every bus to 'root-bus' makes it impossible to
attach
root ports to specific buses and it doesn't allow for custom bus
naming because we're ignoring the 'id' value when registering the root
bus.
After this patch, creating pnv-phb4 devices with 'id' being set will
result in the following qtree:
qemu-system-ppc64 -m 4G -machine powernv9,accel=tcg \
-device pnv-phb4,chip-id=0,index=0,id=pcie.0 \
-device pnv-phb4,chip-id=1,index=4,id=pcie.1
bus: main-system-bus
type System
dev: pnv-phb4, id "pcie.1"
index = 4 (0x4)
chip-id = 1 (0x1)
version = 704374636546 (0xa400000002)
device-id = 1217 (0x4c1)
x-config-reg-migration-enabled = true
bypass-iommu = false
bus: pcie.1
type pnv-phb4-root-bus
dev: pnv-phb4, id "pcie.0"
index = 0 (0x0)
chip-id = 0 (0x0)
version = 704374636546 (0xa400000002)
device-id = 1217 (0x4c1)
x-config-reg-migration-enabled = true
bypass-iommu = false
bus: pcie.0
type pnv-phb4-root-bus
And without setting any ids:
qemu-system-ppc64 -m 4G -machine powernv9,accel=tcg \
-device pnv-phb4,chip-id=0,index=0,id=pcie.0 \
-device pnv-phb4,chip-id=1,index=4,id=pcie.1
bus: main-system-bus
type System
dev: pnv-phb4, id ""
index = 4 (0x4)
chip-id = 1 (0x1)
version = 704374636546 (0xa400000002)
device-id = 1217 (0x4c1)
x-config-reg-migration-enabled = true
bypass-iommu = false
bus: pnv-phb4-root-bus.1
type pnv-phb4-root-bus
dev: pnv-phb4, id ""
index = 0 (0x0)
chip-id = 0 (0x0)
version = 704374636546 (0xa400000002)
device-id = 1217 (0x4c1)
x-config-reg-migration-enabled = true
bypass-iommu = false
bus: pnv-phb4-root-bus.0
type pnv-phb4-root-bus
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211228193806.1198496-17-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 932de569708e59eb74c6c56800a4eb8d764cc97d
https://github.com/qemu/qemu/commit/932de569708e59eb74c6c56800a4eb8d764cc97d
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M target/ppc/mmu-radix64.c
Log Message:
-----------
target/ppc: Improve logging in Radix MMU
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211222071002.1568894-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9b4eaee4d47c912eb1449953ba3258f11600153a
https://github.com/qemu/qemu/commit/9b4eaee4d47c912eb1449953ba3258f11600153a
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M target/ppc/mmu-radix64.c
M target/ppc/mmu-radix64.h
Log Message:
-----------
target/ppc: Check effective address validity
For Radix translation, the EA range is 64-bits. when EA(2:11) are
nonzero, a segment interrupt should occur.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Message-Id: <20211231073122.3183583-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 62e79ef9144d5b8bf89848a59ecb62fad2f52c1c
https://github.com/qemu/qemu/commit/62e79ef9144d5b8bf89848a59ecb62fad2f52c1c
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Remove static inline
The compiler should know better how to inline code if necessary.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220103063441.3424853-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6789f23b6484960b8665f6f661188dfecccdacb6
https://github.com/qemu/qemu/commit/6789f23b6484960b8665f6f661188dfecccdacb6
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Print out literal exception names in logs
It facilitates reading the logs when mask CPU_LOG_INT is activated. We
should do the same for error codes.
Cc: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211222064025.1541490-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220103063441.3424853-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: b3b5c5d38f42f74e8338d864e60f2f0754978131
https://github.com/qemu/qemu/commit/b3b5c5d38f42f74e8338d864e60f2f0754978131
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M hw/ppc/mpc8544_guts.c
M hw/ppc/ppc4xx_devs.c
M hw/ppc/ppc4xx_pci.c
M hw/ppc/trace-events
Log Message:
-----------
ppc/ppc4xx: Convert printfs()
Use a QEMU log primitive for errors and trace events for debug.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.drobear.id.au>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211222064025.1541490-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220103063441.3424853-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 56964585a051daf2f27a6e81adf87f58952b783a
https://github.com/qemu/qemu/commit/56964585a051daf2f27a6e81adf87f58952b783a
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
Log Message:
-----------
ppc/ppc405: Activate MMU logs
There is no need to deactivate MMU logging at compile time. Remove all
use of defines. Only keep DUMP_PAGE_TABLES for another series since
page tables could be dumped from the monitor.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211222064025.1541490-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220103063441.3424853-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: cbd8f17d16c890e6d9316627e2d4def6f965988d
https://github.com/qemu/qemu/commit/cbd8f17d16c890e6d9316627e2d4def6f965988d
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M hw/ppc/ppc.c
M hw/ppc/trace-events
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/helper.h
M target/ppc/spr_tcg.h
M target/ppc/timebase_helper.c
M target/ppc/translate.c
Log Message:
-----------
ppc/ppc405: Restore TCR and STR write handlers
The 405 timers were broken when booke support was added. Assumption
was made that the register numbers were the same but it's not :
SPR_BOOKE_TSR (0x150)
SPR_BOOKE_TCR (0x154)
SPR_40x_TSR (0x3D8)
SPR_40x_TCR (0x3DA)
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Fixes: ddd1055b07fd ("PPC: booke timers")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211222064025.1541490-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220103063441.3424853-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: b1273a5e13b7245e93f777c3eaa1c1477157b3de
https://github.com/qemu/qemu/commit/b1273a5e13b7245e93f777c3eaa1c1477157b3de
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M hw/ppc/ppc.c
Log Message:
-----------
ppc/ppc405: Rework ppc_40x_timers_init() to use a PowerPCCPU
This is a small cleanup to ease reading. It includes the removal of a
check done on the returned value of g_malloc0(), which can not fail.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211222064025.1541490-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220103063441.3424853-7-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c316203c1ee6f9a6c301a0a6767d27cbb6a65c46
https://github.com/qemu/qemu/commit/c316203c1ee6f9a6c301a0a6767d27cbb6a65c46
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Fix timer initialization
Timers are already initialized in ppc4xx_init(). No need to do it a
second time with a wrong set.
Fixes: d715ea961254 ("PPC: 405: Fix ppc405ep initialization")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211222064025.1541490-7-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220103063441.3424853-8-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: dd69d140cedc904f3491c17415f75d753c7f1be4
https://github.com/qemu/qemu/commit/dd69d140cedc904f3491c17415f75d753c7f1be4
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/spr_tcg.h
M target/ppc/translate.c
Log Message:
-----------
ppc/ppc405: Introduce a store helper for SPR_40x_PID
The PID SPR of the 405 CPU contains the translation ID of the TLB
which is a 8-bit field. Enforce the mask with a store helper.
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211222064025.1541490-8-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220103063441.3424853-9-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: fbe08667c5bd91395eea578398f07e83c768fa56
https://github.com/qemu/qemu/commit/fbe08667c5bd91395eea578398f07e83c768fa56
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
ppc/ppc405: Dump specific registers
Rework slightly ppc_cpu_dump_state() to replace the various 'if'
statements with a 'switch'.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211222064025.1541490-9-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220103063441.3424853-10-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 84ade98e87ea982ec6625ffd91058aaf443c206e
https://github.com/qemu/qemu/commit/84ade98e87ea982ec6625ffd91058aaf443c206e
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M target/ppc/fpu_helper.c
M tests/tcg/ppc64/Makefile.target
M tests/tcg/ppc64le/Makefile.target
A tests/tcg/ppc64le/non_signalling_xscv.c
Log Message:
-----------
target/ppc: do not silence snan in xscvspdpn
The non-signalling versions of VSX scalar convert to shorter/longer
precision insns doesn't silence SNaNs in the hardware. To better match
this behavior, use the non-arithmatic conversion of helper_todouble
instead of float32_to_float64. A test is added to prevent future
regressions.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211228120310.1957990-1-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 19e70626f8554245a30d3d46b613d80f2b670c04
https://github.com/qemu/qemu/commit/19e70626f8554245a30d3d46b613d80f2b670c04
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: powerpc_excp: Set alternate SRRs directly
There are currently only two interrupts that use alternate SRRs, so
let them write to them directly during the setup code.
No functional change intended.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20211229165751.3774248-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2541e686589a86167cbee98162d3fde2bbf67bc2
https://github.com/qemu/qemu/commit/2541e686589a86167cbee98162d3fde2bbf67bc2
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: powerpc_excp: Add excp_vectors bounds check
The next patch will start accessing the excp_vectors array earlier in
the function, so add a bounds check as first thing here.
This converts the empty return on POWERPC_EXCP_NONE to an error. This
exception number never reaches this function and if it does it
probably means something else went wrong up the line.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20211229165751.3774248-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: d1cbee61abd5ca76cd04886d066e18fcda8d1116
https://github.com/qemu/qemu/commit/d1cbee61abd5ca76cd04886d066e18fcda8d1116
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: powerpc_excp: Set vector earlier
None of the interrupt setup code touches 'vector', so we can move it
earlier in the function. This will allow us to later move the System
Call Vectored setup that is on the top level into the
POWERPC_EXCP_SYSCALL_VECTORED code block.
This patch also moves the verification for when 'excp' does not have
an address associated with it. We now bail a little earlier when that
is the case. This should not cause any visible effects.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20211229165751.3774248-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 5ac11b126d47755c39727cc772ee16cb49b3ade7
https://github.com/qemu/qemu/commit/5ac11b126d47755c39727cc772ee16cb49b3ade7
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: powerpc_excp: Move system call vectored code together
Now that 'vector' is known before calling the interrupt-specific setup
code, we can move all of the scv setup into one place.
No functional change intended.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211229165751.3774248-5-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 93130c8475692b1e52e3d3c3beedc3a79b4562d5
https://github.com/qemu/qemu/commit/93130c8475692b1e52e3d3c3beedc3a79b4562d5
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: powerpc_excp: Stop passing excp_model around
We can just access it directly in powerpc_excp.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
[ clg: Took into account removal of inline ]
Message-Id: <20211229165751.3774248-6-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6e8b990354d244ad5af40c747fdf3c008962b4e3
https://github.com/qemu/qemu/commit/6e8b990354d244ad5af40c747fdf3c008962b4e3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/helper_regs.c
M target/ppc/machine.c
M target/ppc/power8-pmu.c
M target/ppc/power8-pmu.h
Log Message:
-----------
target/ppc: Cache per-pmc insn and cycle count settings
This is the combination of frozen bit and counter type, on a per
counter basis. So far this is only used by HFLAGS_INSN_CNT, but
will be used more later.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
[danielhb: fixed PMC4 cyc_cnt shift, insn run latch code,
MMCR0_FC handling, "PMC[1-6]" comment]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220103224746.167831-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ffae5616c3677f7d6ad15267e6a15b895357b674
https://github.com/qemu/qemu/commit/ffae5616c3677f7d6ad15267e6a15b895357b674
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M target/ppc/power8-pmu.c
Log Message:
-----------
target/ppc: Rewrite pmu_increment_insns
Use the cached pmc_ins_cnt value. Unroll the loop over the
different PMC counters. Treat the PMC4 run-latch specially.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220103224746.167831-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: eec4dfdadbc68d2103a02e449618b191eb9c0886
https://github.com/qemu/qemu/commit/eec4dfdadbc68d2103a02e449618b191eb9c0886
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M target/ppc/power8-pmu.c
Log Message:
-----------
target/ppc: Use env->pnc_cyc_cnt
Use the cached pmc_cyc_cnt value in pmu_update_cycles
and pmc_update_overflow_timer. This leaves pmc_get_event
and pmc_is_inactive unused, so remove them.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220103224746.167831-4-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 0625c7760d5451d7436ef0738f763c6bb5141919
https://github.com/qemu/qemu/commit/0625c7760d5451d7436ef0738f763c6bb5141919
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M target/ppc/power8-pmu.c
Log Message:
-----------
target/ppc: do not call hreg_compute_hflags() in helper_store_mmcr0()
MMCR0 writes will change only MMCR0 bits which are used to calculate
HFLAGS_PMCC0, HFLAGS_PMCC1 and HFLAGS_INSN_CNT hflags. No other machine
register will be changed during this operation. This means that
hreg_compute_hflags() is overkill for what we need to do.
pmu_update_summaries() is already updating HFLAGS_INSN_CNT without
calling hreg_compure_hflags(). Let's do the same for the other 2 MMCR0
hflags.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220103224746.167831-5-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 67e41fe0cfb62e6cdfa659f0155417d17e5274ea
https://github.com/qemu/qemu/commit/67e41fe0cfb62e6cdfa659f0155417d17e5274ea
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-01-04 (Tue, 04 Jan 2022)
Changed paths:
M hw/pci-host/pnv_phb3.c
M hw/pci-host/pnv_phb4.c
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/mpc8544_guts.c
M hw/ppc/pnv.c
M hw/ppc/ppc.c
M hw/ppc/ppc405_uc.c
M hw/ppc/ppc4xx_devs.c
M hw/ppc/ppc4xx_pci.c
M hw/ppc/trace-events
M include/hw/pci-host/pnv_phb4.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/helper_regs.c
M target/ppc/machine.c
M target/ppc/mmu-radix64.c
M target/ppc/mmu-radix64.h
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
M target/ppc/power8-pmu.c
M target/ppc/power8-pmu.h
M target/ppc/spr_tcg.h
M target/ppc/timebase_helper.c
M target/ppc/translate.c
M tests/tcg/ppc64/Makefile.target
M tests/tcg/ppc64le/Makefile.target
A tests/tcg/ppc64le/non_signalling_xscv.c
Log Message:
-----------
Merge tag 'pull-ppc-20220104' of https://github.com/legoater/qemu into staging
ppc 7.0 queue:
* Cleanup of PowerNV PHBs (Daniel and Cedric)
* Cleanup and fixes for PPC405 machine (Cedric)
* Fix for xscvspdpn (Matheus)
* Rework of powerpc exception handling 1/n (Fabiano)
* Optimisation for PMU (Richard and Daniel)
# gpg: Signature made Mon 03 Jan 2022 11:04:06 PM PST
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-ppc-20220104' of https://github.com/legoater/qemu: (26 commits)
target/ppc: do not call hreg_compute_hflags() in helper_store_mmcr0()
target/ppc: Use env->pnc_cyc_cnt
target/ppc: Rewrite pmu_increment_insns
target/ppc: Cache per-pmc insn and cycle count settings
target/ppc: powerpc_excp: Stop passing excp_model around
target/ppc: powerpc_excp: Move system call vectored code together
target/ppc: powerpc_excp: Set vector earlier
target/ppc: powerpc_excp: Add excp_vectors bounds check
target/ppc: powerpc_excp: Set alternate SRRs directly
target/ppc: do not silence snan in xscvspdpn
ppc/ppc405: Dump specific registers
ppc/ppc405: Introduce a store helper for SPR_40x_PID
ppc/ppc405: Fix timer initialization
ppc/ppc405: Rework ppc_40x_timers_init() to use a PowerPCCPU
ppc/ppc405: Restore TCR and STR write handlers
ppc/ppc405: Activate MMU logs
ppc/ppc4xx: Convert printfs()
target/ppc: Print out literal exception names in logs
target/ppc: Remove static inline
target/ppc: Check effective address validity
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/b5a3d8bc9146...67e41fe0cfb6
- [Qemu-commits] [qemu/qemu] 316717: ppc/pnv: Change the maximum of PHB3 devices for Po...,
Richard Henderson <=