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[Qemu-commits] [qemu/qemu] 915f77: target/riscv: zfh: half-precision loa


From: Richard Henderson
Subject: [Qemu-commits] [qemu/qemu] 915f77: target/riscv: zfh: half-precision load and store
Date: Mon, 20 Dec 2021 10:26:48 -0800

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 915f77b2119952fc6d05ab64db4d749e6b5c196e
      
https://github.com/qemu/qemu/commit/915f77b2119952fc6d05ab64db4d749e6b5c196e
  Author: Kito Cheng <kito.cheng@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/insn32.decode
    A target/riscv/insn_trans/trans_rvzfh.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: zfh: half-precision load and store

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211210074329.5775-2-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 00c1899f123713bb0629d3994fd4be26d64aeb69
      
https://github.com/qemu/qemu/commit/00c1899f123713bb0629d3994fd4be26d64aeb69
  Author: Kito Cheng <kito.cheng@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/fpu_helper.c
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvzfh.c.inc
    M target/riscv/internals.h

  Log Message:
  -----------
  target/riscv: zfh: half-precision computational

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211210074329.5775-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7b03c8e5b5a07bc2d357438b4ee92b116afe8914
      
https://github.com/qemu/qemu/commit/7b03c8e5b5a07bc2d357438b4ee92b116afe8914
  Author: Kito Cheng <kito.cheng@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/fpu_helper.c
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvzfh.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: zfh: half-precision convert and move

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211210074329.5775-4-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 11f9c450a6772c095c5f9c40f5a08c2f8d15a9a1
      
https://github.com/qemu/qemu/commit/11f9c450a6772c095c5f9c40f5a08c2f8d15a9a1
  Author: Kito Cheng <kito.cheng@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/fpu_helper.c
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvzfh.c.inc

  Log Message:
  -----------
  target/riscv: zfh: half-precision floating-point compare

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211210074329.5775-5-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6bc6fc96d1c9628c4c3514d277e541429e5b0b80
      
https://github.com/qemu/qemu/commit/6bc6fc96d1c9628c4c3514d277e541429e5b0b80
  Author: Kito Cheng <kito.cheng@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/fpu_helper.c
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvzfh.c.inc

  Log Message:
  -----------
  target/riscv: zfh: half-precision floating-point classify

Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211210074329.5775-6-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 13fb8c7b4252872c1b07fac5f0ea9231480c8463
      
https://github.com/qemu/qemu/commit/13fb8c7b4252872c1b07fac5f0ea9231480c8463
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: zfh: add Zfh cpu property

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211210074329.5775-7-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2d258b428b4f61b71be823fe2a67e7a174078501
      
https://github.com/qemu/qemu/commit/2d258b428b4f61b71be823fe2a67e7a174078501
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/insn_trans/trans_rvzfh.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: zfh: implement zfhmin extension

Zfhmin extension is a subset of Zfh extension, consisting only of data
transfer and conversion instructions.

If enabled, only the following instructions from Zfh extension are
included:
  * flh, fsh, fmv.x.h, fmv.h.x, fcvt.s.h, fcvt.h.s
  * If D extension is present: fcvt.d.h, fcvt.h.d

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211210074329.5775-8-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e523773040ed914b60c8b68c25a96c88b2bb112a
      
https://github.com/qemu/qemu/commit/e523773040ed914b60c8b68c25a96c88b2bb112a
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: zfh: add Zfhmin cpu property

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211210074329.5775-9-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 9ec6622db30df1c00d863c1ffc33341f9e0a534d
      
https://github.com/qemu/qemu/commit/9ec6622db30df1c00d863c1ffc33341f9e0a534d
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: drop vector 0.7.1 and add 1.0 support

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20211210075704.23951-2-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 52561f2a808a16bde80c9a165f54e07df2e527a7
      
https://github.com/qemu/qemu/commit/52561f2a808a16bde80c9a165f54e07df2e527a7
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: Use FIELD_EX32() to extract wd field

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-3-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 61b4b69d122c055fbf6310e629f3f2d1e70c2599
      
https://github.com/qemu/qemu/commit/61b4b69d122c055fbf6310e629f3f2d1e70c2599
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: add mstatus VS field

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-4-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: c36b2f1a4d036dc105018c1af3f127a4d3333789
      
https://github.com/qemu/qemu/commit/c36b2f1a4d036dc105018c1af3f127a4d3333789
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-5-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 89a81e376a53c17b554d213302e678027c3ad60e
      
https://github.com/qemu/qemu/commit/89a81e376a53c17b554d213302e678027c3ad60e
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: add sstatus VS field

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-6-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7b07a37c2caad9252c6c5eec11ab9776826328ff
      
https://github.com/qemu/qemu/commit/7b07a37c2caad9252c6c5eec11ab9776826328ff
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: introduce writable misa.v field

Implementations may have a writable misa.v field. Analogous to the way
in which the floating-point unit is handled, the mstatus.vs field may
exist even if misa.v is clear.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-7-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8e1ee1fb571cbfa7d6897560fed3cd9f367058a1
      
https://github.com/qemu/qemu/commit/8e1ee1fb571cbfa7d6897560fed3cd9f367058a1
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: add translation-time vector context status

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-8-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 9bd291f6e3f8cccca73b58039744f926eb4ac457
      
https://github.com/qemu/qemu/commit/9bd291f6e3f8cccca73b58039744f926eb4ac457
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: remove rvv related codes from fcsr registers

* Remove VXRM and VXSAT fields from FCSR register as they are only
  presented in VCSR register.
* Remove RVV loose check in fs() predicate function.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-9-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4594fa5a96d07a5087df4437aed68dbe0136ca08
      
https://github.com/qemu/qemu/commit/4594fa5a96d07a5087df4437aed68dbe0136ca08
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: add vcsr register

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-10-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2e56505475cba574ff041cd9d57d417c7d705d24
      
https://github.com/qemu/qemu/commit/2e56505475cba574ff041cd9d57d417c7d705d24
  Author: Greentime Hu <greentime.hu@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: add vlenb register

Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-11-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6bc3dfa96de4173b12929824eaf80fc95d22ac28
      
https://github.com/qemu/qemu/commit/6bc3dfa96de4173b12929824eaf80fc95d22ac28
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers

If VS field is off, accessing vector csr registers should raise an
illegal-instruction exception.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-12-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f9298de51432148163d8ed9c2b15bc0096546c07
      
https://github.com/qemu/qemu/commit/f9298de51432148163d8ed9c2b15bc0096546c07
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/internals.h
    M target/riscv/translate.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: remove MLEN calculations

As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5).
Thus, remove all MLEN related calculations.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-13-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 33f1beaf12ebb835cd11a8be0bad229b2af166e2
      
https://github.com/qemu/qemu/commit/33f1beaf12ebb835cd11a8be0bad229b2af166e2
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/translate.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: add fractional LMUL

Introduce the concepts of fractional LMUL for RVV 1.0.
In RVV 1.0, LMUL bits are contiguous in vtype register.

Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600)
and MSTATUS_FS (0x6000) bits.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-14-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3479a814e4e61509dc48e7012b41ef4528ae42c5
      
https://github.com/qemu/qemu/commit/3479a814e4e61509dc48e7012b41ef4528ae42c5
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: add VMA and VTA

Introduce vma and vta fields in vtype register.

According to RVV 1.0 spec (section 3.3.3):

When a set is marked agnostic, the corresponding set of destination
elements in any vector or mask destination operand can either retain
the value they previously held, or are overwritten with 1s.

So, either vta/vma is set to undisturbed or agnostic, it's legal to
retain the inactive masked-off elements and tail elements' original
values unchanged. Therefore, besides declaring vta/vma fields in vtype
register, also remove all the tail elements clean functions in this
commit.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-15-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f31dacd720032419531589488020a61da2d58931
      
https://github.com/qemu/qemu/commit/f31dacd720032419531589488020a61da2d58931
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: rvv-1.0: update check functions

Update check functions with RVV 1.0 rules.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-16-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ff64fc91d1fdf8fe71394d81ba35f33410731d8e
      
https://github.com/qemu/qemu/commit/ff64fc91d1fdf8fe71394d81ba35f33410731d8e
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: introduce more imm value modes in translator functions

Immediate value in translator function is extended not only
zero-extended and sign-extended but with more modes to be applicable
with multiple formats of vector instructions.

* IMM_ZX:         Zero-extended
* IMM_SX:         Sign-extended
* IMM_TRUNC_SEW:  Truncate to log(SEW) bit
* IMM_TRUNC_2SEW: Truncate to log(2*SEW) bit

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-17-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 9b4a40a78603956344404c53cc355c2ea1ee70c3
      
https://github.com/qemu/qemu/commit/9b4a40a78603956344404c53cc355c2ea1ee70c3
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: rvv:1.0: add translation-time nan-box helper function

* Add fp16 nan-box check generator function, if a 16-bit input is not
  properly nanboxed, then the input is replaced with the default qnan.
* Add do_nanbox() helper function to utilize gen_check_nanbox_X() to
  generate the NaN-boxed floating-point values based on SEW setting.
* Apply nanbox helper in opfvf_trans().

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-18-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 57a2d89a82be6167a5200b5efa66b89686ce3141
      
https://github.com/qemu/qemu/commit/57a2d89a82be6167a5200b5efa66b89686ce3141
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: remove amo operations instructions

Vector AMOs are removed from standard vector extensions. Will be added
later as separate Zvamo extension, but will need a different encoding
from earlier proposal.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-19-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d9b7609a1fb237dd05fac4cfe5163429115c9c6d
      
https://github.com/qemu/qemu/commit/d9b7609a1fb237dd05fac4cfe5163429115c9c6d
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: configure instructions

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-20-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 79556fb6fa067922fb11d2a1209852900109c7ae
      
https://github.com/qemu/qemu/commit/79556fb6fa067922fb11d2a1209852900109c7ae
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: stride load and store instructions

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-21-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 08b9d0ed4aaff095a940280eba1321e3414dd5ac
      
https://github.com/qemu/qemu/commit/08b9d0ed4aaff095a940280eba1321e3414dd5ac
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: index load and store instructions

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-22-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 83fcd573b121939e850d9a9836e24298d189aa79
      
https://github.com/qemu/qemu/commit/83fcd573b121939e850d9a9836e24298d189aa79
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store 
insns

Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-23-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d3e5e2ff4fefde240120afaf86b032de19b0c722
      
https://github.com/qemu/qemu/commit/d3e5e2ff4fefde240120afaf86b032de19b0c722
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: fault-only-first unit stride load

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-24-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 30206bd8421d6ca17ba762ec18b039b12fcf6c9d
      
https://github.com/qemu/qemu/commit/30206bd8421d6ca17ba762ec18b039b12fcf6c9d
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: load/store whole register instructions

Add the following instructions:

* vl<nf>re<eew>.v
* vs<nf>r.v

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-25-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 5a9f8e15522819c3315544de5b13ca3a058a3132
      
https://github.com/qemu/qemu/commit/5a9f8e15522819c3315544de5b13ca3a058a3132
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: update vext_max_elems() for load/store insns

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-26-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a689a82b7fe65d1e09d27f7af1aead8a3ef471ce
      
https://github.com/qemu/qemu/commit/a689a82b7fe65d1e09d27f7af1aead8a3ef471ce
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: rvv-1.0: take fractional LMUL into vector max elements 
calculation

Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into
calculation for RVV 1.0.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-27-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 20f2079acfcab639d602c6a865bea43a3458b6e9
      
https://github.com/qemu/qemu/commit/20f2079acfcab639d602c6a865bea43a3458b6e9
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn32.decode

  Log Message:
  -----------
  target/riscv: rvv-1.0: floating-point square-root instruction

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-28-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0676d8e3dcd5c569a473bd90eb328b376b720ee0
      
https://github.com/qemu/qemu/commit/0676d8e3dcd5c569a473bd90eb328b376b720ee0
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn32.decode

  Log Message:
  -----------
  target/riscv: rvv-1.0: floating-point classify instructions

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-29-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0014aa741dedb1810d19a747c581d265b2b43298
      
https://github.com/qemu/qemu/commit/0014aa741dedb1810d19a747c581d265b2b43298
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: count population in mask instruction

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-30-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d71a24fc82c50f6fe0d86feece01a4ef43b1af82
      
https://github.com/qemu/qemu/commit/d71a24fc82c50f6fe0d86feece01a4ef43b1af82
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: find-first-set mask bit instruction

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-31-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 40c1495d69b17d34f073a5b92970b1b82e6ad7ef
      
https://github.com/qemu/qemu/commit/40c1495d69b17d34f073a5b92970b1b82e6ad7ef
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: set-X-first mask bit instructions

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-32-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ee17eaa120fc58a7737880b6a88114bee09dc616
      
https://github.com/qemu/qemu/commit/ee17eaa120fc58a7737880b6a88114bee09dc616
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: rvv-1.0: iota instruction

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-33-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f4f47e04de6185ddaf36e9b6ec34aa6e28923a07
      
https://github.com/qemu/qemu/commit/f4f47e04de6185ddaf36e9b6ec34aa6e28923a07
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn32.decode

  Log Message:
  -----------
  target/riscv: rvv-1.0: element index instruction

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-34-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 308ee805786a18f236daead36b11f53cd5017899
      
https://github.com/qemu/qemu/commit/308ee805786a18f236daead36b11f53cd5017899
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: rvv-1.0: allow load element with sign-extended

For some vector instructions (e.g. vmv.s.x), the element is loaded with
sign-extended.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-35-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 50bfb45b2c5bbbac8ffb7f051eb8c88128cae88d
      
https://github.com/qemu/qemu/commit/50bfb45b2c5bbbac8ffb7f051eb8c88128cae88d
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: register gather instructions

* Add vrgatherei16.vv instruction.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-36-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: dedc53cbc9f267e2ad037218ab07f9b4097efa65
      
https://github.com/qemu/qemu/commit/dedc53cbc9f267e2ad037218ab07f9b4097efa65
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: rvv-1.0: integer scalar move instructions

* Remove "vmv.s.x: dothing if rs1 == 0" constraint.
* Add vmv.x.s instruction.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-37-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: c4b3e46f0092ee9303787ae12ea9869eebcdc1ac
      
https://github.com/qemu/qemu/commit/c4b3e46f0092ee9303787ae12ea9869eebcdc1ac
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: rvv-1.0: floating-point move instruction

NaN-boxed the scalar floating-point register based on RVV 1.0's rules.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-38-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 5c4eb8fb5649f1fd137fb4d85a019332908fe066
      
https://github.com/qemu/qemu/commit/5c4eb8fb5649f1fd137fb4d85a019332908fe066
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/internals.h

  Log Message:
  -----------
  target/riscv: rvv-1.0: floating-point scalar move instructions

NaN-boxed the scalar floating-point register based on RVV 1.0's rules.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-39-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6b85975e11952447c3a301f33d2736c7890003dd
      
https://github.com/qemu/qemu/commit/6b85975e11952447c3a301f33d2736c7890003dd
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: rvv-1.0: whole register move instructions

Add the following instructions:

* vmv1r.v
* vmv2r.v
* vmv4r.v
* vmv8r.v

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-40-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: cd01340e75a700591de5715aa9f0aa226e5a0d34
      
https://github.com/qemu/qemu/commit/cd01340e75a700591de5715aa9f0aa226e5a0d34
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: integer extension instructions

Add the following instructions:

* vzext.vf2
* vzext.vf4
* vzext.vf8
* vsext.vf2
* vsext.vf4
* vsext.vf8

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-41-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8b99a110f7ff2c7e1d1294998226b84176384ef3
      
https://github.com/qemu/qemu/commit/8b99a110f7ff2c7e1d1294998226b84176384ef3
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: single-width averaging add and subtract instructions

Add the following instructions:

* vaaddu.vv
* vaaddu.vx
* vasubu.vv
* vasubu.vx

Remove the following instructions:

* vadd.vi

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-42-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a75ae09f2a7ed09c017f22f04bf71bd7b453fef7
      
https://github.com/qemu/qemu/commit/a75ae09f2a7ed09c017f22f04bf71bd7b453fef7
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: rvv-1.0: single-width bit shift instructions

Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-43-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: bb45485ad1721cbbe2b35f4daad83f847bed3d36
      
https://github.com/qemu/qemu/commit/bb45485ad1721cbbe2b35f4daad83f847bed3d36
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow

* Only do carry-in or borrow-in if is masked (vm=0).
* Remove clear function from helper functions as the tail elements
  are unchanged in RVV 1.0.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-44-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7daa5852bc25a843118a8bc46d8622d97bf5dab0
      
https://github.com/qemu/qemu/commit/7daa5852bc25a843118a8bc46d8622d97bf5dab0
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: narrowing integer right shift instructions

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-45-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f51c3cf1fa8681c45e3fb805a8136b58d093e988
      
https://github.com/qemu/qemu/commit/f51c3cf1fa8681c45e3fb805a8136b58d093e988
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn32.decode

  Log Message:
  -----------
  target/riscv: rvv-1.0: widening integer multiply-add instructions

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-46-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d6be7a35041b010f3bb01197bd7ff06258f70a7f
      
https://github.com/qemu/qemu/commit/d6be7a35041b010f3bb01197bd7ff06258f70a7f
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: rvv-1.0: single-width saturating add and subtract instructions

Sign-extend vsaddu.vi immediate value.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-47-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 063f8bbca05d859461809c68319517fe711e7bd8
      
https://github.com/qemu/qemu/commit/063f8bbca05d859461809c68319517fe711e7bd8
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: integer comparison instructions

* Sign-extend vmselu.vi and vmsgtu.vi immediate values.
* Remove "set tail elements to zeros" as tail elements can be unchanged
  for either VTA to have undisturbed or agnostic setting.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-48-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e70aa16e5e506475459cd524449e39484b4a984f
      
https://github.com/qemu/qemu/commit/e70aa16e5e506475459cd524449e39484b4a984f
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: floating-point compare instructions

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-49-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 50f6696c0f87372348b0760f858187cda3e7eb7f
      
https://github.com/qemu/qemu/commit/50f6696c0f87372348b0760f858187cda3e7eb7f
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: mask-register logical instructions

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-50-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6438ed61de22d9fb945452b5fe5b0ea594aa8ccc
      
https://github.com/qemu/qemu/commit/6438ed61de22d9fb945452b5fe5b0ea594aa8ccc
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: slide instructions

* Remove clear function from helper functions as the tail elements
  are unchanged in RVV 1.0.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-51-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8500d4ab2e9b50cb8a23b751e991e5ece6b0d0cc
      
https://github.com/qemu/qemu/commit/8500d4ab2e9b50cb8a23b751e991e5ece6b0d0cc
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: floating-point slide instructions

Add the following instructions:

* vfslide1up.vf
* vfslide1down.vf

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-52-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a70b3a73e75c6147ef4e08546038315d38c207a3
      
https://github.com/qemu/qemu/commit/a70b3a73e75c6147ef4e08546038315d38c207a3
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: narrowing fixed-point clip instructions

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-53-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 08b60eebc4ac101eef94639553766c3c1969c4d3
      
https://github.com/qemu/qemu/commit/08b60eebc4ac101eef94639553766c3c1969c4d3
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: single-width floating-point reduction

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-54-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: b8dd99f2d10311e0f4527507f56a1721e9c19505
      
https://github.com/qemu/qemu/commit/b8dd99f2d10311e0f4527507f56a1721e9c19505
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: rvv-1.0: widening floating-point reduction instructions

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-55-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 74eb7834bc7b2033d8caa308320afacbaff0525f
      
https://github.com/qemu/qemu/commit/74eb7834bc7b2033d8caa308320afacbaff0525f
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: rvv-1.0: single-width scaling shift instructions

log(SEW) truncate vssra.vi immediate value.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-56-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a12c812d19008e964e35df3ece84503c8d3221c0
      
https://github.com/qemu/qemu/commit/a12c812d19008e964e35df3ece84503c8d3221c0
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: remove widening saturating scaled multiply-add

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-57-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e29c5cefd81caae221ab1eb9cef18923cf0f01ba
      
https://github.com/qemu/qemu/commit/e29c5cefd81caae221ab1eb9cef18923cf0f01ba
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: remove vmford.vv and vmford.vf

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-58-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: c3536f2f5569da0072b9b42add093852f1469c37
      
https://github.com/qemu/qemu/commit/c3536f2f5569da0072b9b42add093852f1469c37
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: rvv-1.0: remove integer extract instruction

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-59-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 49c5611a9716963759d36b80b278d68e4335f9d7
      
https://github.com/qemu/qemu/commit/49c5611a9716963759d36b80b278d68e4335f9d7
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: floating-point min/max instructions

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-60-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 986c895de17c332c8cb241333dd478cb2ce8b8cc
      
https://github.com/qemu/qemu/commit/986c895de17c332c8cb241333dd478cb2ce8b8cc
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/fpu_helper.c
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/internals.h

  Log Message:
  -----------
  target/riscv: introduce floating-point rounding mode enum

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-61-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 900da87ab966654be76cc9c2fb860329cb423bd4
      
https://github.com/qemu/qemu/commit/900da87ab966654be76cc9c2fb860329cb423bd4
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: rvv-1.0: floating-point/integer type-convert instructions

Add the following instructions:

* vfcvt.rtz.xu.f.v
* vfcvt.rtz.x.f.v

Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding
modes.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-62-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3ce4c09df75529da0a5798279a01e24c02df15da
      
https://github.com/qemu/qemu/commit/3ce4c09df75529da0a5798279a01e24c02df15da
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: widening floating-point/integer type-convert

Add the following instructions:

* vfwcvt.rtz.xu.f.v
* vfwcvt.rtz.x.f.v

Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point
rounding modes.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-63-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 75804f71319706308dd48441b408abc09481c5ae
      
https://github.com/qemu/qemu/commit/75804f71319706308dd48441b408abc09481c5ae
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/fpu_helper.c
    M target/riscv/helper.h
    M target/riscv/internals.h
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: add "set round to odd" rounding mode helper function

helper_set_rounding_mode() is responsible for SIGILL, and "round to odd"
should be an interface private to translation, so add a new independent
helper_set_rod_rounding_mode().

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-64-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ff679b58e3efed7b03dcd08ea7f9018978a084e5
      
https://github.com/qemu/qemu/commit/ff679b58e3efed7b03dcd08ea7f9018978a084e5
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: narrowing floating-point/integer type-convert

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-65-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8a4b52575ab1793f5cc86ddd0b5e986799dfc615
      
https://github.com/qemu/qemu/commit/8a4b52575ab1793f5cc86ddd0b5e986799dfc615
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-66-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f714361ed79180a9780334cfe1b89b69f6c9bfe9
      
https://github.com/qemu/qemu/commit/f714361ed79180a9780334cfe1b89b69f6c9bfe9
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/csr.c
    M target/riscv/helper.h
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/translate.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: implement vstart CSR

* Update and check vstart value for vector instructions.
* Add whole register move instruction helper functions as we have to
  call helper function for case where vstart is not zero.
* Remove probe_pages() calls in vector load/store instructions
  (except fault-only-first loads) to raise the memory access exception
  at the exact processed vector element.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-67-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d6c4d3f2a693f4520ec72b0bd25be6ec03fee13a
      
https://github.com/qemu/qemu/commit/d6c4d3f2a693f4520ec72b0bd25be6ec03fee13a
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not 
valid

If the frm field contains an invalid rounding mode (101-111),
attempting to execute any vector floating-point instruction, even
those that do not depend on the rounding mode, will raise an illegal
instruction exception.

Call gen_set_rm() with DYN rounding mode to check and trigger illegal
instruction exception if frm field contains invalid value at run-time
for vector floating-point instructions.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-68-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 719d3561b269d880b2d31e64ed7632407952bad0
      
https://github.com/qemu/qemu/commit/719d3561b269d880b2d31e64ed7632407952bad0
  Author: Hsiangkai Wang <kai.wang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/gdbstub.c

  Log Message:
  -----------
  target/riscv: gdb: support vector registers for rv64 & rv32

Signed-off-by: Hsiangkai Wang <kai.wang@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-69-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e848a1e5632518647ac146d75b2fe006050ffb82
      
https://github.com/qemu/qemu/commit/e848a1e5632518647ac146d75b2fe006050ffb82
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: floating-point reciprocal square-root estimate 
instruction

Implement the floating-point reciprocal square-root estimate to 7 bits
instruction.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-70-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 55c35407c3706148761373aaa1d3350b57e86e8d
      
https://github.com/qemu/qemu/commit/55c35407c3706148761373aaa1d3350b57e86e8d
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: floating-point reciprocal estimate instruction

Implement the floating-point reciprocal estimate to 7 bits instruction.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-71-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6b5c8eb3e7de3c1b9dc2845b6b001ddd7d2eb359
      
https://github.com/qemu/qemu/commit/6b5c8eb3e7de3c1b9dc2845b6b001ddd7d2eb359
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn32.decode

  Log Message:
  -----------
  target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11

Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction.
vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-72-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 34a2c2d81ad94ff910051b8b93b4aaff895cec88
      
https://github.com/qemu/qemu/commit/34a2c2d81ad94ff910051b8b93b4aaff895cec88
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: rvv-1.0: add vsetivli instruction

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-73-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 5c89e9c0966dd423207bc477fcda9eb454d4308f
      
https://github.com/qemu/qemu/commit/5c89e9c0966dd423207bc477fcda9eb454d4308f
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()

Add supports of Vector unit-stride mask load/store instructions
(vlm.v, vsm.v), which has:
    evl (effective vector length) = ceil(env->vl / 8).

The new instructions operate the same as unmasked byte loads and stores.
Add evl parameter to reuse vext_ldst_us().

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-74-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 26086aea0d4f5575c0b66acd05ccb41349f8a32d
      
https://github.com/qemu/qemu/commit/26086aea0d4f5575c0b66acd05ccb41349f8a32d
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: add vector unit-stride mask load/store insns

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-75-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 9c0d2559deb11ee3d62153b5911e891d1b3679c1
      
https://github.com/qemu/qemu/commit/9c0d2559deb11ee3d62153b5911e891d1b3679c1
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and 
vmorn.mm

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-76-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 45ca2ca6bdfbfc802fde87721ff3d164ea970d3d
      
https://github.com/qemu/qemu/commit/45ca2ca6bdfbfc802fde87721ff3d164ea970d3d
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: rvv-1.0: update opivv_vadc_check() comment

Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is
moved to Section 11.4 in RVV v1.0 spec. Update the comment, no
functional changes.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-77-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: cc13aa3614519159e21f5bc1710c13fc79323853
      
https://github.com/qemu/qemu/commit/cc13aa3614519159e21f5bc1710c13fc79323853
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions

SEW has the limitation which cannot exceed ELEN.

Widening instructions have a destination group with EEW = 2*SEW
and narrowing instructions have a source operand with EEW = 2*SEW.
Both of the instructions have the limitation of: 2*SEW <= ELEN.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-78-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a7cad953fa2d5d4dd063a817c0d506eeb39310f5
      
https://github.com/qemu/qemu/commit/a7cad953fa2d5d4dd063a817c0d506eeb39310f5
  Author: Khem Raj <raj.khem@gmail.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M linux-user/riscv/target_syscall.h

  Log Message:
  -----------
  riscv: Set 5.4 as minimum kernel version for riscv32

5.4 is first stable API as far as rv32 is concerned see [1]

[1] 
https://sourceware.org/git/?p=glibc.git;a=commit;h=7a55dd3fb6d2c307a002a16776be84310b9c8989

Signed-off-by: Khem Raj <raj.khem@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bin.meng@windriver.com>
Message-Id: <20211216073111.2890607-1-raj.khem@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0643c12e4bc021ce5cb06aa1bfa02d25d8386b61
      
https://github.com/qemu/qemu/commit/0643c12e4bc021ce5cb06aa1bfa02d25d8386b61
  Author: Vineet Gupta <vineetg@rivosinc.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Enable bitmanip Zb[abcs] instructions

The bitmanip extension has now been ratified [1] and upstream tooling
(gcc/binutils) support it too, so move them out of experimental and also
enable by default (for better test exposure/coverage)

[1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211216051844.3921088-1-vineetg@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7e322a7f23a60b0e181b55ef722fdf390ec4e463
      
https://github.com/qemu/qemu/commit/7e322a7f23a60b0e181b55ef722fdf390ec4e463
  Author: Jessica Clarke <jrtc27@jrtc27.com>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M hw/riscv/boot.c

  Log Message:
  -----------
  hw/riscv: Use load address rather than entry point for fw_dynamic next_addr

The original BBL boot method had the kernel embedded as an opaque blob
that was blindly jumped to, which OpenSBI implemented as fw_payload.
OpenSBI then implemented fw_jump, which allows the payload to be loaded
elsewhere, but still blindly jumps to a fixed address at which the
kernel is to be loaded. Finally, OpenSBI introduced fw_dynamic, which
allows the previous stage to inform it where to jump to, rather than
having to blindly guess like fw_jump, or embed the payload as part of
the build like fw_payload. When used with an opaque binary (i.e. the
output of objcopy -O binary), it matches the behaviour of the previous
methods. However, when used with an ELF, QEMU currently passes on the
ELF's entry point address, which causes a discrepancy compared with all
the other boot methods if that entry point is not the first instruction
in the binary.

This difference specific to fw_dynamic with an ELF is not apparent when
booting Linux, since its entry point is the first instruction in the
binary. However, FreeBSD has a separate ELF entry point, following the
calling convention used by its bootloader, that differs from the first
instruction in the binary, used for the legacy SBI entry point, and so
the specific combination of QEMU's default fw_dynamic firmware with
booting FreeBSD as an ELF rather than a raw binary does not work.

Thus, align the behaviour when loading an ELF with the behaviour when
loading a raw binary; namely, use the base address of the loaded kernel
in place of the entry point.

The uImage code is left as-is in using the U-Boot header's entry point,
since the calling convention for that entry point is the same as the SBI
one and it mirrors what U-Boot will do.

Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211214032456.70203-1-jrtc27@jrtc27.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: c7d773ae49688463b59ade6989f8d612fecb973d
      
https://github.com/qemu/qemu/commit/c7d773ae49688463b59ade6989f8d612fecb973d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-12-20 (Mon, 20 Dec 2021)

  Changed paths:
    M hw/riscv/boot.c
    M linux-user/riscv/target_syscall.h
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/fpu_helper.c
    M target/riscv/gdbstub.c
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    A target/riscv/insn_trans/trans_rvzfh.c.inc
    M target/riscv/internals.h
    M target/riscv/translate.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  Merge tag 'pull-riscv-to-apply-20211220-1' of github.com:alistair23/qemu into 
staging

First RISC-V PR for QEMU 7.0

 - Add support for ratified 1.0 Vector extension
 - Drop support for draft 0.7.1 Vector extension
 - Support Zfhmin and Zfh extensions
 - Improve kernel loading for non-Linux platforms

# gpg: Signature made Sun 19 Dec 2021 08:56:08 PM PST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20211220-1' of github.com:alistair23/qemu: (88 
commits)
  hw/riscv: Use load address rather than entry point for fw_dynamic next_addr
  target/riscv: Enable bitmanip Zb[abcs] instructions
  riscv: Set 5.4 as minimum kernel version for riscv32
  target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions
  target/riscv: rvv-1.0: update opivv_vadc_check() comment
  target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and 
vmorn.mm
  target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
  target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
  target/riscv: rvv-1.0: add vsetivli instruction
  target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
  target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
  target/riscv: rvv-1.0: floating-point reciprocal square-root estimate 
instruction
  target/riscv: gdb: support vector registers for rv64 & rv32
  target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not 
valid
  target/riscv: rvv-1.0: implement vstart CSR
  target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
  target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
  target/riscv: add "set round to odd" rounding mode helper function
  target/riscv: rvv-1.0: widening floating-point/integer type-convert
  target/riscv: rvv-1.0: floating-point/integer type-convert instructions
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/212a33d3b0c6...c7d773ae4968



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